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drm/nouveau: port remainder of drm code, and rip out compat layer
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <core/engine.h>
31
32 #include <subdev/fb.h>
33 #include <subdev/vm.h>
34 #include <subdev/bar.h>
35
36 #include "nouveau_drm.h"
37 #include "nouveau_dma.h"
38 #include "nouveau_fence.h"
39
40 #include "nouveau_bo.h"
41 #include "nouveau_ttm.h"
42 #include "nouveau_gem.h"
43
44 /*
45 * NV10-NV40 tiling helpers
46 */
47
48 static void
49 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
50 u32 addr, u32 size, u32 pitch, u32 flags)
51 {
52 struct nouveau_drm *drm = nouveau_drm(dev);
53 int i = reg - drm->tile.reg;
54 struct nouveau_fb *pfb = nouveau_fb(drm->device);
55 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
56 struct nouveau_engine *engine;
57
58 nouveau_fence_unref(&reg->fence);
59
60 if (tile->pitch)
61 pfb->tile.fini(pfb, i, tile);
62
63 if (pitch)
64 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
65
66 pfb->tile.prog(pfb, i, tile);
67
68 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
69 engine->tile_prog(engine, i);
70 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
71 engine->tile_prog(engine, i);
72 }
73
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
76 {
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
79
80 spin_lock(&drm->tile.lock);
81
82 if (!tile->used &&
83 (!tile->fence || nouveau_fence_done(tile->fence)))
84 tile->used = true;
85 else
86 tile = NULL;
87
88 spin_unlock(&drm->tile.lock);
89 return tile;
90 }
91
92 static void
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct nouveau_fence *fence)
95 {
96 struct nouveau_drm *drm = nouveau_drm(dev);
97
98 if (tile) {
99 spin_lock(&drm->tile.lock);
100 if (fence) {
101 /* Mark it as pending. */
102 tile->fence = fence;
103 nouveau_fence_ref(fence);
104 }
105
106 tile->used = false;
107 spin_unlock(&drm->tile.lock);
108 }
109 }
110
111 static struct nouveau_drm_tile *
112 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
113 u32 size, u32 pitch, u32 flags)
114 {
115 struct nouveau_drm *drm = nouveau_drm(dev);
116 struct nouveau_fb *pfb = nouveau_fb(drm->device);
117 struct nouveau_drm_tile *tile, *found = NULL;
118 int i;
119
120 for (i = 0; i < pfb->tile.regions; i++) {
121 tile = nv10_bo_get_tile_region(dev, i);
122
123 if (pitch && !found) {
124 found = tile;
125 continue;
126
127 } else if (tile && pfb->tile.region[i].pitch) {
128 /* Kill an unused tile region. */
129 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
130 }
131
132 nv10_bo_put_tile_region(dev, tile, NULL);
133 }
134
135 if (found)
136 nv10_bo_update_tile_region(dev, found, addr, size,
137 pitch, flags);
138 return found;
139 }
140
141 static void
142 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
143 {
144 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
145 struct drm_device *dev = drm->dev;
146 struct nouveau_bo *nvbo = nouveau_bo(bo);
147
148 if (unlikely(nvbo->gem))
149 DRM_ERROR("bo %p still attached to GEM object\n", bo);
150 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
151 kfree(nvbo);
152 }
153
154 static void
155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
156 int *align, int *size)
157 {
158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
159 struct nouveau_device *device = nv_device(drm->device);
160
161 if (device->card_type < NV_50) {
162 if (nvbo->tile_mode) {
163 if (device->chipset >= 0x40) {
164 *align = 65536;
165 *size = roundup(*size, 64 * nvbo->tile_mode);
166
167 } else if (device->chipset >= 0x30) {
168 *align = 32768;
169 *size = roundup(*size, 64 * nvbo->tile_mode);
170
171 } else if (device->chipset >= 0x20) {
172 *align = 16384;
173 *size = roundup(*size, 64 * nvbo->tile_mode);
174
175 } else if (device->chipset >= 0x10) {
176 *align = 16384;
177 *size = roundup(*size, 32 * nvbo->tile_mode);
178 }
179 }
180 } else {
181 *size = roundup(*size, (1 << nvbo->page_shift));
182 *align = max((1 << nvbo->page_shift), *align);
183 }
184
185 *size = roundup(*size, PAGE_SIZE);
186 }
187
188 int
189 nouveau_bo_new(struct drm_device *dev, int size, int align,
190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
191 struct sg_table *sg,
192 struct nouveau_bo **pnvbo)
193 {
194 struct nouveau_drm *drm = nouveau_drm(dev);
195 struct nouveau_bo *nvbo;
196 size_t acc_size;
197 int ret;
198 int type = ttm_bo_type_device;
199
200 if (sg)
201 type = ttm_bo_type_sg;
202
203 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
204 if (!nvbo)
205 return -ENOMEM;
206 INIT_LIST_HEAD(&nvbo->head);
207 INIT_LIST_HEAD(&nvbo->entry);
208 INIT_LIST_HEAD(&nvbo->vma_list);
209 nvbo->tile_mode = tile_mode;
210 nvbo->tile_flags = tile_flags;
211 nvbo->bo.bdev = &drm->ttm.bdev;
212
213 nvbo->page_shift = 12;
214 if (drm->client.base.vm) {
215 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
216 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
217 }
218
219 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
220 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
221 nouveau_bo_placement_set(nvbo, flags, 0);
222
223 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
224 sizeof(struct nouveau_bo));
225
226 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
227 type, &nvbo->placement,
228 align >> PAGE_SHIFT, 0, false, NULL, acc_size, sg,
229 nouveau_bo_del_ttm);
230 if (ret) {
231 /* ttm will call nouveau_bo_del_ttm if it fails.. */
232 return ret;
233 }
234
235 *pnvbo = nvbo;
236 return 0;
237 }
238
239 static void
240 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
241 {
242 *n = 0;
243
244 if (type & TTM_PL_FLAG_VRAM)
245 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
246 if (type & TTM_PL_FLAG_TT)
247 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
248 if (type & TTM_PL_FLAG_SYSTEM)
249 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
250 }
251
252 static void
253 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
254 {
255 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
256 struct nouveau_fb *pfb = nouveau_fb(drm->device);
257 u32 vram_pages = pfb->ram.size >> PAGE_SHIFT;
258
259 if (nv_device(drm->device)->card_type == NV_10 &&
260 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
261 nvbo->bo.mem.num_pages < vram_pages / 4) {
262 /*
263 * Make sure that the color and depth buffers are handled
264 * by independent memory controller units. Up to a 9x
265 * speed up when alpha-blending and depth-test are enabled
266 * at the same time.
267 */
268 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
269 nvbo->placement.fpfn = vram_pages / 2;
270 nvbo->placement.lpfn = ~0;
271 } else {
272 nvbo->placement.fpfn = 0;
273 nvbo->placement.lpfn = vram_pages / 2;
274 }
275 }
276 }
277
278 void
279 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
280 {
281 struct ttm_placement *pl = &nvbo->placement;
282 uint32_t flags = TTM_PL_MASK_CACHING |
283 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
284
285 pl->placement = nvbo->placements;
286 set_placement_list(nvbo->placements, &pl->num_placement,
287 type, flags);
288
289 pl->busy_placement = nvbo->busy_placements;
290 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
291 type | busy, flags);
292
293 set_placement_range(nvbo, type);
294 }
295
296 int
297 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
298 {
299 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
300 struct ttm_buffer_object *bo = &nvbo->bo;
301 int ret;
302
303 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
304 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
305 1 << bo->mem.mem_type, memtype);
306 return -EINVAL;
307 }
308
309 if (nvbo->pin_refcnt++)
310 return 0;
311
312 ret = ttm_bo_reserve(bo, false, false, false, 0);
313 if (ret)
314 goto out;
315
316 nouveau_bo_placement_set(nvbo, memtype, 0);
317
318 ret = nouveau_bo_validate(nvbo, false, false, false);
319 if (ret == 0) {
320 switch (bo->mem.mem_type) {
321 case TTM_PL_VRAM:
322 drm->gem.vram_available -= bo->mem.size;
323 break;
324 case TTM_PL_TT:
325 drm->gem.gart_available -= bo->mem.size;
326 break;
327 default:
328 break;
329 }
330 }
331 ttm_bo_unreserve(bo);
332 out:
333 if (unlikely(ret))
334 nvbo->pin_refcnt--;
335 return ret;
336 }
337
338 int
339 nouveau_bo_unpin(struct nouveau_bo *nvbo)
340 {
341 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
342 struct ttm_buffer_object *bo = &nvbo->bo;
343 int ret;
344
345 if (--nvbo->pin_refcnt)
346 return 0;
347
348 ret = ttm_bo_reserve(bo, false, false, false, 0);
349 if (ret)
350 return ret;
351
352 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
353
354 ret = nouveau_bo_validate(nvbo, false, false, false);
355 if (ret == 0) {
356 switch (bo->mem.mem_type) {
357 case TTM_PL_VRAM:
358 drm->gem.vram_available += bo->mem.size;
359 break;
360 case TTM_PL_TT:
361 drm->gem.gart_available += bo->mem.size;
362 break;
363 default:
364 break;
365 }
366 }
367
368 ttm_bo_unreserve(bo);
369 return ret;
370 }
371
372 int
373 nouveau_bo_map(struct nouveau_bo *nvbo)
374 {
375 int ret;
376
377 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
378 if (ret)
379 return ret;
380
381 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
382 ttm_bo_unreserve(&nvbo->bo);
383 return ret;
384 }
385
386 void
387 nouveau_bo_unmap(struct nouveau_bo *nvbo)
388 {
389 if (nvbo)
390 ttm_bo_kunmap(&nvbo->kmap);
391 }
392
393 int
394 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
395 bool no_wait_reserve, bool no_wait_gpu)
396 {
397 int ret;
398
399 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
400 no_wait_reserve, no_wait_gpu);
401 if (ret)
402 return ret;
403
404 return 0;
405 }
406
407 u16
408 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
409 {
410 bool is_iomem;
411 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
412 mem = &mem[index];
413 if (is_iomem)
414 return ioread16_native((void __force __iomem *)mem);
415 else
416 return *mem;
417 }
418
419 void
420 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
421 {
422 bool is_iomem;
423 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
424 mem = &mem[index];
425 if (is_iomem)
426 iowrite16_native(val, (void __force __iomem *)mem);
427 else
428 *mem = val;
429 }
430
431 u32
432 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
433 {
434 bool is_iomem;
435 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
436 mem = &mem[index];
437 if (is_iomem)
438 return ioread32_native((void __force __iomem *)mem);
439 else
440 return *mem;
441 }
442
443 void
444 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
445 {
446 bool is_iomem;
447 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
448 mem = &mem[index];
449 if (is_iomem)
450 iowrite32_native(val, (void __force __iomem *)mem);
451 else
452 *mem = val;
453 }
454
455 static struct ttm_tt *
456 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
457 uint32_t page_flags, struct page *dummy_read)
458 {
459 struct nouveau_drm *drm = nouveau_bdev(bdev);
460 struct drm_device *dev = drm->dev;
461
462 if (drm->agp.stat == ENABLED) {
463 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
464 page_flags, dummy_read);
465 }
466
467 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
468 }
469
470 static int
471 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
472 {
473 /* We'll do this from user space. */
474 return 0;
475 }
476
477 static int
478 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
479 struct ttm_mem_type_manager *man)
480 {
481 struct nouveau_drm *drm = nouveau_bdev(bdev);
482
483 switch (type) {
484 case TTM_PL_SYSTEM:
485 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
486 man->available_caching = TTM_PL_MASK_CACHING;
487 man->default_caching = TTM_PL_FLAG_CACHED;
488 break;
489 case TTM_PL_VRAM:
490 if (nv_device(drm->device)->card_type >= NV_50) {
491 man->func = &nouveau_vram_manager;
492 man->io_reserve_fastpath = false;
493 man->use_io_reserve_lru = true;
494 } else {
495 man->func = &ttm_bo_manager_func;
496 }
497 man->flags = TTM_MEMTYPE_FLAG_FIXED |
498 TTM_MEMTYPE_FLAG_MAPPABLE;
499 man->available_caching = TTM_PL_FLAG_UNCACHED |
500 TTM_PL_FLAG_WC;
501 man->default_caching = TTM_PL_FLAG_WC;
502 break;
503 case TTM_PL_TT:
504 if (nv_device(drm->device)->card_type >= NV_50)
505 man->func = &nouveau_gart_manager;
506 else
507 if (drm->agp.stat != ENABLED)
508 man->func = &nv04_gart_manager;
509 else
510 man->func = &ttm_bo_manager_func;
511
512 if (drm->agp.stat == ENABLED) {
513 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
514 man->available_caching = TTM_PL_FLAG_UNCACHED |
515 TTM_PL_FLAG_WC;
516 man->default_caching = TTM_PL_FLAG_WC;
517 } else {
518 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
519 TTM_MEMTYPE_FLAG_CMA;
520 man->available_caching = TTM_PL_MASK_CACHING;
521 man->default_caching = TTM_PL_FLAG_CACHED;
522 }
523
524 break;
525 default:
526 return -EINVAL;
527 }
528 return 0;
529 }
530
531 static void
532 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
533 {
534 struct nouveau_bo *nvbo = nouveau_bo(bo);
535
536 switch (bo->mem.mem_type) {
537 case TTM_PL_VRAM:
538 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
539 TTM_PL_FLAG_SYSTEM);
540 break;
541 default:
542 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
543 break;
544 }
545
546 *pl = nvbo->placement;
547 }
548
549
550 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
551 * TTM_PL_{VRAM,TT} directly.
552 */
553
554 static int
555 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
556 struct nouveau_bo *nvbo, bool evict,
557 bool no_wait_reserve, bool no_wait_gpu,
558 struct ttm_mem_reg *new_mem)
559 {
560 struct nouveau_fence *fence = NULL;
561 int ret;
562
563 ret = nouveau_fence_new(chan, &fence);
564 if (ret)
565 return ret;
566
567 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
568 no_wait_reserve, no_wait_gpu, new_mem);
569 nouveau_fence_unref(&fence);
570 return ret;
571 }
572
573 static int
574 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
575 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
576 {
577 struct nouveau_mem *node = old_mem->mm_node;
578 int ret = RING_SPACE(chan, 10);
579 if (ret == 0) {
580 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
581 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
582 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
583 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
584 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
585 OUT_RING (chan, PAGE_SIZE);
586 OUT_RING (chan, PAGE_SIZE);
587 OUT_RING (chan, PAGE_SIZE);
588 OUT_RING (chan, new_mem->num_pages);
589 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
590 }
591 return ret;
592 }
593
594 static int
595 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
596 {
597 int ret = RING_SPACE(chan, 2);
598 if (ret == 0) {
599 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
600 OUT_RING (chan, handle);
601 }
602 return ret;
603 }
604
605 static int
606 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
607 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
608 {
609 struct nouveau_mem *node = old_mem->mm_node;
610 u64 src_offset = node->vma[0].offset;
611 u64 dst_offset = node->vma[1].offset;
612 u32 page_count = new_mem->num_pages;
613 int ret;
614
615 page_count = new_mem->num_pages;
616 while (page_count) {
617 int line_count = (page_count > 8191) ? 8191 : page_count;
618
619 ret = RING_SPACE(chan, 11);
620 if (ret)
621 return ret;
622
623 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
624 OUT_RING (chan, upper_32_bits(src_offset));
625 OUT_RING (chan, lower_32_bits(src_offset));
626 OUT_RING (chan, upper_32_bits(dst_offset));
627 OUT_RING (chan, lower_32_bits(dst_offset));
628 OUT_RING (chan, PAGE_SIZE);
629 OUT_RING (chan, PAGE_SIZE);
630 OUT_RING (chan, PAGE_SIZE);
631 OUT_RING (chan, line_count);
632 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
633 OUT_RING (chan, 0x00000110);
634
635 page_count -= line_count;
636 src_offset += (PAGE_SIZE * line_count);
637 dst_offset += (PAGE_SIZE * line_count);
638 }
639
640 return 0;
641 }
642
643 static int
644 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
645 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
646 {
647 struct nouveau_mem *node = old_mem->mm_node;
648 u64 src_offset = node->vma[0].offset;
649 u64 dst_offset = node->vma[1].offset;
650 u32 page_count = new_mem->num_pages;
651 int ret;
652
653 page_count = new_mem->num_pages;
654 while (page_count) {
655 int line_count = (page_count > 2047) ? 2047 : page_count;
656
657 ret = RING_SPACE(chan, 12);
658 if (ret)
659 return ret;
660
661 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
662 OUT_RING (chan, upper_32_bits(dst_offset));
663 OUT_RING (chan, lower_32_bits(dst_offset));
664 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
665 OUT_RING (chan, upper_32_bits(src_offset));
666 OUT_RING (chan, lower_32_bits(src_offset));
667 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
668 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
669 OUT_RING (chan, PAGE_SIZE); /* line_length */
670 OUT_RING (chan, line_count);
671 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
672 OUT_RING (chan, 0x00100110);
673
674 page_count -= line_count;
675 src_offset += (PAGE_SIZE * line_count);
676 dst_offset += (PAGE_SIZE * line_count);
677 }
678
679 return 0;
680 }
681
682 static int
683 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
684 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
685 {
686 struct nouveau_mem *node = old_mem->mm_node;
687 u64 src_offset = node->vma[0].offset;
688 u64 dst_offset = node->vma[1].offset;
689 u32 page_count = new_mem->num_pages;
690 int ret;
691
692 page_count = new_mem->num_pages;
693 while (page_count) {
694 int line_count = (page_count > 8191) ? 8191 : page_count;
695
696 ret = RING_SPACE(chan, 11);
697 if (ret)
698 return ret;
699
700 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
701 OUT_RING (chan, upper_32_bits(src_offset));
702 OUT_RING (chan, lower_32_bits(src_offset));
703 OUT_RING (chan, upper_32_bits(dst_offset));
704 OUT_RING (chan, lower_32_bits(dst_offset));
705 OUT_RING (chan, PAGE_SIZE);
706 OUT_RING (chan, PAGE_SIZE);
707 OUT_RING (chan, PAGE_SIZE);
708 OUT_RING (chan, line_count);
709 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
710 OUT_RING (chan, 0x00000110);
711
712 page_count -= line_count;
713 src_offset += (PAGE_SIZE * line_count);
714 dst_offset += (PAGE_SIZE * line_count);
715 }
716
717 return 0;
718 }
719
720 static int
721 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
722 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
723 {
724 struct nouveau_mem *node = old_mem->mm_node;
725 int ret = RING_SPACE(chan, 7);
726 if (ret == 0) {
727 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
728 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
729 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
730 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
731 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
732 OUT_RING (chan, 0x00000000 /* COPY */);
733 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
734 }
735 return ret;
736 }
737
738 static int
739 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
740 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
741 {
742 struct nouveau_mem *node = old_mem->mm_node;
743 int ret = RING_SPACE(chan, 7);
744 if (ret == 0) {
745 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
746 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
747 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
748 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
749 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
750 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
751 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
752 }
753 return ret;
754 }
755
756 static int
757 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
758 {
759 int ret = RING_SPACE(chan, 6);
760 if (ret == 0) {
761 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
762 OUT_RING (chan, handle);
763 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
764 OUT_RING (chan, NvNotify0);
765 OUT_RING (chan, NvDmaFB);
766 OUT_RING (chan, NvDmaFB);
767 }
768
769 return ret;
770 }
771
772 static int
773 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
774 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
775 {
776 struct nouveau_mem *node = old_mem->mm_node;
777 struct nouveau_bo *nvbo = nouveau_bo(bo);
778 u64 length = (new_mem->num_pages << PAGE_SHIFT);
779 u64 src_offset = node->vma[0].offset;
780 u64 dst_offset = node->vma[1].offset;
781 int ret;
782
783 while (length) {
784 u32 amount, stride, height;
785
786 amount = min(length, (u64)(4 * 1024 * 1024));
787 stride = 16 * 4;
788 height = amount / stride;
789
790 if (new_mem->mem_type == TTM_PL_VRAM &&
791 nouveau_bo_tile_layout(nvbo)) {
792 ret = RING_SPACE(chan, 8);
793 if (ret)
794 return ret;
795
796 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
797 OUT_RING (chan, 0);
798 OUT_RING (chan, 0);
799 OUT_RING (chan, stride);
800 OUT_RING (chan, height);
801 OUT_RING (chan, 1);
802 OUT_RING (chan, 0);
803 OUT_RING (chan, 0);
804 } else {
805 ret = RING_SPACE(chan, 2);
806 if (ret)
807 return ret;
808
809 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
810 OUT_RING (chan, 1);
811 }
812 if (old_mem->mem_type == TTM_PL_VRAM &&
813 nouveau_bo_tile_layout(nvbo)) {
814 ret = RING_SPACE(chan, 8);
815 if (ret)
816 return ret;
817
818 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
819 OUT_RING (chan, 0);
820 OUT_RING (chan, 0);
821 OUT_RING (chan, stride);
822 OUT_RING (chan, height);
823 OUT_RING (chan, 1);
824 OUT_RING (chan, 0);
825 OUT_RING (chan, 0);
826 } else {
827 ret = RING_SPACE(chan, 2);
828 if (ret)
829 return ret;
830
831 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
832 OUT_RING (chan, 1);
833 }
834
835 ret = RING_SPACE(chan, 14);
836 if (ret)
837 return ret;
838
839 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
840 OUT_RING (chan, upper_32_bits(src_offset));
841 OUT_RING (chan, upper_32_bits(dst_offset));
842 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
843 OUT_RING (chan, lower_32_bits(src_offset));
844 OUT_RING (chan, lower_32_bits(dst_offset));
845 OUT_RING (chan, stride);
846 OUT_RING (chan, stride);
847 OUT_RING (chan, stride);
848 OUT_RING (chan, height);
849 OUT_RING (chan, 0x00000101);
850 OUT_RING (chan, 0x00000000);
851 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
852 OUT_RING (chan, 0);
853
854 length -= amount;
855 src_offset += amount;
856 dst_offset += amount;
857 }
858
859 return 0;
860 }
861
862 static int
863 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
864 {
865 int ret = RING_SPACE(chan, 4);
866 if (ret == 0) {
867 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
868 OUT_RING (chan, handle);
869 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
870 OUT_RING (chan, NvNotify0);
871 }
872
873 return ret;
874 }
875
876 static inline uint32_t
877 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
878 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
879 {
880 if (mem->mem_type == TTM_PL_TT)
881 return NvDmaTT;
882 return NvDmaFB;
883 }
884
885 static int
886 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
887 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
888 {
889 u32 src_offset = old_mem->start << PAGE_SHIFT;
890 u32 dst_offset = new_mem->start << PAGE_SHIFT;
891 u32 page_count = new_mem->num_pages;
892 int ret;
893
894 ret = RING_SPACE(chan, 3);
895 if (ret)
896 return ret;
897
898 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
899 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
900 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
901
902 page_count = new_mem->num_pages;
903 while (page_count) {
904 int line_count = (page_count > 2047) ? 2047 : page_count;
905
906 ret = RING_SPACE(chan, 11);
907 if (ret)
908 return ret;
909
910 BEGIN_NV04(chan, NvSubCopy,
911 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
912 OUT_RING (chan, src_offset);
913 OUT_RING (chan, dst_offset);
914 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
915 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
916 OUT_RING (chan, PAGE_SIZE); /* line_length */
917 OUT_RING (chan, line_count);
918 OUT_RING (chan, 0x00000101);
919 OUT_RING (chan, 0x00000000);
920 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
921 OUT_RING (chan, 0);
922
923 page_count -= line_count;
924 src_offset += (PAGE_SIZE * line_count);
925 dst_offset += (PAGE_SIZE * line_count);
926 }
927
928 return 0;
929 }
930
931 static int
932 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
933 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
934 {
935 struct nouveau_mem *node = mem->mm_node;
936 int ret;
937
938 ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages <<
939 PAGE_SHIFT, node->page_shift,
940 NV_MEM_ACCESS_RW, vma);
941 if (ret)
942 return ret;
943
944 if (mem->mem_type == TTM_PL_VRAM)
945 nouveau_vm_map(vma, node);
946 else
947 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
948
949 return 0;
950 }
951
952 static int
953 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
954 bool no_wait_reserve, bool no_wait_gpu,
955 struct ttm_mem_reg *new_mem)
956 {
957 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
958 struct nouveau_channel *chan = chan = drm->channel;
959 struct nouveau_bo *nvbo = nouveau_bo(bo);
960 struct ttm_mem_reg *old_mem = &bo->mem;
961 int ret;
962
963 mutex_lock(&chan->cli->mutex);
964
965 /* create temporary vmas for the transfer and attach them to the
966 * old nouveau_mem node, these will get cleaned up after ttm has
967 * destroyed the ttm_mem_reg
968 */
969 if (nv_device(drm->device)->card_type >= NV_50) {
970 struct nouveau_mem *node = old_mem->mm_node;
971
972 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
973 if (ret)
974 goto out;
975
976 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
977 if (ret)
978 goto out;
979 }
980
981 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
982 if (ret == 0) {
983 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
984 no_wait_reserve,
985 no_wait_gpu, new_mem);
986 }
987
988 out:
989 mutex_unlock(&chan->cli->mutex);
990 return ret;
991 }
992
993 void
994 nouveau_bo_move_init(struct nouveau_channel *chan)
995 {
996 struct nouveau_cli *cli = chan->cli;
997 struct nouveau_drm *drm = chan->drm;
998 static const struct {
999 const char *name;
1000 int engine;
1001 u32 oclass;
1002 int (*exec)(struct nouveau_channel *,
1003 struct ttm_buffer_object *,
1004 struct ttm_mem_reg *, struct ttm_mem_reg *);
1005 int (*init)(struct nouveau_channel *, u32 handle);
1006 } _methods[] = {
1007 { "COPY", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1008 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1009 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1010 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1011 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1012 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1013 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1014 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1015 {},
1016 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1017 }, *mthd = _methods;
1018 const char *name = "CPU";
1019 int ret;
1020
1021 do {
1022 struct nouveau_object *object;
1023 u32 handle = (mthd->engine << 16) | mthd->oclass;
1024
1025 ret = nouveau_object_new(nv_object(cli), chan->handle, handle,
1026 mthd->oclass, NULL, 0, &object);
1027 if (ret == 0) {
1028 ret = mthd->init(chan, handle);
1029 if (ret) {
1030 nouveau_object_del(nv_object(cli),
1031 chan->handle, handle);
1032 continue;
1033 }
1034
1035 drm->ttm.move = mthd->exec;
1036 name = mthd->name;
1037 break;
1038 }
1039 } while ((++mthd)->exec);
1040
1041 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1042 }
1043
1044 static int
1045 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1046 bool no_wait_reserve, bool no_wait_gpu,
1047 struct ttm_mem_reg *new_mem)
1048 {
1049 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1050 struct ttm_placement placement;
1051 struct ttm_mem_reg tmp_mem;
1052 int ret;
1053
1054 placement.fpfn = placement.lpfn = 0;
1055 placement.num_placement = placement.num_busy_placement = 1;
1056 placement.placement = placement.busy_placement = &placement_memtype;
1057
1058 tmp_mem = *new_mem;
1059 tmp_mem.mm_node = NULL;
1060 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
1061 if (ret)
1062 return ret;
1063
1064 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1065 if (ret)
1066 goto out;
1067
1068 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
1069 if (ret)
1070 goto out;
1071
1072 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
1073 out:
1074 ttm_bo_mem_put(bo, &tmp_mem);
1075 return ret;
1076 }
1077
1078 static int
1079 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1080 bool no_wait_reserve, bool no_wait_gpu,
1081 struct ttm_mem_reg *new_mem)
1082 {
1083 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1084 struct ttm_placement placement;
1085 struct ttm_mem_reg tmp_mem;
1086 int ret;
1087
1088 placement.fpfn = placement.lpfn = 0;
1089 placement.num_placement = placement.num_busy_placement = 1;
1090 placement.placement = placement.busy_placement = &placement_memtype;
1091
1092 tmp_mem = *new_mem;
1093 tmp_mem.mm_node = NULL;
1094 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
1095 if (ret)
1096 return ret;
1097
1098 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
1099 if (ret)
1100 goto out;
1101
1102 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
1103 if (ret)
1104 goto out;
1105
1106 out:
1107 ttm_bo_mem_put(bo, &tmp_mem);
1108 return ret;
1109 }
1110
1111 static void
1112 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1113 {
1114 struct nouveau_bo *nvbo = nouveau_bo(bo);
1115 struct nouveau_vma *vma;
1116
1117 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1118 if (bo->destroy != nouveau_bo_del_ttm)
1119 return;
1120
1121 list_for_each_entry(vma, &nvbo->vma_list, head) {
1122 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1123 nouveau_vm_map(vma, new_mem->mm_node);
1124 } else
1125 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1126 nvbo->page_shift == vma->vm->vmm->spg_shift) {
1127 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1128 nouveau_vm_map_sg_table(vma, 0, new_mem->
1129 num_pages << PAGE_SHIFT,
1130 new_mem->mm_node);
1131 else
1132 nouveau_vm_map_sg(vma, 0, new_mem->
1133 num_pages << PAGE_SHIFT,
1134 new_mem->mm_node);
1135 } else {
1136 nouveau_vm_unmap(vma);
1137 }
1138 }
1139 }
1140
1141 static int
1142 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1143 struct nouveau_drm_tile **new_tile)
1144 {
1145 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1146 struct drm_device *dev = drm->dev;
1147 struct nouveau_bo *nvbo = nouveau_bo(bo);
1148 u64 offset = new_mem->start << PAGE_SHIFT;
1149
1150 *new_tile = NULL;
1151 if (new_mem->mem_type != TTM_PL_VRAM)
1152 return 0;
1153
1154 if (nv_device(drm->device)->card_type >= NV_10) {
1155 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1156 nvbo->tile_mode,
1157 nvbo->tile_flags);
1158 }
1159
1160 return 0;
1161 }
1162
1163 static void
1164 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1165 struct nouveau_drm_tile *new_tile,
1166 struct nouveau_drm_tile **old_tile)
1167 {
1168 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1169 struct drm_device *dev = drm->dev;
1170
1171 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1172 *old_tile = new_tile;
1173 }
1174
1175 static int
1176 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1177 bool no_wait_reserve, bool no_wait_gpu,
1178 struct ttm_mem_reg *new_mem)
1179 {
1180 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1181 struct nouveau_bo *nvbo = nouveau_bo(bo);
1182 struct ttm_mem_reg *old_mem = &bo->mem;
1183 struct nouveau_drm_tile *new_tile = NULL;
1184 int ret = 0;
1185
1186 if (nv_device(drm->device)->card_type < NV_50) {
1187 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1188 if (ret)
1189 return ret;
1190 }
1191
1192 /* Fake bo copy. */
1193 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1194 BUG_ON(bo->mem.mm_node != NULL);
1195 bo->mem = *new_mem;
1196 new_mem->mm_node = NULL;
1197 goto out;
1198 }
1199
1200 /* CPU copy if we have no accelerated method available */
1201 if (!drm->ttm.move) {
1202 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1203 goto out;
1204 }
1205
1206 /* Hardware assisted copy. */
1207 if (new_mem->mem_type == TTM_PL_SYSTEM)
1208 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1209 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1210 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1211 else
1212 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1213
1214 if (!ret)
1215 goto out;
1216
1217 /* Fallback to software copy. */
1218 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1219
1220 out:
1221 if (nv_device(drm->device)->card_type < NV_50) {
1222 if (ret)
1223 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1224 else
1225 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1226 }
1227
1228 return ret;
1229 }
1230
1231 static int
1232 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1233 {
1234 return 0;
1235 }
1236
1237 static int
1238 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1239 {
1240 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1241 struct nouveau_drm *drm = nouveau_bdev(bdev);
1242 struct drm_device *dev = drm->dev;
1243 int ret;
1244
1245 mem->bus.addr = NULL;
1246 mem->bus.offset = 0;
1247 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1248 mem->bus.base = 0;
1249 mem->bus.is_iomem = false;
1250 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1251 return -EINVAL;
1252 switch (mem->mem_type) {
1253 case TTM_PL_SYSTEM:
1254 /* System memory */
1255 return 0;
1256 case TTM_PL_TT:
1257 #if __OS_HAS_AGP
1258 if (drm->agp.stat == ENABLED) {
1259 mem->bus.offset = mem->start << PAGE_SHIFT;
1260 mem->bus.base = drm->agp.base;
1261 mem->bus.is_iomem = true;
1262 }
1263 #endif
1264 break;
1265 case TTM_PL_VRAM:
1266 mem->bus.offset = mem->start << PAGE_SHIFT;
1267 mem->bus.base = pci_resource_start(dev->pdev, 1);
1268 mem->bus.is_iomem = true;
1269 if (nv_device(drm->device)->card_type >= NV_50) {
1270 struct nouveau_bar *bar = nouveau_bar(drm->device);
1271 struct nouveau_mem *node = mem->mm_node;
1272
1273 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1274 &node->bar_vma);
1275 if (ret)
1276 return ret;
1277
1278 mem->bus.offset = node->bar_vma.offset;
1279 }
1280 break;
1281 default:
1282 return -EINVAL;
1283 }
1284 return 0;
1285 }
1286
1287 static void
1288 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1289 {
1290 struct nouveau_drm *drm = nouveau_bdev(bdev);
1291 struct nouveau_bar *bar = nouveau_bar(drm->device);
1292 struct nouveau_mem *node = mem->mm_node;
1293
1294 if (!node->bar_vma.node)
1295 return;
1296
1297 bar->unmap(bar, &node->bar_vma);
1298 }
1299
1300 static int
1301 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1302 {
1303 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1304 struct nouveau_bo *nvbo = nouveau_bo(bo);
1305 struct nouveau_device *device = nv_device(drm->device);
1306 u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT;
1307
1308 /* as long as the bo isn't in vram, and isn't tiled, we've got
1309 * nothing to do here.
1310 */
1311 if (bo->mem.mem_type != TTM_PL_VRAM) {
1312 if (nv_device(drm->device)->card_type < NV_50 ||
1313 !nouveau_bo_tile_layout(nvbo))
1314 return 0;
1315 }
1316
1317 /* make sure bo is in mappable vram */
1318 if (bo->mem.start + bo->mem.num_pages < mappable)
1319 return 0;
1320
1321
1322 nvbo->placement.fpfn = 0;
1323 nvbo->placement.lpfn = mappable;
1324 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1325 return nouveau_bo_validate(nvbo, false, true, false);
1326 }
1327
1328 static int
1329 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1330 {
1331 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1332 struct nouveau_drm *drm;
1333 struct drm_device *dev;
1334 unsigned i;
1335 int r;
1336 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1337
1338 if (ttm->state != tt_unpopulated)
1339 return 0;
1340
1341 if (slave && ttm->sg) {
1342 /* make userspace faulting work */
1343 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1344 ttm_dma->dma_address, ttm->num_pages);
1345 ttm->state = tt_unbound;
1346 return 0;
1347 }
1348
1349 drm = nouveau_bdev(ttm->bdev);
1350 dev = drm->dev;
1351
1352 #if __OS_HAS_AGP
1353 if (drm->agp.stat == ENABLED) {
1354 return ttm_agp_tt_populate(ttm);
1355 }
1356 #endif
1357
1358 #ifdef CONFIG_SWIOTLB
1359 if (swiotlb_nr_tbl()) {
1360 return ttm_dma_populate((void *)ttm, dev->dev);
1361 }
1362 #endif
1363
1364 r = ttm_pool_populate(ttm);
1365 if (r) {
1366 return r;
1367 }
1368
1369 for (i = 0; i < ttm->num_pages; i++) {
1370 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1371 0, PAGE_SIZE,
1372 PCI_DMA_BIDIRECTIONAL);
1373 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1374 while (--i) {
1375 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1376 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1377 ttm_dma->dma_address[i] = 0;
1378 }
1379 ttm_pool_unpopulate(ttm);
1380 return -EFAULT;
1381 }
1382 }
1383 return 0;
1384 }
1385
1386 static void
1387 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1388 {
1389 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1390 struct nouveau_drm *drm;
1391 struct drm_device *dev;
1392 unsigned i;
1393 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1394
1395 if (slave)
1396 return;
1397
1398 drm = nouveau_bdev(ttm->bdev);
1399 dev = drm->dev;
1400
1401 #if __OS_HAS_AGP
1402 if (drm->agp.stat == ENABLED) {
1403 ttm_agp_tt_unpopulate(ttm);
1404 return;
1405 }
1406 #endif
1407
1408 #ifdef CONFIG_SWIOTLB
1409 if (swiotlb_nr_tbl()) {
1410 ttm_dma_unpopulate((void *)ttm, dev->dev);
1411 return;
1412 }
1413 #endif
1414
1415 for (i = 0; i < ttm->num_pages; i++) {
1416 if (ttm_dma->dma_address[i]) {
1417 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1418 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1419 }
1420 }
1421
1422 ttm_pool_unpopulate(ttm);
1423 }
1424
1425 void
1426 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1427 {
1428 struct nouveau_fence *old_fence = NULL;
1429
1430 if (likely(fence))
1431 nouveau_fence_ref(fence);
1432
1433 spin_lock(&nvbo->bo.bdev->fence_lock);
1434 old_fence = nvbo->bo.sync_obj;
1435 nvbo->bo.sync_obj = fence;
1436 spin_unlock(&nvbo->bo.bdev->fence_lock);
1437
1438 nouveau_fence_unref(&old_fence);
1439 }
1440
1441 static void
1442 nouveau_bo_fence_unref(void **sync_obj)
1443 {
1444 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1445 }
1446
1447 static void *
1448 nouveau_bo_fence_ref(void *sync_obj)
1449 {
1450 return nouveau_fence_ref(sync_obj);
1451 }
1452
1453 static bool
1454 nouveau_bo_fence_signalled(void *sync_obj, void *sync_arg)
1455 {
1456 return nouveau_fence_done(sync_obj);
1457 }
1458
1459 static int
1460 nouveau_bo_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
1461 {
1462 return nouveau_fence_wait(sync_obj, lazy, intr);
1463 }
1464
1465 static int
1466 nouveau_bo_fence_flush(void *sync_obj, void *sync_arg)
1467 {
1468 return 0;
1469 }
1470
1471 struct ttm_bo_driver nouveau_bo_driver = {
1472 .ttm_tt_create = &nouveau_ttm_tt_create,
1473 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1474 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1475 .invalidate_caches = nouveau_bo_invalidate_caches,
1476 .init_mem_type = nouveau_bo_init_mem_type,
1477 .evict_flags = nouveau_bo_evict_flags,
1478 .move_notify = nouveau_bo_move_ntfy,
1479 .move = nouveau_bo_move,
1480 .verify_access = nouveau_bo_verify_access,
1481 .sync_obj_signaled = nouveau_bo_fence_signalled,
1482 .sync_obj_wait = nouveau_bo_fence_wait,
1483 .sync_obj_flush = nouveau_bo_fence_flush,
1484 .sync_obj_unref = nouveau_bo_fence_unref,
1485 .sync_obj_ref = nouveau_bo_fence_ref,
1486 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1487 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1488 .io_mem_free = &nouveau_ttm_io_mem_free,
1489 };
1490
1491 struct nouveau_vma *
1492 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1493 {
1494 struct nouveau_vma *vma;
1495 list_for_each_entry(vma, &nvbo->vma_list, head) {
1496 if (vma->vm == vm)
1497 return vma;
1498 }
1499
1500 return NULL;
1501 }
1502
1503 int
1504 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1505 struct nouveau_vma *vma)
1506 {
1507 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1508 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1509 int ret;
1510
1511 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1512 NV_MEM_ACCESS_RW, vma);
1513 if (ret)
1514 return ret;
1515
1516 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1517 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1518 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1519 if (node->sg)
1520 nouveau_vm_map_sg_table(vma, 0, size, node);
1521 else
1522 nouveau_vm_map_sg(vma, 0, size, node);
1523 }
1524
1525 list_add_tail(&vma->head, &nvbo->vma_list);
1526 vma->refcount = 1;
1527 return 0;
1528 }
1529
1530 void
1531 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1532 {
1533 if (vma->node) {
1534 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1535 spin_lock(&nvbo->bo.bdev->fence_lock);
1536 ttm_bo_wait(&nvbo->bo, false, false, false);
1537 spin_unlock(&nvbo->bo.bdev->fence_lock);
1538 nouveau_vm_unmap(vma);
1539 }
1540
1541 nouveau_vm_put(vma);
1542 list_del(&vma->head);
1543 }
1544 }
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