drivers/gpu/drm/nouveau/nouveau_dma.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_dma.h"
  31 #include "nouveau_ramht.h"
  32
  33 void
  34 nouveau_dma_pre_init(struct nouveau_channel *chan)
  35 {
  36         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  37         struct nouveau_bo *pushbuf = chan->pushbuf_bo;
  38
  39         if (dev_priv->card_type == NV_50) {
  40                 const int ib_size = pushbuf->bo.mem.size / 2;
  41
  42                 chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
  43                 chan->dma.ib_max = (ib_size / 8) - 1;
  44                 chan->dma.ib_put = 0;
  45                 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
  46
  47                 chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
  48         } else {
  49                 chan->dma.max  = (pushbuf->bo.mem.size >> 2) - 2;
  50         }
  51
  52         chan->dma.put  = 0;
  53         chan->dma.cur  = chan->dma.put;
  54         chan->dma.free = chan->dma.max - chan->dma.cur;
  55 }
  56
  57 int
  58 nouveau_dma_init(struct nouveau_channel *chan)
  59 {
  60         struct drm_device *dev = chan->dev;
  61         struct drm_nouveau_private *dev_priv = dev->dev_private;
  62         struct nouveau_gpuobj *obj = NULL;
  63         int ret, i;
  64
  65         /* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
  66         ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
  67                                     0x0039 : 0x5039, &obj);
  68         if (ret)
  69                 return ret;
  70
  71         ret = nouveau_ramht_insert(chan, NvM2MF, obj);
  72         nouveau_gpuobj_ref(NULL, &obj);
  73         if (ret)
  74                 return ret;
  75
  76         /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
  77         ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
  78         if (ret)
  79                 return ret;
  80
  81         /* Map push buffer */
  82         ret = nouveau_bo_map(chan->pushbuf_bo);
  83         if (ret)
  84                 return ret;
  85
  86         /* Insert NOPS for NOUVEAU_DMA_SKIPS */
  87         ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
  88         if (ret)
  89                 return ret;
  90
  91         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
  92                 OUT_RING(chan, 0);
  93
  94         /* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
  95         ret = RING_SPACE(chan, 4);
  96         if (ret)
  97                 return ret;
  98         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
  99         OUT_RING(chan, NvM2MF);
 100         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
 101         OUT_RING(chan, NvNotify0);
 102
 103         /* Sit back and pray the channel works.. */
 104         FIRE_RING(chan);
 105
 106         return 0;
 107 }
 108
 109 void
 110 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
 111 {
 112         bool is_iomem;
 113         u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
 114         mem = &mem[chan->dma.cur];
 115         if (is_iomem)
 116                 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
 117         else
 118                 memcpy(mem, data, nr_dwords * 4);
 119         chan->dma.cur += nr_dwords;
 120 }
 121
 122 /* Fetch and adjust GPU GET pointer
 123  *
 124  * Returns:
 125  *  value >= 0, the adjusted GET pointer
 126  *  -EINVAL if GET pointer currently outside main push buffer
 127  *  -EBUSY if timeout exceeded
 128  */
 129 static inline int
 130 READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
 131 {
 132         uint32_t val;
 133
 134         val = nvchan_rd32(chan, chan->user_get);
 135
 136         /* reset counter as long as GET is still advancing, this is
 137          * to avoid misdetecting a GPU lockup if the GPU happens to
 138          * just be processing an operation that takes a long time
 139          */
 140         if (val != *prev_get) {
 141                 *prev_get = val;
 142                 *timeout = 0;
 143         }
 144
 145         if ((++*timeout & 0xff) == 0) {
 146                 DRM_UDELAY(1);
 147                 if (*timeout > 100000)
 148                         return -EBUSY;
 149         }
 150
 151         if (val < chan->pushbuf_base ||
 152             val > chan->pushbuf_base + (chan->dma.max << 2))
 153                 return -EINVAL;
 154
 155         return (val - chan->pushbuf_base) >> 2;
 156 }
 157
 158 void
 159 nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
 160               int delta, int length)
 161 {
 162         struct nouveau_bo *pb = chan->pushbuf_bo;
 163         uint64_t offset = bo->bo.offset + delta;
 164         int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
 165
 166         BUG_ON(chan->dma.ib_free < 1);
 167         nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
 168         nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
 169
 170         chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
 171
 172         DRM_MEMORYBARRIER();
 173         /* Flush writes. */
 174         nouveau_bo_rd32(pb, 0);
 175
 176         nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
 177         chan->dma.ib_free--;
 178 }
 179
 180 static int
 181 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
 182 {
 183         uint32_t cnt = 0, prev_get = 0;
 184
 185         while (chan->dma.ib_free < count) {
 186                 uint32_t get = nvchan_rd32(chan, 0x88);
 187                 if (get != prev_get) {
 188                         prev_get = get;
 189                         cnt = 0;
 190                 }
 191
 192                 if ((++cnt & 0xff) == 0) {
 193                         DRM_UDELAY(1);
 194                         if (cnt > 100000)
 195                                 return -EBUSY;
 196                 }
 197
 198                 chan->dma.ib_free = get - chan->dma.ib_put;
 199                 if (chan->dma.ib_free <= 0)
 200                         chan->dma.ib_free += chan->dma.ib_max;
 201         }
 202
 203         return 0;
 204 }
 205
 206 static int
 207 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
 208 {
 209         uint32_t cnt = 0, prev_get = 0;
 210         int ret;
 211
 212         ret = nv50_dma_push_wait(chan, slots + 1);
 213         if (unlikely(ret))
 214                 return ret;
 215
 216         while (chan->dma.free < count) {
 217                 int get = READ_GET(chan, &prev_get, &cnt);
 218                 if (unlikely(get < 0)) {
 219                         if (get == -EINVAL)
 220                                 continue;
 221
 222                         return get;
 223                 }
 224
 225                 if (get <= chan->dma.cur) {
 226                         chan->dma.free = chan->dma.max - chan->dma.cur;
 227                         if (chan->dma.free >= count)
 228                                 break;
 229
 230                         FIRE_RING(chan);
 231                         do {
 232                                 get = READ_GET(chan, &prev_get, &cnt);
 233                                 if (unlikely(get < 0)) {
 234                                         if (get == -EINVAL)
 235                                                 continue;
 236                                         return get;
 237                                 }
 238                         } while (get == 0);
 239                         chan->dma.cur = 0;
 240                         chan->dma.put = 0;
 241                 }
 242
 243                 chan->dma.free = get - chan->dma.cur - 1;
 244         }
 245
 246         return 0;
 247 }
 248
 249 int
 250 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
 251 {
 252         uint32_t prev_get = 0, cnt = 0;
 253         int get;
 254
 255         if (chan->dma.ib_max)
 256                 return nv50_dma_wait(chan, slots, size);
 257
 258         while (chan->dma.free < size) {
 259                 get = READ_GET(chan, &prev_get, &cnt);
 260                 if (unlikely(get == -EBUSY))
 261                         return -EBUSY;
 262
 263                 /* loop until we have a usable GET pointer.  the value
 264                  * we read from the GPU may be outside the main ring if
 265                  * PFIFO is processing a buffer called from the main ring,
 266                  * discard these values until something sensible is seen.
 267                  *
 268                  * the other case we discard GET is while the GPU is fetching
 269                  * from the SKIPS area, so the code below doesn't have to deal
 270                  * with some fun corner cases.
 271                  */
 272                 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
 273                         continue;
 274
 275                 if (get <= chan->dma.cur) {
 276                         /* engine is fetching behind us, or is completely
 277                          * idle (GET == PUT) so we have free space up until
 278                          * the end of the push buffer
 279                          *
 280                          * we can only hit that path once per call due to
 281                          * looping back to the beginning of the push buffer,
 282                          * we'll hit the fetching-ahead-of-us path from that
 283                          * point on.
 284                          *
 285                          * the *one* exception to that rule is if we read
 286                          * GET==PUT, in which case the below conditional will
 287                          * always succeed and break us out of the wait loop.
 288                          */
 289                         chan->dma.free = chan->dma.max - chan->dma.cur;
 290                         if (chan->dma.free >= size)
 291                                 break;
 292
 293                         /* not enough space left at the end of the push buffer,
 294                          * instruct the GPU to jump back to the start right
 295                          * after processing the currently pending commands.
 296                          */
 297                         OUT_RING(chan, chan->pushbuf_base | 0x20000000);
 298
 299                         /* wait for GET to depart from the skips area.
 300                          * prevents writing GET==PUT and causing a race
 301                          * condition that causes us to think the GPU is
 302                          * idle when it's not.
 303                          */
 304                         do {
 305                                 get = READ_GET(chan, &prev_get, &cnt);
 306                                 if (unlikely(get == -EBUSY))
 307                                         return -EBUSY;
 308                                 if (unlikely(get == -EINVAL))
 309                                         continue;
 310                         } while (get <= NOUVEAU_DMA_SKIPS);
 311                         WRITE_PUT(NOUVEAU_DMA_SKIPS);
 312
 313                         /* we're now submitting commands at the start of
 314                          * the push buffer.
 315                          */
 316                         chan->dma.cur  =
 317                         chan->dma.put  = NOUVEAU_DMA_SKIPS;
 318                 }
 319
 320                 /* engine fetching ahead of us, we have space up until the
 321                  * current GET pointer.  the "- 1" is to ensure there's
 322                  * space left to emit a jump back to the beginning of the
 323                  * push buffer if we require it.  we can never get GET == PUT
 324                  * here, so this is safe.
 325                  */
 326                 chan->dma.free = get - chan->dma.cur - 1;
 327         }
 328
 329         return 0;
 330 }
 331