drivers/gpu/drm/nouveau/nouveau_dma.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_dma.h"
  29 #include "nouveau_vmm.h"
  30
  31 void
  32 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
  33 {
  34         bool is_iomem;
  35         u32 *mem = ttm_kmap_obj_virtual(&chan->push.buffer->kmap, &is_iomem);
  36         mem = &mem[chan->dma.cur];
  37         if (is_iomem)
  38                 memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
  39         else
  40                 memcpy(mem, data, nr_dwords * 4);
  41         chan->dma.cur += nr_dwords;
  42 }
  43
  44 /* Fetch and adjust GPU GET pointer
  45  *
  46  * Returns:
  47  *  value >= 0, the adjusted GET pointer
  48  *  -EINVAL if GET pointer currently outside main push buffer
  49  *  -EBUSY if timeout exceeded
  50  */
  51 static inline int
  52 READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout)
  53 {
  54         uint64_t val;
  55
  56         val = nvif_rd32(&chan->user, chan->user_get);
  57         if (chan->user_get_hi)
  58                 val |= (uint64_t)nvif_rd32(&chan->user, chan->user_get_hi) << 32;
  59
  60         /* reset counter as long as GET is still advancing, this is
  61          * to avoid misdetecting a GPU lockup if the GPU happens to
  62          * just be processing an operation that takes a long time
  63          */
  64         if (val != *prev_get) {
  65                 *prev_get = val;
  66                 *timeout = 0;
  67         }
  68
  69         if ((++*timeout & 0xff) == 0) {
  70                 udelay(1);
  71                 if (*timeout > 100000)
  72                         return -EBUSY;
  73         }
  74
  75         if (val < chan->push.addr ||
  76             val > chan->push.addr + (chan->dma.max << 2))
  77                 return -EINVAL;
  78
  79         return (val - chan->push.addr) >> 2;
  80 }
  81
  82 void
  83 nv50_dma_push(struct nouveau_channel *chan, u64 offset, int length)
  84 {
  85         struct nouveau_bo *pb = chan->push.buffer;
  86         int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
  87
  88         BUG_ON(chan->dma.ib_free < 1);
  89
  90         nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
  91         nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
  92
  93         chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
  94
  95         mb();
  96         /* Flush writes. */
  97         nouveau_bo_rd32(pb, 0);
  98
  99         nvif_wr32(&chan->user, 0x8c, chan->dma.ib_put);
 100         chan->dma.ib_free--;
 101 }
 102
 103 static int
 104 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
 105 {
 106         uint32_t cnt = 0, prev_get = 0;
 107
 108         while (chan->dma.ib_free < count) {
 109                 uint32_t get = nvif_rd32(&chan->user, 0x88);
 110                 if (get != prev_get) {
 111                         prev_get = get;
 112                         cnt = 0;
 113                 }
 114
 115                 if ((++cnt & 0xff) == 0) {
 116                         DRM_UDELAY(1);
 117                         if (cnt > 100000)
 118                                 return -EBUSY;
 119                 }
 120
 121                 chan->dma.ib_free = get - chan->dma.ib_put;
 122                 if (chan->dma.ib_free <= 0)
 123                         chan->dma.ib_free += chan->dma.ib_max;
 124         }
 125
 126         return 0;
 127 }
 128
 129 static int
 130 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
 131 {
 132         uint64_t prev_get = 0;
 133         int ret, cnt = 0;
 134
 135         ret = nv50_dma_push_wait(chan, slots + 1);
 136         if (unlikely(ret))
 137                 return ret;
 138
 139         while (chan->dma.free < count) {
 140                 int get = READ_GET(chan, &prev_get, &cnt);
 141                 if (unlikely(get < 0)) {
 142                         if (get == -EINVAL)
 143                                 continue;
 144
 145                         return get;
 146                 }
 147
 148                 if (get <= chan->dma.cur) {
 149                         chan->dma.free = chan->dma.max - chan->dma.cur;
 150                         if (chan->dma.free >= count)
 151                                 break;
 152
 153                         FIRE_RING(chan);
 154                         do {
 155                                 get = READ_GET(chan, &prev_get, &cnt);
 156                                 if (unlikely(get < 0)) {
 157                                         if (get == -EINVAL)
 158                                                 continue;
 159                                         return get;
 160                                 }
 161                         } while (get == 0);
 162                         chan->dma.cur = 0;
 163                         chan->dma.put = 0;
 164                 }
 165
 166                 chan->dma.free = get - chan->dma.cur - 1;
 167         }
 168
 169         return 0;
 170 }
 171
 172 int
 173 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
 174 {
 175         uint64_t prev_get = 0;
 176         int cnt = 0, get;
 177
 178         if (chan->dma.ib_max)
 179                 return nv50_dma_wait(chan, slots, size);
 180
 181         while (chan->dma.free < size) {
 182                 get = READ_GET(chan, &prev_get, &cnt);
 183                 if (unlikely(get == -EBUSY))
 184                         return -EBUSY;
 185
 186                 /* loop until we have a usable GET pointer.  the value
 187                  * we read from the GPU may be outside the main ring if
 188                  * PFIFO is processing a buffer called from the main ring,
 189                  * discard these values until something sensible is seen.
 190                  *
 191                  * the other case we discard GET is while the GPU is fetching
 192                  * from the SKIPS area, so the code below doesn't have to deal
 193                  * with some fun corner cases.
 194                  */
 195                 if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
 196                         continue;
 197
 198                 if (get <= chan->dma.cur) {
 199                         /* engine is fetching behind us, or is completely
 200                          * idle (GET == PUT) so we have free space up until
 201                          * the end of the push buffer
 202                          *
 203                          * we can only hit that path once per call due to
 204                          * looping back to the beginning of the push buffer,
 205                          * we'll hit the fetching-ahead-of-us path from that
 206                          * point on.
 207                          *
 208                          * the *one* exception to that rule is if we read
 209                          * GET==PUT, in which case the below conditional will
 210                          * always succeed and break us out of the wait loop.
 211                          */
 212                         chan->dma.free = chan->dma.max - chan->dma.cur;
 213                         if (chan->dma.free >= size)
 214                                 break;
 215
 216                         /* not enough space left at the end of the push buffer,
 217                          * instruct the GPU to jump back to the start right
 218                          * after processing the currently pending commands.
 219                          */
 220                         OUT_RING(chan, chan->push.addr | 0x20000000);
 221
 222                         /* wait for GET to depart from the skips area.
 223                          * prevents writing GET==PUT and causing a race
 224                          * condition that causes us to think the GPU is
 225                          * idle when it's not.
 226                          */
 227                         do {
 228                                 get = READ_GET(chan, &prev_get, &cnt);
 229                                 if (unlikely(get == -EBUSY))
 230                                         return -EBUSY;
 231                                 if (unlikely(get == -EINVAL))
 232                                         continue;
 233                         } while (get <= NOUVEAU_DMA_SKIPS);
 234                         WRITE_PUT(NOUVEAU_DMA_SKIPS);
 235
 236                         /* we're now submitting commands at the start of
 237                          * the push buffer.
 238                          */
 239                         chan->dma.cur  =
 240                         chan->dma.put  = NOUVEAU_DMA_SKIPS;
 241                 }
 242
 243                 /* engine fetching ahead of us, we have space up until the
 244                  * current GET pointer.  the "- 1" is to ensure there's
 245                  * space left to emit a jump back to the beginning of the
 246                  * push buffer if we require it.  we can never get GET == PUT
 247                  * here, so this is safe.
 248                  */
 249                 chan->dma.free = get - chan->dma.cur - 1;
 250         }
 251
 252         return 0;
 253 }
 254