drivers/gpu/drm/nouveau/nouveau_dp.c

   1 /*
   2  * Copyright 2009 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_i2c.h"
  29 #include "nouveau_connector.h"
  30 #include "nouveau_encoder.h"
  31
  32 /******************************************************************************
  33  * aux channel util functions
  34  *****************************************************************************/
  35 #define AUX_DBG(fmt, args...) do {                                             \
  36         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) {                     \
  37                 NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args);     \
  38         }                                                                      \
  39 } while (0)
  40 #define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
  41
  42 static void
  43 auxch_fini(struct drm_device *dev, int ch)
  44 {
  45         nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
  46 }
  47
  48 static int
  49 auxch_init(struct drm_device *dev, int ch)
  50 {
  51         const u32 unksel = 1; /* nfi which to use, or if it matters.. */
  52         const u32 ureq = unksel ? 0x00100000 : 0x00200000;
  53         const u32 urep = unksel ? 0x01000000 : 0x02000000;
  54         u32 ctrl, timeout;
  55
  56         /* wait up to 1ms for any previous transaction to be done... */
  57         timeout = 1000;
  58         do {
  59                 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
  60                 udelay(1);
  61                 if (!timeout--) {
  62                         AUX_ERR("begin idle timeout 0x%08x", ctrl);
  63                         return -EBUSY;
  64                 }
  65         } while (ctrl & 0x03010000);
  66
  67         /* set some magic, and wait up to 1ms for it to appear */
  68         nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
  69         timeout = 1000;
  70         do {
  71                 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
  72                 udelay(1);
  73                 if (!timeout--) {
  74                         AUX_ERR("magic wait 0x%08x\n", ctrl);
  75                         auxch_fini(dev, ch);
  76                         return -EBUSY;
  77                 }
  78         } while ((ctrl & 0x03000000) != urep);
  79
  80         return 0;
  81 }
  82
  83 static int
  84 auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
  85 {
  86         u32 ctrl, stat, timeout, retries;
  87         u32 xbuf[4] = {};
  88         int ret, i;
  89
  90         AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
  91
  92         ret = auxch_init(dev, ch);
  93         if (ret)
  94                 goto out;
  95
  96         stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
  97         if (!(stat & 0x10000000)) {
  98                 AUX_DBG("sink not detected\n");
  99                 ret = -ENXIO;
 100                 goto out;
 101         }
 102
 103         if (!(type & 1)) {
 104                 memcpy(xbuf, data, size);
 105                 for (i = 0; i < 16; i += 4) {
 106                         AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
 107                         nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
 108                 }
 109         }
 110
 111         ctrl  = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
 112         ctrl &= ~0x0001f0ff;
 113         ctrl |= type << 12;
 114         ctrl |= size - 1;
 115         nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
 116
 117         /* retry transaction a number of times on failure... */
 118         ret = -EREMOTEIO;
 119         for (retries = 0; retries < 32; retries++) {
 120                 /* reset, and delay a while if this is a retry */
 121                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
 122                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
 123                 if (retries)
 124                         udelay(400);
 125
 126                 /* transaction request, wait up to 1ms for it to complete */
 127                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
 128
 129                 timeout = 1000;
 130                 do {
 131                         ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
 132                         udelay(1);
 133                         if (!timeout--) {
 134                                 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
 135                                 goto out;
 136                         }
 137                 } while (ctrl & 0x00010000);
 138
 139                 /* read status, and check if transaction completed ok */
 140                 stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
 141                 if (!(stat & 0x000f0f00)) {
 142                         ret = 0;
 143                         break;
 144                 }
 145
 146                 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
 147         }
 148
 149         if (type & 1) {
 150                 for (i = 0; i < 16; i += 4) {
 151                         xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
 152                         AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
 153                 }
 154                 memcpy(data, xbuf, size);
 155         }
 156
 157 out:
 158         auxch_fini(dev, ch);
 159         return ret;
 160 }
 161
 162 static int
 163 auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
 164 {
 165         struct drm_device *dev = encoder->dev;
 166         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 167         struct nouveau_i2c_chan *auxch;
 168         int ret;
 169
 170         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
 171         if (!auxch)
 172                 return -ENODEV;
 173
 174         ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
 175         if (ret)
 176                 return ret;
 177
 178         return 0;
 179 }
 180
 181 static int
 182 auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
 183 {
 184         struct drm_device *dev = encoder->dev;
 185         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 186         struct nouveau_i2c_chan *auxch;
 187         int ret;
 188
 189         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
 190         if (!auxch)
 191                 return -ENODEV;
 192
 193         ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
 194         return ret;
 195 }
 196
 197 static u32
 198 dp_link_bw_get(struct drm_device *dev, int or, int link)
 199 {
 200         u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
 201         if (!(ctrl & 0x000c0000))
 202                 return 162000;
 203         return 270000;
 204 }
 205
 206 static int
 207 dp_lane_count_get(struct drm_device *dev, int or, int link)
 208 {
 209         u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 210         switch (ctrl & 0x000f0000) {
 211         case 0x00010000: return 1;
 212         case 0x00030000: return 2;
 213         default:
 214                 return 4;
 215         }
 216 }
 217
 218 void
 219 nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
 220 {
 221         const u32 symbol = 100000;
 222         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
 223         int TU, VTUi, VTUf, VTUa;
 224         u64 link_data_rate, link_ratio, unk;
 225         u32 best_diff = 64 * symbol;
 226         u32 link_nr, link_bw, r;
 227
 228         /* calculate packed data rate for each lane */
 229         link_nr = dp_lane_count_get(dev, or, link);
 230         link_data_rate = (clk * bpp / 8) / link_nr;
 231
 232         /* calculate ratio of packed data rate to link symbol rate */
 233         link_bw = dp_link_bw_get(dev, or, link);
 234         link_ratio = link_data_rate * symbol;
 235         r = do_div(link_ratio, link_bw);
 236
 237         for (TU = 64; TU >= 32; TU--) {
 238                 /* calculate average number of valid symbols in each TU */
 239                 u32 tu_valid = link_ratio * TU;
 240                 u32 calc, diff;
 241
 242                 /* find a hw representation for the fraction.. */
 243                 VTUi = tu_valid / symbol;
 244                 calc = VTUi * symbol;
 245                 diff = tu_valid - calc;
 246                 if (diff) {
 247                         if (diff >= (symbol / 2)) {
 248                                 VTUf = symbol / (symbol - diff);
 249                                 if (symbol - (VTUf * diff))
 250                                         VTUf++;
 251
 252                                 if (VTUf <= 15) {
 253                                         VTUa  = 1;
 254                                         calc += symbol - (symbol / VTUf);
 255                                 } else {
 256                                         VTUa  = 0;
 257                                         VTUf  = 1;
 258                                         calc += symbol;
 259                                 }
 260                         } else {
 261                                 VTUa  = 0;
 262                                 VTUf  = min((int)(symbol / diff), 15);
 263                                 calc += symbol / VTUf;
 264                         }
 265
 266                         diff = calc - tu_valid;
 267                 } else {
 268                         /* no remainder, but the hw doesn't like the fractional
 269                          * part to be zero.  decrement the integer part and
 270                          * have the fraction add a whole symbol back
 271                          */
 272                         VTUa = 0;
 273                         VTUf = 1;
 274                         VTUi--;
 275                 }
 276
 277                 if (diff < best_diff) {
 278                         best_diff = diff;
 279                         bestTU = TU;
 280                         bestVTUa = VTUa;
 281                         bestVTUf = VTUf;
 282                         bestVTUi = VTUi;
 283                         if (diff == 0)
 284                                 break;
 285                 }
 286         }
 287
 288         if (!bestTU) {
 289                 NV_ERROR(dev, "DP: unable to find suitable config\n");
 290                 return;
 291         }
 292
 293         /* XXX close to vbios numbers, but not right */
 294         unk  = (symbol - link_ratio) * bestTU;
 295         unk *= link_ratio;
 296         r = do_div(unk, symbol);
 297         r = do_div(unk, symbol);
 298         unk += 6;
 299
 300         nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
 301         nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
 302                                                              bestVTUf << 16 |
 303                                                              bestVTUi << 8 |
 304                                                              unk);
 305 }
 306
 307 static int
 308 nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
 309 {
 310         struct drm_device *dev = encoder->dev;
 311         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 312         uint32_t tmp;
 313         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
 314
 315         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 316         tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
 317                  NV50_SOR_DP_CTRL_LANE_MASK);
 318         tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
 319         if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 320                 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
 321         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 322
 323         return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
 324 }
 325
 326 static int
 327 nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
 328 {
 329         struct drm_device *dev = encoder->dev;
 330         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 331         uint32_t tmp;
 332         int reg = 0x614300 + (nv_encoder->or * 0x800);
 333
 334         tmp  = nv_rd32(dev, reg);
 335         tmp &= 0xfff3ffff;
 336         if (cmd == DP_LINK_BW_2_7)
 337                 tmp |= 0x00040000;
 338         nv_wr32(dev, reg, tmp);
 339
 340         return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
 341 }
 342
 343 static int
 344 nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 348         uint32_t tmp;
 349         uint8_t cmd;
 350         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
 351         int ret;
 352
 353         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 354         tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
 355         tmp |= (pattern << 24);
 356         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 357
 358         ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
 359         if (ret)
 360                 return ret;
 361         cmd &= ~DP_TRAINING_PATTERN_MASK;
 362         cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
 363         return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
 364 }
 365
 366 static int
 367 nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
 368 {
 369         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 370         struct drm_device *dev = encoder->dev;
 371         struct bit_displayport_encoder_table_entry *dpse;
 372         struct bit_displayport_encoder_table *dpe;
 373         int i, dpe_headerlen, max_vs = 0;
 374
 375         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 376         if (!dpe)
 377                 return false;
 378         dpse = (void *)((char *)dpe + dpe_headerlen);
 379
 380         for (i = 0; i < dpe_headerlen; i++, dpse++) {
 381                 if (dpse->vs_level > max_vs)
 382                         max_vs = dpse->vs_level;
 383         }
 384
 385         return max_vs;
 386 }
 387
 388 static int
 389 nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
 390 {
 391         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 392         struct drm_device *dev = encoder->dev;
 393         struct bit_displayport_encoder_table_entry *dpse;
 394         struct bit_displayport_encoder_table *dpe;
 395         int i, dpe_headerlen, max_pre = 0;
 396
 397         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 398         if (!dpe)
 399                 return false;
 400         dpse = (void *)((char *)dpe + dpe_headerlen);
 401
 402         for (i = 0; i < dpe_headerlen; i++, dpse++) {
 403                 if (dpse->vs_level != vs)
 404                         continue;
 405
 406                 if (dpse->pre_level > max_pre)
 407                         max_pre = dpse->pre_level;
 408         }
 409
 410         return max_pre;
 411 }
 412
 413 static bool
 414 nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
 415 {
 416         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 417         struct drm_device *dev = encoder->dev;
 418         struct bit_displayport_encoder_table *dpe;
 419         int ret, i, dpe_headerlen, vs = 0, pre = 0;
 420         uint8_t request[2];
 421
 422         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 423         if (!dpe)
 424                 return false;
 425
 426         ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
 427         if (ret)
 428                 return false;
 429
 430         NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
 431
 432         /* Keep all lanes at the same level.. */
 433         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
 434                 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
 435                 int lane_vs = lane_req & 3;
 436                 int lane_pre = (lane_req >> 2) & 3;
 437
 438                 if (lane_vs > vs)
 439                         vs = lane_vs;
 440                 if (lane_pre > pre)
 441                         pre = lane_pre;
 442         }
 443
 444         if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
 445                 vs  = nouveau_dp_max_voltage_swing(encoder);
 446                 vs |= 4;
 447         }
 448
 449         if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
 450                 pre  = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
 451                 pre |= 4;
 452         }
 453
 454         /* Update the configuration for all lanes.. */
 455         for (i = 0; i < nv_encoder->dp.link_nr; i++)
 456                 config[i] = (pre << 3) | vs;
 457
 458         return true;
 459 }
 460
 461 static bool
 462 nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
 463 {
 464         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 465         struct drm_device *dev = encoder->dev;
 466         struct bit_displayport_encoder_table_entry *dpse;
 467         struct bit_displayport_encoder_table *dpe;
 468         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
 469         int dpe_headerlen, ret, i;
 470
 471         NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
 472                  config[0], config[1], config[2], config[3]);
 473
 474         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 475         if (!dpe)
 476                 return false;
 477         dpse = (void *)((char *)dpe + dpe_headerlen);
 478
 479         for (i = 0; i < dpe->record_nr; i++, dpse++) {
 480                 if (dpse->vs_level == (config[0] & 3) &&
 481                     dpse->pre_level == ((config[0] >> 3) & 3))
 482                         break;
 483         }
 484         BUG_ON(i == dpe->record_nr);
 485
 486         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
 487                 const int shift[4] = { 16, 8, 0, 24 };
 488                 uint32_t mask = 0xff << shift[i];
 489                 uint32_t reg0, reg1, reg2;
 490
 491                 reg0  = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
 492                 reg0 |= (dpse->reg0 << shift[i]);
 493                 reg1  = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
 494                 reg1 |= (dpse->reg1 << shift[i]);
 495                 reg2  = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
 496                 reg2 |= (dpse->reg2 << 8);
 497                 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
 498                 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
 499                 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
 500         }
 501
 502         ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
 503         if (ret)
 504                 return false;
 505
 506         return true;
 507 }
 508
 509 bool
 510 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
 511 {
 512         struct drm_device *dev = encoder->dev;
 513         struct drm_nouveau_private *dev_priv = dev->dev_private;
 514         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 515         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 516         struct nouveau_connector *nv_connector;
 517         struct bit_displayport_encoder_table *dpe;
 518         int dpe_headerlen;
 519         uint8_t config[4], status[3];
 520         bool cr_done, cr_max_vs, eq_done, hpd_state;
 521         int ret = 0, i, tries, voltage;
 522
 523         NV_DEBUG_KMS(dev, "link training!!\n");
 524
 525         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 526         if (!nv_connector)
 527                 return false;
 528
 529         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
 530         if (!dpe) {
 531                 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
 532                 return false;
 533         }
 534
 535         /* disable hotplug detect, this flips around on some panels during
 536          * link training.
 537          */
 538         hpd_state = pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
 539
 540         if (dpe->script0) {
 541                 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
 542                 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
 543                                             nv_encoder->dcb, -1);
 544         }
 545
 546 train:
 547         cr_done = eq_done = false;
 548
 549         /* set link configuration */
 550         NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
 551                  nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
 552
 553         ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
 554         if (ret)
 555                 return false;
 556
 557         config[0] = nv_encoder->dp.link_nr;
 558         if (nv_encoder->dp.dpcd_version >= 0x11 &&
 559             nv_encoder->dp.enhanced_frame)
 560                 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 561
 562         ret = nouveau_dp_lane_count_set(encoder, config[0]);
 563         if (ret)
 564                 return false;
 565
 566         /* clock recovery */
 567         NV_DEBUG_KMS(dev, "\tbegin cr\n");
 568         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
 569         if (ret)
 570                 goto stop;
 571
 572         tries = 0;
 573         voltage = -1;
 574         memset(config, 0x00, sizeof(config));
 575         for (;;) {
 576                 if (!nouveau_dp_link_train_commit(encoder, config))
 577                         break;
 578
 579                 udelay(100);
 580
 581                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
 582                 if (ret)
 583                         break;
 584                 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
 585                          status[0], status[1]);
 586
 587                 cr_done = true;
 588                 cr_max_vs = false;
 589                 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
 590                         int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
 591
 592                         if (!(lane & DP_LANE_CR_DONE)) {
 593                                 cr_done = false;
 594                                 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
 595                                         cr_max_vs = true;
 596                                 break;
 597                         }
 598                 }
 599
 600                 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
 601                         voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 602                         tries = 0;
 603                 }
 604
 605                 if (cr_done || cr_max_vs || (++tries == 5))
 606                         break;
 607
 608                 if (!nouveau_dp_link_train_adjust(encoder, config))
 609                         break;
 610         }
 611
 612         if (!cr_done)
 613                 goto stop;
 614
 615         /* channel equalisation */
 616         NV_DEBUG_KMS(dev, "\tbegin eq\n");
 617         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
 618         if (ret)
 619                 goto stop;
 620
 621         for (tries = 0; tries <= 5; tries++) {
 622                 udelay(400);
 623
 624                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
 625                 if (ret)
 626                         break;
 627                 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
 628                          status[0], status[1]);
 629
 630                 eq_done = true;
 631                 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
 632                         eq_done = false;
 633
 634                 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
 635                         int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
 636
 637                         if (!(lane & DP_LANE_CR_DONE)) {
 638                                 cr_done = false;
 639                                 break;
 640                         }
 641
 642                         if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
 643                             !(lane & DP_LANE_SYMBOL_LOCKED)) {
 644                                 eq_done = false;
 645                                 break;
 646                         }
 647                 }
 648
 649                 if (eq_done || !cr_done)
 650                         break;
 651
 652                 if (!nouveau_dp_link_train_adjust(encoder, config) ||
 653                     !nouveau_dp_link_train_commit(encoder, config))
 654                         break;
 655         }
 656
 657 stop:
 658         /* end link training */
 659         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
 660         if (ret)
 661                 return false;
 662
 663         /* retry at a lower setting, if possible */
 664         if (!ret && !(eq_done && cr_done)) {
 665                 NV_DEBUG_KMS(dev, "\twe failed\n");
 666                 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
 667                         NV_DEBUG_KMS(dev, "retry link training at low rate\n");
 668                         nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
 669                         goto train;
 670                 }
 671         }
 672
 673         if (dpe->script1) {
 674                 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
 675                 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
 676                                             nv_encoder->dcb, -1);
 677         }
 678
 679         /* re-enable hotplug detect */
 680         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, hpd_state);
 681
 682         return eq_done;
 683 }
 684
 685 bool
 686 nouveau_dp_detect(struct drm_encoder *encoder)
 687 {
 688         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 689         struct drm_device *dev = encoder->dev;
 690         uint8_t dpcd[4];
 691         int ret;
 692
 693         ret = auxch_rd(encoder, 0x0000, dpcd, 4);
 694         if (ret)
 695                 return false;
 696
 697         NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
 698                       "display: link_bw %d, link_nr %d version 0x%02x\n",
 699                  nv_encoder->dcb->dpconf.link_bw,
 700                  nv_encoder->dcb->dpconf.link_nr,
 701                  dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
 702
 703         nv_encoder->dp.dpcd_version = dpcd[0];
 704
 705         nv_encoder->dp.link_bw = dpcd[1];
 706         if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
 707             !nv_encoder->dcb->dpconf.link_bw)
 708                 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
 709
 710         nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
 711         if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
 712                 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
 713
 714         nv_encoder->dp.enhanced_frame = (dpcd[2] & DP_ENHANCED_FRAME_CAP);
 715
 716         return true;
 717 }
 718
 719 int
 720 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
 721                  uint8_t *data, int data_nr)
 722 {
 723         return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
 724 }
 725
 726 static int
 727 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 728 {
 729         struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
 730         struct i2c_msg *msg = msgs;
 731         int ret, mcnt = num;
 732
 733         while (mcnt--) {
 734                 u8 remaining = msg->len;
 735                 u8 *ptr = msg->buf;
 736
 737                 while (remaining) {
 738                         u8 cnt = (remaining > 16) ? 16 : remaining;
 739                         u8 cmd;
 740
 741                         if (msg->flags & I2C_M_RD)
 742                                 cmd = AUX_I2C_READ;
 743                         else
 744                                 cmd = AUX_I2C_WRITE;
 745
 746                         if (mcnt || remaining > 16)
 747                                 cmd |= AUX_I2C_MOT;
 748
 749                         ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
 750                         if (ret < 0)
 751                                 return ret;
 752
 753                         ptr += cnt;
 754                         remaining -= cnt;
 755                 }
 756
 757                 msg++;
 758         }
 759
 760         return num;
 761 }
 762
 763 static u32
 764 nouveau_dp_i2c_func(struct i2c_adapter *adap)
 765 {
 766         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 767 }
 768
 769 const struct i2c_algorithm nouveau_dp_i2c_algo = {
 770         .master_xfer = nouveau_dp_i2c_xfer,
 771         .functionality = nouveau_dp_i2c_func
 772 };