drivers/gpu/drm/nouveau/nouveau_dp.c

   1 /*
   2  * Copyright 2009 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_i2c.h"
  29 #include "nouveau_connector.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_crtc.h"
  32
  33 /******************************************************************************
  34  * aux channel util functions
  35  *****************************************************************************/
  36 #define AUX_DBG(fmt, args...) do {                                             \
  37         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) {                     \
  38                 NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args);     \
  39         }                                                                      \
  40 } while (0)
  41 #define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
  42
  43 static void
  44 auxch_fini(struct drm_device *dev, int ch)
  45 {
  46         nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
  47 }
  48
  49 static int
  50 auxch_init(struct drm_device *dev, int ch)
  51 {
  52         const u32 unksel = 1; /* nfi which to use, or if it matters.. */
  53         const u32 ureq = unksel ? 0x00100000 : 0x00200000;
  54         const u32 urep = unksel ? 0x01000000 : 0x02000000;
  55         u32 ctrl, timeout;
  56
  57         /* wait up to 1ms for any previous transaction to be done... */
  58         timeout = 1000;
  59         do {
  60                 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
  61                 udelay(1);
  62                 if (!timeout--) {
  63                         AUX_ERR("begin idle timeout 0x%08x", ctrl);
  64                         return -EBUSY;
  65                 }
  66         } while (ctrl & 0x03010000);
  67
  68         /* set some magic, and wait up to 1ms for it to appear */
  69         nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
  70         timeout = 1000;
  71         do {
  72                 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
  73                 udelay(1);
  74                 if (!timeout--) {
  75                         AUX_ERR("magic wait 0x%08x\n", ctrl);
  76                         auxch_fini(dev, ch);
  77                         return -EBUSY;
  78                 }
  79         } while ((ctrl & 0x03000000) != urep);
  80
  81         return 0;
  82 }
  83
  84 static int
  85 auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
  86 {
  87         u32 ctrl, stat, timeout, retries;
  88         u32 xbuf[4] = {};
  89         int ret, i;
  90
  91         AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
  92
  93         ret = auxch_init(dev, ch);
  94         if (ret)
  95                 goto out;
  96
  97         stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
  98         if (!(stat & 0x10000000)) {
  99                 AUX_DBG("sink not detected\n");
 100                 ret = -ENXIO;
 101                 goto out;
 102         }
 103
 104         if (!(type & 1)) {
 105                 memcpy(xbuf, data, size);
 106                 for (i = 0; i < 16; i += 4) {
 107                         AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
 108                         nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
 109                 }
 110         }
 111
 112         ctrl  = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
 113         ctrl &= ~0x0001f0ff;
 114         ctrl |= type << 12;
 115         ctrl |= size - 1;
 116         nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
 117
 118         /* retry transaction a number of times on failure... */
 119         ret = -EREMOTEIO;
 120         for (retries = 0; retries < 32; retries++) {
 121                 /* reset, and delay a while if this is a retry */
 122                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
 123                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
 124                 if (retries)
 125                         udelay(400);
 126
 127                 /* transaction request, wait up to 1ms for it to complete */
 128                 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
 129
 130                 timeout = 1000;
 131                 do {
 132                         ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
 133                         udelay(1);
 134                         if (!timeout--) {
 135                                 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
 136                                 goto out;
 137                         }
 138                 } while (ctrl & 0x00010000);
 139
 140                 /* read status, and check if transaction completed ok */
 141                 stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
 142                 if (!(stat & 0x000f0f00)) {
 143                         ret = 0;
 144                         break;
 145                 }
 146
 147                 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
 148         }
 149
 150         if (type & 1) {
 151                 for (i = 0; i < 16; i += 4) {
 152                         xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
 153                         AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
 154                 }
 155                 memcpy(data, xbuf, size);
 156         }
 157
 158 out:
 159         auxch_fini(dev, ch);
 160         return ret;
 161 }
 162
 163 static u32
 164 dp_link_bw_get(struct drm_device *dev, int or, int link)
 165 {
 166         u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
 167         if (!(ctrl & 0x000c0000))
 168                 return 162000;
 169         return 270000;
 170 }
 171
 172 static int
 173 dp_lane_count_get(struct drm_device *dev, int or, int link)
 174 {
 175         u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 176         switch (ctrl & 0x000f0000) {
 177         case 0x00010000: return 1;
 178         case 0x00030000: return 2;
 179         default:
 180                 return 4;
 181         }
 182 }
 183
 184 void
 185 nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
 186 {
 187         const u32 symbol = 100000;
 188         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
 189         int TU, VTUi, VTUf, VTUa;
 190         u64 link_data_rate, link_ratio, unk;
 191         u32 best_diff = 64 * symbol;
 192         u32 link_nr, link_bw, r;
 193
 194         /* calculate packed data rate for each lane */
 195         link_nr = dp_lane_count_get(dev, or, link);
 196         link_data_rate = (clk * bpp / 8) / link_nr;
 197
 198         /* calculate ratio of packed data rate to link symbol rate */
 199         link_bw = dp_link_bw_get(dev, or, link);
 200         link_ratio = link_data_rate * symbol;
 201         r = do_div(link_ratio, link_bw);
 202
 203         for (TU = 64; TU >= 32; TU--) {
 204                 /* calculate average number of valid symbols in each TU */
 205                 u32 tu_valid = link_ratio * TU;
 206                 u32 calc, diff;
 207
 208                 /* find a hw representation for the fraction.. */
 209                 VTUi = tu_valid / symbol;
 210                 calc = VTUi * symbol;
 211                 diff = tu_valid - calc;
 212                 if (diff) {
 213                         if (diff >= (symbol / 2)) {
 214                                 VTUf = symbol / (symbol - diff);
 215                                 if (symbol - (VTUf * diff))
 216                                         VTUf++;
 217
 218                                 if (VTUf <= 15) {
 219                                         VTUa  = 1;
 220                                         calc += symbol - (symbol / VTUf);
 221                                 } else {
 222                                         VTUa  = 0;
 223                                         VTUf  = 1;
 224                                         calc += symbol;
 225                                 }
 226                         } else {
 227                                 VTUa  = 0;
 228                                 VTUf  = min((int)(symbol / diff), 15);
 229                                 calc += symbol / VTUf;
 230                         }
 231
 232                         diff = calc - tu_valid;
 233                 } else {
 234                         /* no remainder, but the hw doesn't like the fractional
 235                          * part to be zero.  decrement the integer part and
 236                          * have the fraction add a whole symbol back
 237                          */
 238                         VTUa = 0;
 239                         VTUf = 1;
 240                         VTUi--;
 241                 }
 242
 243                 if (diff < best_diff) {
 244                         best_diff = diff;
 245                         bestTU = TU;
 246                         bestVTUa = VTUa;
 247                         bestVTUf = VTUf;
 248                         bestVTUi = VTUi;
 249                         if (diff == 0)
 250                                 break;
 251                 }
 252         }
 253
 254         if (!bestTU) {
 255                 NV_ERROR(dev, "DP: unable to find suitable config\n");
 256                 return;
 257         }
 258
 259         /* XXX close to vbios numbers, but not right */
 260         unk  = (symbol - link_ratio) * bestTU;
 261         unk *= link_ratio;
 262         r = do_div(unk, symbol);
 263         r = do_div(unk, symbol);
 264         unk += 6;
 265
 266         nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
 267         nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
 268                                                              bestVTUf << 16 |
 269                                                              bestVTUi << 8 |
 270                                                              unk);
 271 }
 272
 273 /******************************************************************************
 274  * link training
 275  *****************************************************************************/
 276 struct dp_state {
 277         struct dcb_entry *dcb;
 278         int auxch;
 279         int crtc;
 280         int or;
 281         int link;
 282         u8 *dpcd;
 283         int link_nr;
 284         u32 link_bw;
 285         u8  stat[6];
 286         u8  conf[4];
 287 };
 288
 289 static void
 290 dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
 291 {
 292         struct drm_nouveau_private *dev_priv = dev->dev_private;
 293         int or = dp->or, link = dp->link;
 294         u8 *bios, headerlen, sink[2];
 295         u32 dp_ctrl;
 296
 297         NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
 298
 299         /* set selected link rate on source */
 300         switch (dp->link_bw) {
 301         case 270000:
 302                 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
 303                 sink[0] = DP_LINK_BW_2_7;
 304                 break;
 305         default:
 306                 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
 307                 sink[0] = DP_LINK_BW_1_62;
 308                 break;
 309         }
 310
 311         /* offset +0x0a of each dp encoder table entry is a pointer to another
 312          * table, that has (among other things) pointers to more scripts that
 313          * need to be executed, this time depending on link speed.
 314          */
 315         bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
 316         if (bios && (bios = ROMPTR(&dev_priv->vbios, bios[10]))) {
 317                 u16 script = ROM16(bios[2]);
 318                 if (dp->link_bw != 270000)
 319                         script = ROM16(bios[6]);
 320
 321                 nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
 322         }
 323
 324         /* configure lane count on the source */
 325         dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
 326         sink[1] = dp->link_nr;
 327         if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
 328                 dp_ctrl |= 0x00004000;
 329                 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 330         }
 331
 332         nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
 333
 334         /* inform the sink of the new configuration */
 335         auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
 336 }
 337
 338 static void
 339 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
 340 {
 341         NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
 342         nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
 343         auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &tp, 1);
 344 }
 345
 346 static int
 347 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
 348 {
 349         u32 mask = 0, drv = 0, pre = 0, unk = 0;
 350         u8  shifts[4] = { 16, 8, 0, 24 };
 351         u8  *bios, *last, headerlen;
 352         int link = dp->link;
 353         int or = dp->or;
 354         int i;
 355
 356         bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
 357         last = bios + headerlen + (bios[4] * 5);
 358         for (i = 0; i < dp->link_nr; i++) {
 359                 u8  lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
 360                 u8 *conf = bios + headerlen;
 361
 362                 while (conf < last) {
 363                         if ((lane  & 3) == conf[0] &&
 364                             (lane >> 2) == conf[1])
 365                                 break;
 366                         conf += 5;
 367                 }
 368
 369                 if (conf == last)
 370                         return -EINVAL;
 371
 372                 dp->conf[i] = (conf[1] << 3) | conf[0];
 373                 if (conf[0] == DP_TRAIN_VOLTAGE_SWING_1200)
 374                         dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
 375                 if (conf[1] == DP_TRAIN_PRE_EMPHASIS_9_5)
 376                         dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 377
 378                 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
 379
 380                 mask |= 0xff << shifts[i];
 381                 drv  |= conf[2] << shifts[i];
 382                 pre  |= conf[3] << shifts[i];
 383                 unk   = (unk & ~0x0000ff00) | (conf[4] << 8);
 384                 unk  |= 1 << (shifts[i] >> 3);
 385         }
 386
 387         nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
 388         nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
 389         nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
 390
 391         return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
 392 }
 393
 394 static int
 395 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
 396 {
 397         int ret;
 398
 399         udelay(delay);
 400
 401         ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
 402         if (ret)
 403                 return ret;
 404
 405         NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
 406                      dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
 407                      dp->stat[4], dp->stat[5]);
 408         return 0;
 409 }
 410
 411 static int
 412 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
 413 {
 414         bool cr_done = false, abort = false;
 415         int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 416         int tries = 0, i;
 417
 418         dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
 419
 420         do {
 421                 if (dp_link_train_commit(dev, dp) ||
 422                     dp_link_train_update(dev, dp, 100))
 423                         break;
 424
 425                 cr_done = true;
 426                 for (i = 0; i < dp->link_nr; i++) {
 427                         u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 428                         if (!(lane & DP_LANE_CR_DONE)) {
 429                                 cr_done = false;
 430                                 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
 431                                         abort = true;
 432                                 break;
 433                         }
 434                 }
 435
 436                 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
 437                         voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 438                         tries = 0;
 439                 }
 440         } while (!cr_done && !abort && ++tries < 5);
 441
 442         return cr_done ? 0 : -1;
 443 }
 444
 445 static int
 446 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
 447 {
 448         bool eq_done, cr_done = true;
 449         int tries = 0, i;
 450
 451         dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
 452
 453         do {
 454                 if (dp_link_train_update(dev, dp, 400))
 455                         break;
 456
 457                 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
 458                 for (i = 0; i < dp->link_nr && eq_done; i++) {
 459                         u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 460                         if (!(lane & DP_LANE_CR_DONE))
 461                                 cr_done = false;
 462                         if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
 463                             !(lane & DP_LANE_SYMBOL_LOCKED))
 464                                 eq_done = false;
 465                 }
 466
 467                 if (dp_link_train_commit(dev, dp))
 468                         break;
 469         } while (!eq_done && cr_done && ++tries <= 5);
 470
 471         return eq_done ? 0 : -1;
 472 }
 473
 474 bool
 475 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
 476 {
 477         struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
 478         struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
 479         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 480         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 481         struct nouveau_connector *nv_connector =
 482                 nouveau_encoder_connector_get(nv_encoder);
 483         struct drm_device *dev = encoder->dev;
 484         struct nouveau_i2c_chan *auxch;
 485         const u32 bw_list[] = { 270000, 162000, 0 };
 486         const u32 *link_bw = bw_list;
 487         struct dp_state dp;
 488         u8 *bios, headerlen;
 489
 490         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
 491         if (!auxch)
 492                 return false;
 493
 494         bios = nouveau_bios_dp_table(dev, nv_encoder->dcb, &headerlen);
 495         if (!bios)
 496                 return -EINVAL;
 497
 498         dp.dcb = nv_encoder->dcb;
 499         dp.crtc = nv_crtc->index;
 500         dp.auxch = auxch->rd;
 501         dp.or = nv_encoder->or;
 502         dp.link = !(nv_encoder->dcb->sorconf.link & 1);
 503         dp.dpcd = nv_encoder->dp.dpcd;
 504
 505         /* some sinks toggle hotplug in response to some of the actions
 506          * we take during link training (DP_SET_POWER is one), we need
 507          * to ignore them for the moment to avoid races.
 508          */
 509         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
 510
 511         /* enable down-spreading, if possible */
 512         if (headerlen >= 16) {
 513                 u16 script = ROM16(bios[14]);
 514                 if (nv_encoder->dp.dpcd[3] & 1)
 515                         script = ROM16(bios[12]);
 516
 517                 nouveau_bios_run_init_table(dev, script, dp.dcb, dp.crtc);
 518         }
 519
 520         /* execute pre-train script from vbios */
 521         nouveau_bios_run_init_table(dev, ROM16(bios[6]), dp.dcb, dp.crtc);
 522
 523         /* start off at highest link rate supported by encoder and display */
 524         while (*link_bw > nv_encoder->dp.link_bw)
 525                 link_bw++;
 526
 527         while (link_bw[0]) {
 528                 /* find minimum required lane count at this link rate */
 529                 dp.link_nr = nv_encoder->dp.link_nr;
 530                 while ((dp.link_nr >> 1) * link_bw[0] > datarate)
 531                         dp.link_nr >>= 1;
 532
 533                 /* drop link rate to minimum with this lane count */
 534                 while ((link_bw[1] * dp.link_nr) > datarate)
 535                         link_bw++;
 536                 dp.link_bw = link_bw[0];
 537
 538                 /* program selected link configuration */
 539                 dp_set_link_config(dev, &dp);
 540
 541                 /* attempt to train the link at this configuration */
 542                 memset(dp.stat, 0x00, sizeof(dp.stat));
 543                 if (!dp_link_train_cr(dev, &dp) &&
 544                     !dp_link_train_eq(dev, &dp))
 545                         break;
 546
 547                 /* retry at lower rate */
 548                 link_bw++;
 549         }
 550
 551         /* finish link training */
 552         dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
 553
 554         /* execute post-train script from vbios */
 555         nouveau_bios_run_init_table(dev, ROM16(bios[8]), dp.dcb, dp.crtc);
 556
 557         /* re-enable hotplug detect */
 558         pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
 559         return true;
 560 }
 561
 562 bool
 563 nouveau_dp_detect(struct drm_encoder *encoder)
 564 {
 565         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 566         struct drm_device *dev = encoder->dev;
 567         struct nouveau_i2c_chan *auxch;
 568         u8 *dpcd = nv_encoder->dp.dpcd;
 569         int ret;
 570
 571         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
 572         if (!auxch)
 573                 return false;
 574
 575         ret = auxch_tx(dev, auxch->rd, 9, DP_DPCD_REV, dpcd, 8);
 576         if (ret)
 577                 return false;
 578
 579         nv_encoder->dp.link_bw = 27000 * dpcd[1];
 580         nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
 581
 582         NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
 583                      nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
 584         NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
 585                      nv_encoder->dcb->dpconf.link_nr,
 586                      nv_encoder->dcb->dpconf.link_bw);
 587
 588         if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
 589                 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
 590         if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
 591                 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
 592
 593         NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
 594                      nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
 595
 596         return true;
 597 }
 598
 599 int
 600 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
 601                  uint8_t *data, int data_nr)
 602 {
 603         return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
 604 }
 605
 606 static int
 607 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 608 {
 609         struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
 610         struct i2c_msg *msg = msgs;
 611         int ret, mcnt = num;
 612
 613         while (mcnt--) {
 614                 u8 remaining = msg->len;
 615                 u8 *ptr = msg->buf;
 616
 617                 while (remaining) {
 618                         u8 cnt = (remaining > 16) ? 16 : remaining;
 619                         u8 cmd;
 620
 621                         if (msg->flags & I2C_M_RD)
 622                                 cmd = AUX_I2C_READ;
 623                         else
 624                                 cmd = AUX_I2C_WRITE;
 625
 626                         if (mcnt || remaining > 16)
 627                                 cmd |= AUX_I2C_MOT;
 628
 629                         ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
 630                         if (ret < 0)
 631                                 return ret;
 632
 633                         ptr += cnt;
 634                         remaining -= cnt;
 635                 }
 636
 637                 msg++;
 638         }
 639
 640         return num;
 641 }
 642
 643 static u32
 644 nouveau_dp_i2c_func(struct i2c_adapter *adap)
 645 {
 646         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 647 }
 648
 649 const struct i2c_algorithm nouveau_dp_i2c_algo = {
 650         .master_xfer = nouveau_dp_i2c_xfer,
 651         .functionality = nouveau_dp_i2c_func
 652 };