2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
48 struct nouveau_fpriv
{
49 struct ttm_object_file
*tfile
;
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
59 #define MAX_NUM_DCB_ENTRIES 16
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68 struct nouveau_tile_reg
{
69 struct nouveau_fence
*fence
;
76 struct ttm_buffer_object bo
;
77 struct ttm_placement placement
;
79 u32 busy_placements
[3];
80 struct ttm_bo_kmap_obj kmap
;
81 struct list_head head
;
83 /* protected by ttm_bo_reserve() */
84 struct drm_file
*reserved_by
;
85 struct list_head entry
;
89 struct nouveau_channel
*channel
;
96 struct nouveau_tile_reg
*tile
;
98 struct drm_gem_object
*gem
;
99 struct drm_file
*cpu_filp
;
103 static inline struct nouveau_bo
*
104 nouveau_bo(struct ttm_buffer_object
*bo
)
106 return container_of(bo
, struct nouveau_bo
, bo
);
109 static inline struct nouveau_bo
*
110 nouveau_gem_object(struct drm_gem_object
*gem
)
112 return gem
? gem
->driver_private
: NULL
;
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem
*
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo
*nvbo
)
120 void __iomem
*ioptr
= (void __force __iomem
*)ttm_kmap_obj_virtual(
121 &nvbo
->kmap
, &is_iomem
);
122 WARN_ON_ONCE(ioptr
&& !is_iomem
);
127 NV_NFORCE
= 0x10000000,
128 NV_NFORCE2
= 0x20000000
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
136 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
137 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
138 struct nouveau_gpuobj
{
139 struct drm_device
*dev
;
140 struct kref refcount
;
141 struct list_head list
;
143 struct drm_mm_node
*im_pramin
;
144 struct nouveau_bo
*im_backing
;
145 uint32_t *im_backing_suspend
;
158 void (*dtor
)(struct drm_device
*, struct nouveau_gpuobj
*);
162 struct nouveau_channel
{
163 struct drm_device
*dev
;
166 /* owner of this fifo */
167 struct drm_file
*file_priv
;
168 /* mapping of the fifo itself */
169 struct drm_local_map
*map
;
171 /* mapping of the regs controling the fifo */
178 /* lock protects the pending list only */
180 struct list_head pending
;
182 uint32_t sequence_ack
;
183 atomic_t last_sequence_irq
;
186 /* DMA push buffer */
187 struct nouveau_gpuobj
*pushbuf
;
188 struct nouveau_bo
*pushbuf_bo
;
189 uint32_t pushbuf_base
;
191 /* Notifier memory */
192 struct nouveau_bo
*notifier_bo
;
193 struct drm_mm notifier_heap
;
196 struct nouveau_gpuobj
*ramfc
;
197 struct nouveau_gpuobj
*cache
;
200 /* XXX may be merge 2 pointers as private data ??? */
201 struct nouveau_gpuobj
*ramin_grctx
;
205 struct nouveau_gpuobj
*vm_pd
;
206 struct nouveau_gpuobj
*vm_gart_pt
;
207 struct nouveau_gpuobj
*vm_vram_pt
[NV50_VM_VRAM_NR
];
210 struct nouveau_gpuobj
*ramin
; /* Private instmem */
211 struct drm_mm ramin_heap
; /* Private PRAMIN heap */
212 struct nouveau_ramht
*ramht
; /* Hash table */
214 /* GPU object info for stuff used in-kernel (mm_enabled) */
216 uint32_t vram_handle
;
217 uint32_t gart_handle
;
220 /* Push buffer state (only for drm's channel on !mm_enabled) */
226 /* access via pushbuf_bo */
234 uint32_t sw_subchannel
[8];
237 struct nouveau_gpuobj
*vblsem
;
238 uint32_t vblsem_offset
;
239 uint32_t vblsem_rval
;
240 struct list_head vbl_wait
;
246 struct drm_info_list info
;
250 struct nouveau_instmem_engine
{
253 int (*init
)(struct drm_device
*dev
);
254 void (*takedown
)(struct drm_device
*dev
);
255 int (*suspend
)(struct drm_device
*dev
);
256 void (*resume
)(struct drm_device
*dev
);
258 int (*populate
)(struct drm_device
*, struct nouveau_gpuobj
*,
260 void (*clear
)(struct drm_device
*, struct nouveau_gpuobj
*);
261 int (*bind
)(struct drm_device
*, struct nouveau_gpuobj
*);
262 int (*unbind
)(struct drm_device
*, struct nouveau_gpuobj
*);
263 void (*flush
)(struct drm_device
*);
266 struct nouveau_mc_engine
{
267 int (*init
)(struct drm_device
*dev
);
268 void (*takedown
)(struct drm_device
*dev
);
271 struct nouveau_timer_engine
{
272 int (*init
)(struct drm_device
*dev
);
273 void (*takedown
)(struct drm_device
*dev
);
274 uint64_t (*read
)(struct drm_device
*dev
);
277 struct nouveau_fb_engine
{
280 int (*init
)(struct drm_device
*dev
);
281 void (*takedown
)(struct drm_device
*dev
);
283 void (*set_region_tiling
)(struct drm_device
*dev
, int i
, uint32_t addr
,
284 uint32_t size
, uint32_t pitch
);
287 struct nouveau_fifo_engine
{
290 struct nouveau_gpuobj
*playlist
[2];
293 int (*init
)(struct drm_device
*);
294 void (*takedown
)(struct drm_device
*);
296 void (*disable
)(struct drm_device
*);
297 void (*enable
)(struct drm_device
*);
298 bool (*reassign
)(struct drm_device
*, bool enable
);
299 bool (*cache_pull
)(struct drm_device
*dev
, bool enable
);
301 int (*channel_id
)(struct drm_device
*);
303 int (*create_context
)(struct nouveau_channel
*);
304 void (*destroy_context
)(struct nouveau_channel
*);
305 int (*load_context
)(struct nouveau_channel
*);
306 int (*unload_context
)(struct drm_device
*);
309 struct nouveau_pgraph_object_method
{
311 int (*exec
)(struct nouveau_channel
*chan
, int grclass
, int mthd
,
315 struct nouveau_pgraph_object_class
{
318 struct nouveau_pgraph_object_method
*methods
;
321 struct nouveau_pgraph_engine
{
322 struct nouveau_pgraph_object_class
*grclass
;
326 /* NV2x/NV3x context table (0x400780) */
327 struct nouveau_gpuobj
*ctx_table
;
329 int (*init
)(struct drm_device
*);
330 void (*takedown
)(struct drm_device
*);
332 void (*fifo_access
)(struct drm_device
*, bool);
334 struct nouveau_channel
*(*channel
)(struct drm_device
*);
335 int (*create_context
)(struct nouveau_channel
*);
336 void (*destroy_context
)(struct nouveau_channel
*);
337 int (*load_context
)(struct nouveau_channel
*);
338 int (*unload_context
)(struct drm_device
*);
340 void (*set_region_tiling
)(struct drm_device
*dev
, int i
, uint32_t addr
,
341 uint32_t size
, uint32_t pitch
);
344 struct nouveau_display_engine
{
345 int (*early_init
)(struct drm_device
*);
346 void (*late_takedown
)(struct drm_device
*);
347 int (*create
)(struct drm_device
*);
348 int (*init
)(struct drm_device
*);
349 void (*destroy
)(struct drm_device
*);
352 struct nouveau_gpio_engine
{
353 int (*init
)(struct drm_device
*);
354 void (*takedown
)(struct drm_device
*);
356 int (*get
)(struct drm_device
*, enum dcb_gpio_tag
);
357 int (*set
)(struct drm_device
*, enum dcb_gpio_tag
, int state
);
359 void (*irq_enable
)(struct drm_device
*, enum dcb_gpio_tag
, bool on
);
362 struct nouveau_pm_voltage_level
{
367 struct nouveau_pm_voltage
{
371 struct nouveau_pm_voltage_level
*level
;
375 #define NOUVEAU_PM_MAX_LEVEL 8
376 struct nouveau_pm_level
{
377 struct device_attribute dev_attr
;
392 struct nouveau_pm_temp_sensor_constants
{
400 struct nouveau_pm_threshold_temp
{
406 struct nouveau_pm_memtiming
{
417 struct nouveau_pm_memtimings
{
419 struct nouveau_pm_memtiming
*timing
;
423 struct nouveau_pm_engine
{
424 struct nouveau_pm_voltage voltage
;
425 struct nouveau_pm_level perflvl
[NOUVEAU_PM_MAX_LEVEL
];
427 struct nouveau_pm_memtimings memtimings
;
428 struct nouveau_pm_temp_sensor_constants sensor_constants
;
429 struct nouveau_pm_threshold_temp threshold_temp
;
431 struct nouveau_pm_level boot
;
432 struct nouveau_pm_level
*cur
;
434 struct device
*hwmon
;
436 int (*clock_get
)(struct drm_device
*, u32 id
);
437 void *(*clock_pre
)(struct drm_device
*, struct nouveau_pm_level
*,
439 void (*clock_set
)(struct drm_device
*, void *);
440 int (*voltage_get
)(struct drm_device
*);
441 int (*voltage_set
)(struct drm_device
*, int voltage
);
442 int (*fanspeed_get
)(struct drm_device
*);
443 int (*fanspeed_set
)(struct drm_device
*, int fanspeed
);
444 int (*temp_get
)(struct drm_device
*);
447 struct nouveau_engine
{
448 struct nouveau_instmem_engine instmem
;
449 struct nouveau_mc_engine mc
;
450 struct nouveau_timer_engine timer
;
451 struct nouveau_fb_engine fb
;
452 struct nouveau_pgraph_engine graph
;
453 struct nouveau_fifo_engine fifo
;
454 struct nouveau_display_engine display
;
455 struct nouveau_gpio_engine gpio
;
456 struct nouveau_pm_engine pm
;
459 struct nouveau_pll_vals
{
463 uint8_t N1
, M1
, N2
, M2
;
465 uint8_t M1
, N1
, M2
, N2
;
470 } __attribute__((packed
));
477 enum nv04_fp_display_regs
{
487 struct nv04_crtc_reg
{
488 unsigned char MiscOutReg
; /* */
491 uint8_t Sequencer
[5];
493 uint8_t Attribute
[21];
494 unsigned char DAC
[768]; /* Internal Colorlookuptable */
504 uint32_t crtc_eng_ctrl
;
507 uint32_t nv10_cursync
;
508 struct nouveau_pll_vals pllvals
;
509 uint32_t ramdac_gen_ctrl
;
515 uint32_t tv_vsync_delay
;
518 uint32_t tv_hsync_delay
;
519 uint32_t tv_hsync_delay2
;
520 uint32_t fp_horiz_regs
[7];
521 uint32_t fp_vert_regs
[7];
524 uint32_t dither_regs
[6];
528 uint32_t fp_margin_color
;
533 uint32_t ctv_regs
[38];
536 struct nv04_output_reg
{
541 struct nv04_mode_state
{
569 uint32_t cursorConfig
;
578 struct nv04_crtc_reg crtc_reg
[2];
581 enum nouveau_card_type
{
591 struct drm_nouveau_private
{
592 struct drm_device
*dev
;
594 /* the card type, takes NV_* as values */
595 enum nouveau_card_type card_type
;
596 /* exact chipset, derived from NV_PMC_BOOT_0 */
602 spinlock_t ramin_lock
;
606 bool ramin_available
;
607 struct drm_mm ramin_heap
;
608 struct list_head gpuobj_list
;
610 struct nouveau_bo
*vga_ram
;
612 struct workqueue_struct
*wq
;
613 struct work_struct irq_work
;
614 struct work_struct hpd_work
;
616 struct list_head vbl_waiting
;
619 struct drm_global_reference mem_global_ref
;
620 struct ttm_bo_global_ref bo_global_ref
;
621 struct ttm_bo_device bdev
;
622 atomic_t validate_sequence
;
628 struct nouveau_bo
*bo
;
631 int fifo_alloc_count
;
632 struct nouveau_channel
*fifos
[NOUVEAU_MAX_CHANNEL_NR
];
634 struct nouveau_engine engine
;
635 struct nouveau_channel
*channel
;
637 /* For PFIFO and PGRAPH. */
638 spinlock_t context_switch_lock
;
640 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
641 struct nouveau_ramht
*ramht
;
642 struct nouveau_gpuobj
*ramfc
;
643 struct nouveau_gpuobj
*ramro
;
645 uint32_t ramin_rsvd_vram
;
649 NOUVEAU_GART_NONE
= 0,
657 struct nouveau_gpuobj
*sg_ctxdma
;
658 struct page
*sg_dummy_page
;
659 dma_addr_t sg_dummy_bus
;
662 /* nv10-nv40 tiling regions */
663 struct nouveau_tile_reg tile
[NOUVEAU_MAX_TILE_NR
];
665 /* VRAM/fb configuration */
667 uint64_t vram_sys_base
;
668 u32 vram_rblock_size
;
671 uint64_t fb_available_size
;
672 uint64_t fb_mappable_pages
;
673 uint64_t fb_aper_free
;
676 /* G8x/G9x virtual address space */
677 uint64_t vm_gart_base
;
678 uint64_t vm_gart_size
;
679 uint64_t vm_vram_base
;
680 uint64_t vm_vram_size
;
682 struct nouveau_gpuobj
*vm_vram_pt
[NV50_VM_VRAM_NR
];
687 struct nv04_mode_state mode_reg
;
688 struct nv04_mode_state saved_reg
;
689 uint32_t saved_vga_font
[4][16384];
691 uint32_t dac_users
[4];
693 struct nouveau_suspend_resume
{
694 uint32_t *ramin_copy
;
697 struct backlight_device
*backlight
;
699 struct nouveau_channel
*evo
;
701 struct dcb_entry
*dcb
;
707 struct dentry
*channel_root
;
710 struct nouveau_fbdev
*nfbdev
;
711 struct apertures_struct
*apertures
;
714 static inline struct drm_nouveau_private
*
715 nouveau_private(struct drm_device
*dev
)
717 return dev
->dev_private
;
720 static inline struct drm_nouveau_private
*
721 nouveau_bdev(struct ttm_bo_device
*bd
)
723 return container_of(bd
, struct drm_nouveau_private
, ttm
.bdev
);
727 nouveau_bo_ref(struct nouveau_bo
*ref
, struct nouveau_bo
**pnvbo
)
729 struct nouveau_bo
*prev
;
735 *pnvbo
= ref
? nouveau_bo(ttm_bo_reference(&ref
->bo
)) : NULL
;
737 struct ttm_buffer_object
*bo
= &prev
->bo
;
745 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
746 struct drm_nouveau_private *nv = dev->dev_private; \
747 if (!nouveau_channel_owner(dev, (cl), (id))) { \
748 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
749 DRM_CURRENTPID, (id)); \
752 (ch) = nv->fifos[(id)]; \
756 extern int nouveau_agpmode
;
757 extern int nouveau_duallink
;
758 extern int nouveau_uscript_lvds
;
759 extern int nouveau_uscript_tmds
;
760 extern int nouveau_vram_pushbuf
;
761 extern int nouveau_vram_notify
;
762 extern int nouveau_fbpercrtc
;
763 extern int nouveau_tv_disable
;
764 extern char *nouveau_tv_norm
;
765 extern int nouveau_reg_debug
;
766 extern char *nouveau_vbios
;
767 extern int nouveau_ignorelid
;
768 extern int nouveau_nofbaccel
;
769 extern int nouveau_noaccel
;
770 extern int nouveau_force_post
;
771 extern int nouveau_override_conntype
;
772 extern char *nouveau_perflvl
;
773 extern int nouveau_perflvl_wr
;
775 extern int nouveau_pci_suspend(struct pci_dev
*pdev
, pm_message_t pm_state
);
776 extern int nouveau_pci_resume(struct pci_dev
*pdev
);
778 /* nouveau_state.c */
779 extern void nouveau_preclose(struct drm_device
*dev
, struct drm_file
*);
780 extern int nouveau_load(struct drm_device
*, unsigned long flags
);
781 extern int nouveau_firstopen(struct drm_device
*);
782 extern void nouveau_lastclose(struct drm_device
*);
783 extern int nouveau_unload(struct drm_device
*);
784 extern int nouveau_ioctl_getparam(struct drm_device
*, void *data
,
786 extern int nouveau_ioctl_setparam(struct drm_device
*, void *data
,
788 extern bool nouveau_wait_until(struct drm_device
*, uint64_t timeout
,
789 uint32_t reg
, uint32_t mask
, uint32_t val
);
790 extern bool nouveau_wait_for_idle(struct drm_device
*);
791 extern int nouveau_card_init(struct drm_device
*);
794 extern int nouveau_mem_vram_init(struct drm_device
*);
795 extern void nouveau_mem_vram_fini(struct drm_device
*);
796 extern int nouveau_mem_gart_init(struct drm_device
*);
797 extern void nouveau_mem_gart_fini(struct drm_device
*);
798 extern int nouveau_mem_init_agp(struct drm_device
*);
799 extern int nouveau_mem_reset_agp(struct drm_device
*);
800 extern void nouveau_mem_close(struct drm_device
*);
801 extern struct nouveau_tile_reg
*nv10_mem_set_tiling(struct drm_device
*dev
,
805 extern void nv10_mem_expire_tiling(struct drm_device
*dev
,
806 struct nouveau_tile_reg
*tile
,
807 struct nouveau_fence
*fence
);
808 extern int nv50_mem_vm_bind_linear(struct drm_device
*, uint64_t virt
,
809 uint32_t size
, uint32_t flags
,
811 extern void nv50_mem_vm_unbind(struct drm_device
*, uint64_t virt
,
814 /* nouveau_notifier.c */
815 extern int nouveau_notifier_init_channel(struct nouveau_channel
*);
816 extern void nouveau_notifier_takedown_channel(struct nouveau_channel
*);
817 extern int nouveau_notifier_alloc(struct nouveau_channel
*, uint32_t handle
,
818 int cout
, uint32_t *offset
);
819 extern int nouveau_notifier_offset(struct nouveau_gpuobj
*, uint32_t *);
820 extern int nouveau_ioctl_notifier_alloc(struct drm_device
*, void *data
,
822 extern int nouveau_ioctl_notifier_free(struct drm_device
*, void *data
,
825 /* nouveau_channel.c */
826 extern struct drm_ioctl_desc nouveau_ioctls
[];
827 extern int nouveau_max_ioctl
;
828 extern void nouveau_channel_cleanup(struct drm_device
*, struct drm_file
*);
829 extern int nouveau_channel_owner(struct drm_device
*, struct drm_file
*,
831 extern int nouveau_channel_alloc(struct drm_device
*dev
,
832 struct nouveau_channel
**chan
,
833 struct drm_file
*file_priv
,
834 uint32_t fb_ctxdma
, uint32_t tt_ctxdma
);
835 extern void nouveau_channel_free(struct nouveau_channel
*);
837 /* nouveau_object.c */
838 extern int nouveau_gpuobj_early_init(struct drm_device
*);
839 extern int nouveau_gpuobj_init(struct drm_device
*);
840 extern void nouveau_gpuobj_takedown(struct drm_device
*);
841 extern int nouveau_gpuobj_suspend(struct drm_device
*dev
);
842 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device
*dev
);
843 extern void nouveau_gpuobj_resume(struct drm_device
*dev
);
844 extern int nouveau_gpuobj_channel_init(struct nouveau_channel
*,
845 uint32_t vram_h
, uint32_t tt_h
);
846 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel
*);
847 extern int nouveau_gpuobj_new(struct drm_device
*, struct nouveau_channel
*,
848 uint32_t size
, int align
, uint32_t flags
,
849 struct nouveau_gpuobj
**);
850 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj
*,
851 struct nouveau_gpuobj
**);
852 extern int nouveau_gpuobj_new_fake(struct drm_device
*, u32 pinst
, u64 vinst
,
854 struct nouveau_gpuobj
**);
855 extern int nouveau_gpuobj_dma_new(struct nouveau_channel
*, int class,
856 uint64_t offset
, uint64_t size
, int access
,
857 int target
, struct nouveau_gpuobj
**);
858 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel
*,
859 uint64_t offset
, uint64_t size
,
860 int access
, struct nouveau_gpuobj
**,
862 extern int nouveau_gpuobj_gr_new(struct nouveau_channel
*, int class,
863 struct nouveau_gpuobj
**);
864 extern int nouveau_gpuobj_sw_new(struct nouveau_channel
*, int class,
865 struct nouveau_gpuobj
**);
866 extern int nouveau_ioctl_grobj_alloc(struct drm_device
*, void *data
,
868 extern int nouveau_ioctl_gpuobj_free(struct drm_device
*, void *data
,
872 extern irqreturn_t
nouveau_irq_handler(DRM_IRQ_ARGS
);
873 extern void nouveau_irq_preinstall(struct drm_device
*);
874 extern int nouveau_irq_postinstall(struct drm_device
*);
875 extern void nouveau_irq_uninstall(struct drm_device
*);
877 /* nouveau_sgdma.c */
878 extern int nouveau_sgdma_init(struct drm_device
*);
879 extern void nouveau_sgdma_takedown(struct drm_device
*);
880 extern int nouveau_sgdma_get_page(struct drm_device
*, uint32_t offset
,
882 extern struct ttm_backend
*nouveau_sgdma_init_ttm(struct drm_device
*);
884 /* nouveau_debugfs.c */
885 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
886 extern int nouveau_debugfs_init(struct drm_minor
*);
887 extern void nouveau_debugfs_takedown(struct drm_minor
*);
888 extern int nouveau_debugfs_channel_init(struct nouveau_channel
*);
889 extern void nouveau_debugfs_channel_fini(struct nouveau_channel
*);
892 nouveau_debugfs_init(struct drm_minor
*minor
)
897 static inline void nouveau_debugfs_takedown(struct drm_minor
*minor
)
902 nouveau_debugfs_channel_init(struct nouveau_channel
*chan
)
908 nouveau_debugfs_channel_fini(struct nouveau_channel
*chan
)
914 extern void nouveau_dma_pre_init(struct nouveau_channel
*);
915 extern int nouveau_dma_init(struct nouveau_channel
*);
916 extern int nouveau_dma_wait(struct nouveau_channel
*, int slots
, int size
);
919 #define ROM_BIOS_PAGE 4096
920 #if defined(CONFIG_ACPI)
921 void nouveau_register_dsm_handler(void);
922 void nouveau_unregister_dsm_handler(void);
923 int nouveau_acpi_get_bios_chunk(uint8_t *bios
, int offset
, int len
);
924 bool nouveau_acpi_rom_supported(struct pci_dev
*pdev
);
925 int nouveau_acpi_edid(struct drm_device
*, struct drm_connector
*);
927 static inline void nouveau_register_dsm_handler(void) {}
928 static inline void nouveau_unregister_dsm_handler(void) {}
929 static inline bool nouveau_acpi_rom_supported(struct pci_dev
*pdev
) { return false; }
930 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios
, int offset
, int len
) { return -EINVAL
; }
931 static inline int nouveau_acpi_edid(struct drm_device
*dev
, struct drm_connector
*connector
) { return -EINVAL
; }
934 /* nouveau_backlight.c */
935 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
936 extern int nouveau_backlight_init(struct drm_device
*);
937 extern void nouveau_backlight_exit(struct drm_device
*);
939 static inline int nouveau_backlight_init(struct drm_device
*dev
)
944 static inline void nouveau_backlight_exit(struct drm_device
*dev
) { }
948 extern int nouveau_bios_init(struct drm_device
*);
949 extern void nouveau_bios_takedown(struct drm_device
*dev
);
950 extern int nouveau_run_vbios_init(struct drm_device
*);
951 extern void nouveau_bios_run_init_table(struct drm_device
*, uint16_t table
,
953 extern struct dcb_gpio_entry
*nouveau_bios_gpio_entry(struct drm_device
*,
955 extern struct dcb_connector_table_entry
*
956 nouveau_bios_connector_entry(struct drm_device
*, int index
);
957 extern u32
get_pll_register(struct drm_device
*, enum pll_types
);
958 extern int get_pll_limits(struct drm_device
*, uint32_t limit_match
,
960 extern int nouveau_bios_run_display_table(struct drm_device
*,
962 uint32_t script
, int pxclk
);
963 extern void *nouveau_bios_dp_table(struct drm_device
*, struct dcb_entry
*,
965 extern bool nouveau_bios_fp_mode(struct drm_device
*, struct drm_display_mode
*);
966 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device
*);
967 extern int nouveau_bios_parse_lvds_table(struct drm_device
*, int pxclk
,
968 bool *dl
, bool *if_is_24bit
);
969 extern int run_tmds_table(struct drm_device
*, struct dcb_entry
*,
970 int head
, int pxclk
);
971 extern int call_lvds_script(struct drm_device
*, struct dcb_entry
*, int head
,
972 enum LVDS_script
, int pxclk
);
975 int nouveau_ttm_global_init(struct drm_nouveau_private
*);
976 void nouveau_ttm_global_release(struct drm_nouveau_private
*);
977 int nouveau_ttm_mmap(struct file
*, struct vm_area_struct
*);
980 int nouveau_dp_auxch(struct nouveau_i2c_chan
*auxch
, int cmd
, int addr
,
981 uint8_t *data
, int data_nr
);
982 bool nouveau_dp_detect(struct drm_encoder
*);
983 bool nouveau_dp_link_train(struct drm_encoder
*);
986 extern int nv04_fb_init(struct drm_device
*);
987 extern void nv04_fb_takedown(struct drm_device
*);
990 extern int nv10_fb_init(struct drm_device
*);
991 extern void nv10_fb_takedown(struct drm_device
*);
992 extern void nv10_fb_set_region_tiling(struct drm_device
*, int, uint32_t,
996 extern int nv30_fb_init(struct drm_device
*);
997 extern void nv30_fb_takedown(struct drm_device
*);
1000 extern int nv40_fb_init(struct drm_device
*);
1001 extern void nv40_fb_takedown(struct drm_device
*);
1002 extern void nv40_fb_set_region_tiling(struct drm_device
*, int, uint32_t,
1003 uint32_t, uint32_t);
1005 extern int nv50_fb_init(struct drm_device
*);
1006 extern void nv50_fb_takedown(struct drm_device
*);
1007 extern void nv50_fb_vm_trap(struct drm_device
*, int display
, const char *);
1010 extern int nvc0_fb_init(struct drm_device
*);
1011 extern void nvc0_fb_takedown(struct drm_device
*);
1014 extern int nv04_fifo_init(struct drm_device
*);
1015 extern void nv04_fifo_disable(struct drm_device
*);
1016 extern void nv04_fifo_enable(struct drm_device
*);
1017 extern bool nv04_fifo_reassign(struct drm_device
*, bool);
1018 extern bool nv04_fifo_cache_pull(struct drm_device
*, bool);
1019 extern int nv04_fifo_channel_id(struct drm_device
*);
1020 extern int nv04_fifo_create_context(struct nouveau_channel
*);
1021 extern void nv04_fifo_destroy_context(struct nouveau_channel
*);
1022 extern int nv04_fifo_load_context(struct nouveau_channel
*);
1023 extern int nv04_fifo_unload_context(struct drm_device
*);
1026 extern int nv10_fifo_init(struct drm_device
*);
1027 extern int nv10_fifo_channel_id(struct drm_device
*);
1028 extern int nv10_fifo_create_context(struct nouveau_channel
*);
1029 extern void nv10_fifo_destroy_context(struct nouveau_channel
*);
1030 extern int nv10_fifo_load_context(struct nouveau_channel
*);
1031 extern int nv10_fifo_unload_context(struct drm_device
*);
1034 extern int nv40_fifo_init(struct drm_device
*);
1035 extern int nv40_fifo_create_context(struct nouveau_channel
*);
1036 extern void nv40_fifo_destroy_context(struct nouveau_channel
*);
1037 extern int nv40_fifo_load_context(struct nouveau_channel
*);
1038 extern int nv40_fifo_unload_context(struct drm_device
*);
1041 extern int nv50_fifo_init(struct drm_device
*);
1042 extern void nv50_fifo_takedown(struct drm_device
*);
1043 extern int nv50_fifo_channel_id(struct drm_device
*);
1044 extern int nv50_fifo_create_context(struct nouveau_channel
*);
1045 extern void nv50_fifo_destroy_context(struct nouveau_channel
*);
1046 extern int nv50_fifo_load_context(struct nouveau_channel
*);
1047 extern int nv50_fifo_unload_context(struct drm_device
*);
1050 extern int nvc0_fifo_init(struct drm_device
*);
1051 extern void nvc0_fifo_takedown(struct drm_device
*);
1052 extern void nvc0_fifo_disable(struct drm_device
*);
1053 extern void nvc0_fifo_enable(struct drm_device
*);
1054 extern bool nvc0_fifo_reassign(struct drm_device
*, bool);
1055 extern bool nvc0_fifo_cache_pull(struct drm_device
*, bool);
1056 extern int nvc0_fifo_channel_id(struct drm_device
*);
1057 extern int nvc0_fifo_create_context(struct nouveau_channel
*);
1058 extern void nvc0_fifo_destroy_context(struct nouveau_channel
*);
1059 extern int nvc0_fifo_load_context(struct nouveau_channel
*);
1060 extern int nvc0_fifo_unload_context(struct drm_device
*);
1063 extern struct nouveau_pgraph_object_class nv04_graph_grclass
[];
1064 extern int nv04_graph_init(struct drm_device
*);
1065 extern void nv04_graph_takedown(struct drm_device
*);
1066 extern void nv04_graph_fifo_access(struct drm_device
*, bool);
1067 extern struct nouveau_channel
*nv04_graph_channel(struct drm_device
*);
1068 extern int nv04_graph_create_context(struct nouveau_channel
*);
1069 extern void nv04_graph_destroy_context(struct nouveau_channel
*);
1070 extern int nv04_graph_load_context(struct nouveau_channel
*);
1071 extern int nv04_graph_unload_context(struct drm_device
*);
1072 extern void nv04_graph_context_switch(struct drm_device
*);
1075 extern struct nouveau_pgraph_object_class nv10_graph_grclass
[];
1076 extern int nv10_graph_init(struct drm_device
*);
1077 extern void nv10_graph_takedown(struct drm_device
*);
1078 extern struct nouveau_channel
*nv10_graph_channel(struct drm_device
*);
1079 extern int nv10_graph_create_context(struct nouveau_channel
*);
1080 extern void nv10_graph_destroy_context(struct nouveau_channel
*);
1081 extern int nv10_graph_load_context(struct nouveau_channel
*);
1082 extern int nv10_graph_unload_context(struct drm_device
*);
1083 extern void nv10_graph_context_switch(struct drm_device
*);
1084 extern void nv10_graph_set_region_tiling(struct drm_device
*, int, uint32_t,
1085 uint32_t, uint32_t);
1088 extern struct nouveau_pgraph_object_class nv20_graph_grclass
[];
1089 extern struct nouveau_pgraph_object_class nv30_graph_grclass
[];
1090 extern int nv20_graph_create_context(struct nouveau_channel
*);
1091 extern void nv20_graph_destroy_context(struct nouveau_channel
*);
1092 extern int nv20_graph_load_context(struct nouveau_channel
*);
1093 extern int nv20_graph_unload_context(struct drm_device
*);
1094 extern int nv20_graph_init(struct drm_device
*);
1095 extern void nv20_graph_takedown(struct drm_device
*);
1096 extern int nv30_graph_init(struct drm_device
*);
1097 extern void nv20_graph_set_region_tiling(struct drm_device
*, int, uint32_t,
1098 uint32_t, uint32_t);
1101 extern struct nouveau_pgraph_object_class nv40_graph_grclass
[];
1102 extern int nv40_graph_init(struct drm_device
*);
1103 extern void nv40_graph_takedown(struct drm_device
*);
1104 extern struct nouveau_channel
*nv40_graph_channel(struct drm_device
*);
1105 extern int nv40_graph_create_context(struct nouveau_channel
*);
1106 extern void nv40_graph_destroy_context(struct nouveau_channel
*);
1107 extern int nv40_graph_load_context(struct nouveau_channel
*);
1108 extern int nv40_graph_unload_context(struct drm_device
*);
1109 extern void nv40_grctx_init(struct nouveau_grctx
*);
1110 extern void nv40_graph_set_region_tiling(struct drm_device
*, int, uint32_t,
1111 uint32_t, uint32_t);
1114 extern struct nouveau_pgraph_object_class nv50_graph_grclass
[];
1115 extern int nv50_graph_init(struct drm_device
*);
1116 extern void nv50_graph_takedown(struct drm_device
*);
1117 extern void nv50_graph_fifo_access(struct drm_device
*, bool);
1118 extern struct nouveau_channel
*nv50_graph_channel(struct drm_device
*);
1119 extern int nv50_graph_create_context(struct nouveau_channel
*);
1120 extern void nv50_graph_destroy_context(struct nouveau_channel
*);
1121 extern int nv50_graph_load_context(struct nouveau_channel
*);
1122 extern int nv50_graph_unload_context(struct drm_device
*);
1123 extern void nv50_graph_context_switch(struct drm_device
*);
1124 extern int nv50_grctx_init(struct nouveau_grctx
*);
1127 extern int nvc0_graph_init(struct drm_device
*);
1128 extern void nvc0_graph_takedown(struct drm_device
*);
1129 extern void nvc0_graph_fifo_access(struct drm_device
*, bool);
1130 extern struct nouveau_channel
*nvc0_graph_channel(struct drm_device
*);
1131 extern int nvc0_graph_create_context(struct nouveau_channel
*);
1132 extern void nvc0_graph_destroy_context(struct nouveau_channel
*);
1133 extern int nvc0_graph_load_context(struct nouveau_channel
*);
1134 extern int nvc0_graph_unload_context(struct drm_device
*);
1136 /* nv04_instmem.c */
1137 extern int nv04_instmem_init(struct drm_device
*);
1138 extern void nv04_instmem_takedown(struct drm_device
*);
1139 extern int nv04_instmem_suspend(struct drm_device
*);
1140 extern void nv04_instmem_resume(struct drm_device
*);
1141 extern int nv04_instmem_populate(struct drm_device
*, struct nouveau_gpuobj
*,
1143 extern void nv04_instmem_clear(struct drm_device
*, struct nouveau_gpuobj
*);
1144 extern int nv04_instmem_bind(struct drm_device
*, struct nouveau_gpuobj
*);
1145 extern int nv04_instmem_unbind(struct drm_device
*, struct nouveau_gpuobj
*);
1146 extern void nv04_instmem_flush(struct drm_device
*);
1148 /* nv50_instmem.c */
1149 extern int nv50_instmem_init(struct drm_device
*);
1150 extern void nv50_instmem_takedown(struct drm_device
*);
1151 extern int nv50_instmem_suspend(struct drm_device
*);
1152 extern void nv50_instmem_resume(struct drm_device
*);
1153 extern int nv50_instmem_populate(struct drm_device
*, struct nouveau_gpuobj
*,
1155 extern void nv50_instmem_clear(struct drm_device
*, struct nouveau_gpuobj
*);
1156 extern int nv50_instmem_bind(struct drm_device
*, struct nouveau_gpuobj
*);
1157 extern int nv50_instmem_unbind(struct drm_device
*, struct nouveau_gpuobj
*);
1158 extern void nv50_instmem_flush(struct drm_device
*);
1159 extern void nv84_instmem_flush(struct drm_device
*);
1160 extern void nv50_vm_flush(struct drm_device
*, int engine
);
1162 /* nvc0_instmem.c */
1163 extern int nvc0_instmem_init(struct drm_device
*);
1164 extern void nvc0_instmem_takedown(struct drm_device
*);
1165 extern int nvc0_instmem_suspend(struct drm_device
*);
1166 extern void nvc0_instmem_resume(struct drm_device
*);
1167 extern int nvc0_instmem_populate(struct drm_device
*, struct nouveau_gpuobj
*,
1169 extern void nvc0_instmem_clear(struct drm_device
*, struct nouveau_gpuobj
*);
1170 extern int nvc0_instmem_bind(struct drm_device
*, struct nouveau_gpuobj
*);
1171 extern int nvc0_instmem_unbind(struct drm_device
*, struct nouveau_gpuobj
*);
1172 extern void nvc0_instmem_flush(struct drm_device
*);
1175 extern int nv04_mc_init(struct drm_device
*);
1176 extern void nv04_mc_takedown(struct drm_device
*);
1179 extern int nv40_mc_init(struct drm_device
*);
1180 extern void nv40_mc_takedown(struct drm_device
*);
1183 extern int nv50_mc_init(struct drm_device
*);
1184 extern void nv50_mc_takedown(struct drm_device
*);
1187 extern int nv04_timer_init(struct drm_device
*);
1188 extern uint64_t nv04_timer_read(struct drm_device
*);
1189 extern void nv04_timer_takedown(struct drm_device
*);
1191 extern long nouveau_compat_ioctl(struct file
*file
, unsigned int cmd
,
1195 extern int nv04_dac_create(struct drm_connector
*, struct dcb_entry
*);
1196 extern uint32_t nv17_dac_sample_load(struct drm_encoder
*encoder
);
1197 extern int nv04_dac_output_offset(struct drm_encoder
*encoder
);
1198 extern void nv04_dac_update_dacclk(struct drm_encoder
*encoder
, bool enable
);
1199 extern bool nv04_dac_in_use(struct drm_encoder
*encoder
);
1202 extern int nv04_dfp_create(struct drm_connector
*, struct dcb_entry
*);
1203 extern int nv04_dfp_get_bound_head(struct drm_device
*dev
, struct dcb_entry
*dcbent
);
1204 extern void nv04_dfp_bind_head(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
1206 extern void nv04_dfp_disable(struct drm_device
*dev
, int head
);
1207 extern void nv04_dfp_update_fp_control(struct drm_encoder
*encoder
, int mode
);
1210 extern int nv04_tv_identify(struct drm_device
*dev
, int i2c_index
);
1211 extern int nv04_tv_create(struct drm_connector
*, struct dcb_entry
*);
1214 extern int nv17_tv_create(struct drm_connector
*, struct dcb_entry
*);
1216 /* nv04_display.c */
1217 extern int nv04_display_early_init(struct drm_device
*);
1218 extern void nv04_display_late_takedown(struct drm_device
*);
1219 extern int nv04_display_create(struct drm_device
*);
1220 extern int nv04_display_init(struct drm_device
*);
1221 extern void nv04_display_destroy(struct drm_device
*);
1224 extern int nv04_crtc_create(struct drm_device
*, int index
);
1227 extern struct ttm_bo_driver nouveau_bo_driver
;
1228 extern int nouveau_bo_new(struct drm_device
*, struct nouveau_channel
*,
1229 int size
, int align
, uint32_t flags
,
1230 uint32_t tile_mode
, uint32_t tile_flags
,
1231 bool no_vm
, bool mappable
, struct nouveau_bo
**);
1232 extern int nouveau_bo_pin(struct nouveau_bo
*, uint32_t flags
);
1233 extern int nouveau_bo_unpin(struct nouveau_bo
*);
1234 extern int nouveau_bo_map(struct nouveau_bo
*);
1235 extern void nouveau_bo_unmap(struct nouveau_bo
*);
1236 extern void nouveau_bo_placement_set(struct nouveau_bo
*, uint32_t type
,
1238 extern u16
nouveau_bo_rd16(struct nouveau_bo
*nvbo
, unsigned index
);
1239 extern void nouveau_bo_wr16(struct nouveau_bo
*nvbo
, unsigned index
, u16 val
);
1240 extern u32
nouveau_bo_rd32(struct nouveau_bo
*nvbo
, unsigned index
);
1241 extern void nouveau_bo_wr32(struct nouveau_bo
*nvbo
, unsigned index
, u32 val
);
1242 extern int nouveau_bo_sync_gpu(struct nouveau_bo
*, struct nouveau_channel
*);
1244 /* nouveau_fence.c */
1245 struct nouveau_fence
;
1246 extern int nouveau_fence_init(struct drm_device
*);
1247 extern void nouveau_fence_fini(struct drm_device
*);
1248 extern int nouveau_fence_channel_init(struct nouveau_channel
*);
1249 extern void nouveau_fence_channel_fini(struct nouveau_channel
*);
1250 extern void nouveau_fence_update(struct nouveau_channel
*);
1251 extern int nouveau_fence_new(struct nouveau_channel
*, struct nouveau_fence
**,
1253 extern int nouveau_fence_emit(struct nouveau_fence
*);
1254 extern void nouveau_fence_work(struct nouveau_fence
*fence
,
1255 void (*work
)(void *priv
, bool signalled
),
1257 struct nouveau_channel
*nouveau_fence_channel(struct nouveau_fence
*);
1258 extern bool nouveau_fence_signalled(void *obj
, void *arg
);
1259 extern int nouveau_fence_wait(void *obj
, void *arg
, bool lazy
, bool intr
);
1260 extern int nouveau_fence_sync(struct nouveau_fence
*, struct nouveau_channel
*);
1261 extern int nouveau_fence_flush(void *obj
, void *arg
);
1262 extern void nouveau_fence_unref(void **obj
);
1263 extern void *nouveau_fence_ref(void *obj
);
1266 extern int nouveau_gem_new(struct drm_device
*, struct nouveau_channel
*,
1267 int size
, int align
, uint32_t flags
,
1268 uint32_t tile_mode
, uint32_t tile_flags
,
1269 bool no_vm
, bool mappable
, struct nouveau_bo
**);
1270 extern int nouveau_gem_object_new(struct drm_gem_object
*);
1271 extern void nouveau_gem_object_del(struct drm_gem_object
*);
1272 extern int nouveau_gem_ioctl_new(struct drm_device
*, void *,
1274 extern int nouveau_gem_ioctl_pushbuf(struct drm_device
*, void *,
1276 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device
*, void *,
1278 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device
*, void *,
1280 extern int nouveau_gem_ioctl_info(struct drm_device
*, void *,
1284 int nv10_gpio_get(struct drm_device
*dev
, enum dcb_gpio_tag tag
);
1285 int nv10_gpio_set(struct drm_device
*dev
, enum dcb_gpio_tag tag
, int state
);
1288 int nv50_gpio_init(struct drm_device
*dev
);
1289 int nv50_gpio_get(struct drm_device
*dev
, enum dcb_gpio_tag tag
);
1290 int nv50_gpio_set(struct drm_device
*dev
, enum dcb_gpio_tag tag
, int state
);
1291 void nv50_gpio_irq_enable(struct drm_device
*, enum dcb_gpio_tag
, bool on
);
1294 int nv50_calc_pll(struct drm_device
*, struct pll_lims
*, int clk
,
1295 int *N1
, int *M1
, int *N2
, int *M2
, int *P
);
1296 int nv50_calc_pll2(struct drm_device
*, struct pll_lims
*,
1297 int clk
, int *N
, int *fN
, int *M
, int *P
);
1299 #ifndef ioread32_native
1301 #define ioread16_native ioread16be
1302 #define iowrite16_native iowrite16be
1303 #define ioread32_native ioread32be
1304 #define iowrite32_native iowrite32be
1305 #else /* def __BIG_ENDIAN */
1306 #define ioread16_native ioread16
1307 #define iowrite16_native iowrite16
1308 #define ioread32_native ioread32
1309 #define iowrite32_native iowrite32
1310 #endif /* def __BIG_ENDIAN else */
1311 #endif /* !ioread32_native */
1313 /* channel control reg access */
1314 static inline u32
nvchan_rd32(struct nouveau_channel
*chan
, unsigned reg
)
1316 return ioread32_native(chan
->user
+ reg
);
1319 static inline void nvchan_wr32(struct nouveau_channel
*chan
,
1320 unsigned reg
, u32 val
)
1322 iowrite32_native(val
, chan
->user
+ reg
);
1325 /* register access */
1326 static inline u32
nv_rd32(struct drm_device
*dev
, unsigned reg
)
1328 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1329 return ioread32_native(dev_priv
->mmio
+ reg
);
1332 static inline void nv_wr32(struct drm_device
*dev
, unsigned reg
, u32 val
)
1334 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1335 iowrite32_native(val
, dev_priv
->mmio
+ reg
);
1338 static inline u32
nv_mask(struct drm_device
*dev
, u32 reg
, u32 mask
, u32 val
)
1340 u32 tmp
= nv_rd32(dev
, reg
);
1341 nv_wr32(dev
, reg
, (tmp
& ~mask
) | val
);
1345 static inline u8
nv_rd08(struct drm_device
*dev
, unsigned reg
)
1347 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1348 return ioread8(dev_priv
->mmio
+ reg
);
1351 static inline void nv_wr08(struct drm_device
*dev
, unsigned reg
, u8 val
)
1353 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1354 iowrite8(val
, dev_priv
->mmio
+ reg
);
1357 #define nv_wait(dev, reg, mask, val) \
1358 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1361 static inline u32
nv_ri32(struct drm_device
*dev
, unsigned offset
)
1363 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1364 return ioread32_native(dev_priv
->ramin
+ offset
);
1367 static inline void nv_wi32(struct drm_device
*dev
, unsigned offset
, u32 val
)
1369 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1370 iowrite32_native(val
, dev_priv
->ramin
+ offset
);
1374 extern u32
nv_ro32(struct nouveau_gpuobj
*, u32 offset
);
1375 extern void nv_wo32(struct nouveau_gpuobj
*, u32 offset
, u32 val
);
1379 * Argument d is (struct drm_device *).
1381 #define NV_PRINTK(level, d, fmt, arg...) \
1382 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1383 pci_name(d->pdev), ##arg)
1384 #ifndef NV_DEBUG_NOTRACE
1385 #define NV_DEBUG(d, fmt, arg...) do { \
1386 if (drm_debug & DRM_UT_DRIVER) { \
1387 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1391 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1392 if (drm_debug & DRM_UT_KMS) { \
1393 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1398 #define NV_DEBUG(d, fmt, arg...) do { \
1399 if (drm_debug & DRM_UT_DRIVER) \
1400 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1402 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1403 if (drm_debug & DRM_UT_KMS) \
1404 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1407 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1408 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1409 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1410 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1411 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1413 /* nouveau_reg_debug bitmask */
1415 NOUVEAU_REG_DEBUG_MC
= 0x1,
1416 NOUVEAU_REG_DEBUG_VIDEO
= 0x2,
1417 NOUVEAU_REG_DEBUG_FB
= 0x4,
1418 NOUVEAU_REG_DEBUG_EXTDEV
= 0x8,
1419 NOUVEAU_REG_DEBUG_CRTC
= 0x10,
1420 NOUVEAU_REG_DEBUG_RAMDAC
= 0x20,
1421 NOUVEAU_REG_DEBUG_VGACRTC
= 0x40,
1422 NOUVEAU_REG_DEBUG_RMVIO
= 0x80,
1423 NOUVEAU_REG_DEBUG_VGAATTR
= 0x100,
1424 NOUVEAU_REG_DEBUG_EVO
= 0x200,
1427 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1428 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1429 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1433 nv_two_heads(struct drm_device
*dev
)
1435 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1436 const int impl
= dev
->pci_device
& 0x0ff0;
1438 if (dev_priv
->card_type
>= NV_10
&& impl
!= 0x0100 &&
1439 impl
!= 0x0150 && impl
!= 0x01a0 && impl
!= 0x0200)
1446 nv_gf4_disp_arch(struct drm_device
*dev
)
1448 return nv_two_heads(dev
) && (dev
->pci_device
& 0x0ff0) != 0x0110;
1452 nv_two_reg_pll(struct drm_device
*dev
)
1454 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1455 const int impl
= dev
->pci_device
& 0x0ff0;
1457 if (impl
== 0x0310 || impl
== 0x0340 || dev_priv
->card_type
>= NV_40
)
1463 nv_match_device(struct drm_device
*dev
, unsigned device
,
1464 unsigned sub_vendor
, unsigned sub_device
)
1466 return dev
->pdev
->device
== device
&&
1467 dev
->pdev
->subsystem_vendor
== sub_vendor
&&
1468 dev
->pdev
->subsystem_device
== sub_device
;
1471 #define NV_SW 0x0000506e
1472 #define NV_SW_DMA_SEMAPHORE 0x00000060
1473 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1474 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1475 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1476 #define NV_SW_YIELD 0x00000080
1477 #define NV_SW_DMA_VBLSEM 0x0000018c
1478 #define NV_SW_VBLSEM_OFFSET 0x00000400
1479 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1480 #define NV_SW_VBLSEM_RELEASE 0x00000408
1482 #endif /* __NOUVEAU_DRV_H__ */