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drm/nouveau: allow irq handlers to be installed by engine-specific code
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 bool used;
70 uint32_t addr;
71 uint32_t limit;
72 uint32_t pitch;
73 uint32_t zcomp;
74 struct drm_mm_node *tag_mem;
75 struct nouveau_fence *fence;
76 };
77
78 struct nouveau_bo {
79 struct ttm_buffer_object bo;
80 struct ttm_placement placement;
81 u32 placements[3];
82 u32 busy_placements[3];
83 struct ttm_bo_kmap_obj kmap;
84 struct list_head head;
85
86 /* protected by ttm_bo_reserve() */
87 struct drm_file *reserved_by;
88 struct list_head entry;
89 int pbbo_index;
90 bool validate_mapped;
91
92 struct nouveau_channel *channel;
93
94 bool mappable;
95 bool no_vm;
96
97 uint32_t tile_mode;
98 uint32_t tile_flags;
99 struct nouveau_tile_reg *tile;
100
101 struct drm_gem_object *gem;
102 int pin_refcnt;
103 };
104
105 #define nouveau_bo_tile_layout(nvbo) \
106 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
107
108 static inline struct nouveau_bo *
109 nouveau_bo(struct ttm_buffer_object *bo)
110 {
111 return container_of(bo, struct nouveau_bo, bo);
112 }
113
114 static inline struct nouveau_bo *
115 nouveau_gem_object(struct drm_gem_object *gem)
116 {
117 return gem ? gem->driver_private : NULL;
118 }
119
120 /* TODO: submit equivalent to TTM generic API upstream? */
121 static inline void __iomem *
122 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
123 {
124 bool is_iomem;
125 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
126 &nvbo->kmap, &is_iomem);
127 WARN_ON_ONCE(ioptr && !is_iomem);
128 return ioptr;
129 }
130
131 enum nouveau_flags {
132 NV_NFORCE = 0x10000000,
133 NV_NFORCE2 = 0x20000000
134 };
135
136 #define NVOBJ_ENGINE_SW 0
137 #define NVOBJ_ENGINE_GR 1
138 #define NVOBJ_ENGINE_PPP 2
139 #define NVOBJ_ENGINE_COPY 3
140 #define NVOBJ_ENGINE_VP 4
141 #define NVOBJ_ENGINE_CRYPT 5
142 #define NVOBJ_ENGINE_BSP 6
143 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
144 #define NVOBJ_ENGINE_INT 0xdeadbeef
145
146 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
147 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
148 struct nouveau_gpuobj {
149 struct drm_device *dev;
150 struct kref refcount;
151 struct list_head list;
152
153 struct drm_mm_node *im_pramin;
154 struct nouveau_bo *im_backing;
155 uint32_t *im_backing_suspend;
156 int im_bound;
157
158 uint32_t flags;
159
160 u32 size;
161 u32 pinst;
162 u32 cinst;
163 u64 vinst;
164
165 uint32_t engine;
166 uint32_t class;
167
168 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
169 void *priv;
170 };
171
172 struct nouveau_page_flip_state {
173 struct list_head head;
174 struct drm_pending_vblank_event *event;
175 int crtc, bpp, pitch, x, y;
176 uint64_t offset;
177 };
178
179 enum nouveau_channel_mutex_class {
180 NOUVEAU_UCHANNEL_MUTEX,
181 NOUVEAU_KCHANNEL_MUTEX
182 };
183
184 struct nouveau_channel {
185 struct drm_device *dev;
186 int id;
187
188 /* references to the channel data structure */
189 struct kref ref;
190 /* users of the hardware channel resources, the hardware
191 * context will be kicked off when it reaches zero. */
192 atomic_t users;
193 struct mutex mutex;
194
195 /* owner of this fifo */
196 struct drm_file *file_priv;
197 /* mapping of the fifo itself */
198 struct drm_local_map *map;
199
200 /* mapping of the regs controling the fifo */
201 void __iomem *user;
202 uint32_t user_get;
203 uint32_t user_put;
204
205 /* Fencing */
206 struct {
207 /* lock protects the pending list only */
208 spinlock_t lock;
209 struct list_head pending;
210 uint32_t sequence;
211 uint32_t sequence_ack;
212 atomic_t last_sequence_irq;
213 } fence;
214
215 /* DMA push buffer */
216 struct nouveau_gpuobj *pushbuf;
217 struct nouveau_bo *pushbuf_bo;
218 uint32_t pushbuf_base;
219
220 /* Notifier memory */
221 struct nouveau_bo *notifier_bo;
222 struct drm_mm notifier_heap;
223
224 /* PFIFO context */
225 struct nouveau_gpuobj *ramfc;
226 struct nouveau_gpuobj *cache;
227
228 /* PGRAPH context */
229 /* XXX may be merge 2 pointers as private data ??? */
230 struct nouveau_gpuobj *ramin_grctx;
231 struct nouveau_gpuobj *crypt_ctx;
232 void *pgraph_ctx;
233
234 /* NV50 VM */
235 struct nouveau_gpuobj *vm_pd;
236 struct nouveau_gpuobj *vm_gart_pt;
237 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
238
239 /* Objects */
240 struct nouveau_gpuobj *ramin; /* Private instmem */
241 struct drm_mm ramin_heap; /* Private PRAMIN heap */
242 struct nouveau_ramht *ramht; /* Hash table */
243
244 /* GPU object info for stuff used in-kernel (mm_enabled) */
245 uint32_t m2mf_ntfy;
246 uint32_t vram_handle;
247 uint32_t gart_handle;
248 bool accel_done;
249
250 /* Push buffer state (only for drm's channel on !mm_enabled) */
251 struct {
252 int max;
253 int free;
254 int cur;
255 int put;
256 /* access via pushbuf_bo */
257
258 int ib_base;
259 int ib_max;
260 int ib_free;
261 int ib_put;
262 } dma;
263
264 uint32_t sw_subchannel[8];
265
266 struct {
267 struct nouveau_gpuobj *vblsem;
268 uint32_t vblsem_head;
269 uint32_t vblsem_offset;
270 uint32_t vblsem_rval;
271 struct list_head vbl_wait;
272 struct list_head flip;
273 } nvsw;
274
275 struct {
276 bool active;
277 char name[32];
278 struct drm_info_list info;
279 } debugfs;
280 };
281
282 struct nouveau_instmem_engine {
283 void *priv;
284
285 int (*init)(struct drm_device *dev);
286 void (*takedown)(struct drm_device *dev);
287 int (*suspend)(struct drm_device *dev);
288 void (*resume)(struct drm_device *dev);
289
290 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
291 u32 *size, u32 align);
292 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
293 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
294 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
295 void (*flush)(struct drm_device *);
296 };
297
298 struct nouveau_mc_engine {
299 int (*init)(struct drm_device *dev);
300 void (*takedown)(struct drm_device *dev);
301 };
302
303 struct nouveau_timer_engine {
304 int (*init)(struct drm_device *dev);
305 void (*takedown)(struct drm_device *dev);
306 uint64_t (*read)(struct drm_device *dev);
307 };
308
309 struct nouveau_fb_engine {
310 int num_tiles;
311 struct drm_mm tag_heap;
312
313 int (*init)(struct drm_device *dev);
314 void (*takedown)(struct drm_device *dev);
315
316 void (*init_tile_region)(struct drm_device *dev, int i,
317 uint32_t addr, uint32_t size,
318 uint32_t pitch, uint32_t flags);
319 void (*set_tile_region)(struct drm_device *dev, int i);
320 void (*free_tile_region)(struct drm_device *dev, int i);
321 };
322
323 struct nouveau_fifo_engine {
324 int channels;
325
326 struct nouveau_gpuobj *playlist[2];
327 int cur_playlist;
328
329 int (*init)(struct drm_device *);
330 void (*takedown)(struct drm_device *);
331
332 void (*disable)(struct drm_device *);
333 void (*enable)(struct drm_device *);
334 bool (*reassign)(struct drm_device *, bool enable);
335 bool (*cache_pull)(struct drm_device *dev, bool enable);
336
337 int (*channel_id)(struct drm_device *);
338
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
343 void (*tlb_flush)(struct drm_device *dev);
344 };
345
346 struct nouveau_pgraph_engine {
347 bool accel_blocked;
348 bool registered;
349 int grctx_size;
350
351 /* NV2x/NV3x context table (0x400780) */
352 struct nouveau_gpuobj *ctx_table;
353
354 int (*init)(struct drm_device *);
355 void (*takedown)(struct drm_device *);
356
357 void (*fifo_access)(struct drm_device *, bool);
358
359 struct nouveau_channel *(*channel)(struct drm_device *);
360 int (*create_context)(struct nouveau_channel *);
361 void (*destroy_context)(struct nouveau_channel *);
362 int (*load_context)(struct nouveau_channel *);
363 int (*unload_context)(struct drm_device *);
364 void (*tlb_flush)(struct drm_device *dev);
365
366 void (*set_tile_region)(struct drm_device *dev, int i);
367 };
368
369 struct nouveau_display_engine {
370 int (*early_init)(struct drm_device *);
371 void (*late_takedown)(struct drm_device *);
372 int (*create)(struct drm_device *);
373 int (*init)(struct drm_device *);
374 void (*destroy)(struct drm_device *);
375 };
376
377 struct nouveau_gpio_engine {
378 int (*init)(struct drm_device *);
379 void (*takedown)(struct drm_device *);
380
381 int (*get)(struct drm_device *, enum dcb_gpio_tag);
382 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
383
384 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
385 };
386
387 struct nouveau_pm_voltage_level {
388 u8 voltage;
389 u8 vid;
390 };
391
392 struct nouveau_pm_voltage {
393 bool supported;
394 u8 vid_mask;
395
396 struct nouveau_pm_voltage_level *level;
397 int nr_level;
398 };
399
400 #define NOUVEAU_PM_MAX_LEVEL 8
401 struct nouveau_pm_level {
402 struct device_attribute dev_attr;
403 char name[32];
404 int id;
405
406 u32 core;
407 u32 memory;
408 u32 shader;
409 u32 unk05;
410
411 u8 voltage;
412 u8 fanspeed;
413
414 u16 memscript;
415 };
416
417 struct nouveau_pm_temp_sensor_constants {
418 u16 offset_constant;
419 s16 offset_mult;
420 u16 offset_div;
421 u16 slope_mult;
422 u16 slope_div;
423 };
424
425 struct nouveau_pm_threshold_temp {
426 s16 critical;
427 s16 down_clock;
428 s16 fan_boost;
429 };
430
431 struct nouveau_pm_memtiming {
432 u32 reg_100220;
433 u32 reg_100224;
434 u32 reg_100228;
435 u32 reg_10022c;
436 u32 reg_100230;
437 u32 reg_100234;
438 u32 reg_100238;
439 u32 reg_10023c;
440 };
441
442 struct nouveau_pm_memtimings {
443 bool supported;
444 struct nouveau_pm_memtiming *timing;
445 int nr_timing;
446 };
447
448 struct nouveau_pm_engine {
449 struct nouveau_pm_voltage voltage;
450 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
451 int nr_perflvl;
452 struct nouveau_pm_memtimings memtimings;
453 struct nouveau_pm_temp_sensor_constants sensor_constants;
454 struct nouveau_pm_threshold_temp threshold_temp;
455
456 struct nouveau_pm_level boot;
457 struct nouveau_pm_level *cur;
458
459 struct device *hwmon;
460 struct notifier_block acpi_nb;
461
462 int (*clock_get)(struct drm_device *, u32 id);
463 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
464 u32 id, int khz);
465 void (*clock_set)(struct drm_device *, void *);
466 int (*voltage_get)(struct drm_device *);
467 int (*voltage_set)(struct drm_device *, int voltage);
468 int (*fanspeed_get)(struct drm_device *);
469 int (*fanspeed_set)(struct drm_device *, int fanspeed);
470 int (*temp_get)(struct drm_device *);
471 };
472
473 struct nouveau_crypt_engine {
474 bool registered;
475
476 int (*init)(struct drm_device *);
477 void (*takedown)(struct drm_device *);
478 int (*create_context)(struct nouveau_channel *);
479 void (*destroy_context)(struct nouveau_channel *);
480 void (*tlb_flush)(struct drm_device *dev);
481 };
482
483 struct nouveau_engine {
484 struct nouveau_instmem_engine instmem;
485 struct nouveau_mc_engine mc;
486 struct nouveau_timer_engine timer;
487 struct nouveau_fb_engine fb;
488 struct nouveau_pgraph_engine graph;
489 struct nouveau_fifo_engine fifo;
490 struct nouveau_display_engine display;
491 struct nouveau_gpio_engine gpio;
492 struct nouveau_pm_engine pm;
493 struct nouveau_crypt_engine crypt;
494 };
495
496 struct nouveau_pll_vals {
497 union {
498 struct {
499 #ifdef __BIG_ENDIAN
500 uint8_t N1, M1, N2, M2;
501 #else
502 uint8_t M1, N1, M2, N2;
503 #endif
504 };
505 struct {
506 uint16_t NM1, NM2;
507 } __attribute__((packed));
508 };
509 int log2P;
510
511 int refclk;
512 };
513
514 enum nv04_fp_display_regs {
515 FP_DISPLAY_END,
516 FP_TOTAL,
517 FP_CRTC,
518 FP_SYNC_START,
519 FP_SYNC_END,
520 FP_VALID_START,
521 FP_VALID_END
522 };
523
524 struct nv04_crtc_reg {
525 unsigned char MiscOutReg;
526 uint8_t CRTC[0xa0];
527 uint8_t CR58[0x10];
528 uint8_t Sequencer[5];
529 uint8_t Graphics[9];
530 uint8_t Attribute[21];
531 unsigned char DAC[768];
532
533 /* PCRTC regs */
534 uint32_t fb_start;
535 uint32_t crtc_cfg;
536 uint32_t cursor_cfg;
537 uint32_t gpio_ext;
538 uint32_t crtc_830;
539 uint32_t crtc_834;
540 uint32_t crtc_850;
541 uint32_t crtc_eng_ctrl;
542
543 /* PRAMDAC regs */
544 uint32_t nv10_cursync;
545 struct nouveau_pll_vals pllvals;
546 uint32_t ramdac_gen_ctrl;
547 uint32_t ramdac_630;
548 uint32_t ramdac_634;
549 uint32_t tv_setup;
550 uint32_t tv_vtotal;
551 uint32_t tv_vskew;
552 uint32_t tv_vsync_delay;
553 uint32_t tv_htotal;
554 uint32_t tv_hskew;
555 uint32_t tv_hsync_delay;
556 uint32_t tv_hsync_delay2;
557 uint32_t fp_horiz_regs[7];
558 uint32_t fp_vert_regs[7];
559 uint32_t dither;
560 uint32_t fp_control;
561 uint32_t dither_regs[6];
562 uint32_t fp_debug_0;
563 uint32_t fp_debug_1;
564 uint32_t fp_debug_2;
565 uint32_t fp_margin_color;
566 uint32_t ramdac_8c0;
567 uint32_t ramdac_a20;
568 uint32_t ramdac_a24;
569 uint32_t ramdac_a34;
570 uint32_t ctv_regs[38];
571 };
572
573 struct nv04_output_reg {
574 uint32_t output;
575 int head;
576 };
577
578 struct nv04_mode_state {
579 struct nv04_crtc_reg crtc_reg[2];
580 uint32_t pllsel;
581 uint32_t sel_clk;
582 };
583
584 enum nouveau_card_type {
585 NV_04 = 0x00,
586 NV_10 = 0x10,
587 NV_20 = 0x20,
588 NV_30 = 0x30,
589 NV_40 = 0x40,
590 NV_50 = 0x50,
591 NV_C0 = 0xc0,
592 };
593
594 struct drm_nouveau_private {
595 struct drm_device *dev;
596
597 /* the card type, takes NV_* as values */
598 enum nouveau_card_type card_type;
599 /* exact chipset, derived from NV_PMC_BOOT_0 */
600 int chipset;
601 int flags;
602
603 void __iomem *mmio;
604
605 spinlock_t ramin_lock;
606 void __iomem *ramin;
607 u32 ramin_size;
608 u32 ramin_base;
609 bool ramin_available;
610 struct drm_mm ramin_heap;
611 struct list_head gpuobj_list;
612 struct list_head classes;
613
614 struct nouveau_bo *vga_ram;
615
616 /* interrupt handling */
617 void (*irq_handler[32])(struct drm_device *);
618 bool msi_enabled;
619 struct workqueue_struct *wq;
620 struct work_struct irq_work;
621 struct work_struct hpd_work;
622
623 struct {
624 spinlock_t lock;
625 uint32_t hpd0_bits;
626 uint32_t hpd1_bits;
627 } hpd_state;
628
629 struct list_head vbl_waiting;
630
631 struct {
632 struct drm_global_reference mem_global_ref;
633 struct ttm_bo_global_ref bo_global_ref;
634 struct ttm_bo_device bdev;
635 atomic_t validate_sequence;
636 } ttm;
637
638 struct {
639 spinlock_t lock;
640 struct drm_mm heap;
641 struct nouveau_bo *bo;
642 } fence;
643
644 struct {
645 spinlock_t lock;
646 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
647 } channels;
648
649 struct nouveau_engine engine;
650 struct nouveau_channel *channel;
651
652 /* For PFIFO and PGRAPH. */
653 spinlock_t context_switch_lock;
654
655 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
656 struct nouveau_ramht *ramht;
657 struct nouveau_gpuobj *ramfc;
658 struct nouveau_gpuobj *ramro;
659
660 uint32_t ramin_rsvd_vram;
661
662 struct {
663 enum {
664 NOUVEAU_GART_NONE = 0,
665 NOUVEAU_GART_AGP,
666 NOUVEAU_GART_SGDMA
667 } type;
668 uint64_t aper_base;
669 uint64_t aper_size;
670 uint64_t aper_free;
671
672 struct nouveau_gpuobj *sg_ctxdma;
673 struct page *sg_dummy_page;
674 dma_addr_t sg_dummy_bus;
675 } gart_info;
676
677 /* nv10-nv40 tiling regions */
678 struct {
679 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
680 spinlock_t lock;
681 } tile;
682
683 /* VRAM/fb configuration */
684 uint64_t vram_size;
685 uint64_t vram_sys_base;
686 u32 vram_rblock_size;
687
688 uint64_t fb_phys;
689 uint64_t fb_available_size;
690 uint64_t fb_mappable_pages;
691 uint64_t fb_aper_free;
692 int fb_mtrr;
693
694 /* G8x/G9x virtual address space */
695 uint64_t vm_gart_base;
696 uint64_t vm_gart_size;
697 uint64_t vm_vram_base;
698 uint64_t vm_vram_size;
699 uint64_t vm_end;
700 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
701 int vm_vram_pt_nr;
702
703 struct nvbios vbios;
704
705 struct nv04_mode_state mode_reg;
706 struct nv04_mode_state saved_reg;
707 uint32_t saved_vga_font[4][16384];
708 uint32_t crtc_owner;
709 uint32_t dac_users[4];
710
711 struct nouveau_suspend_resume {
712 uint32_t *ramin_copy;
713 } susres;
714
715 struct backlight_device *backlight;
716
717 struct nouveau_channel *evo;
718 u32 evo_alloc;
719 struct {
720 struct dcb_entry *dcb;
721 u16 script;
722 u32 pclk;
723 } evo_irq;
724
725 struct {
726 struct dentry *channel_root;
727 } debugfs;
728
729 struct nouveau_fbdev *nfbdev;
730 struct apertures_struct *apertures;
731 };
732
733 static inline struct drm_nouveau_private *
734 nouveau_private(struct drm_device *dev)
735 {
736 return dev->dev_private;
737 }
738
739 static inline struct drm_nouveau_private *
740 nouveau_bdev(struct ttm_bo_device *bd)
741 {
742 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
743 }
744
745 static inline int
746 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
747 {
748 struct nouveau_bo *prev;
749
750 if (!pnvbo)
751 return -EINVAL;
752 prev = *pnvbo;
753
754 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
755 if (prev) {
756 struct ttm_buffer_object *bo = &prev->bo;
757
758 ttm_bo_unref(&bo);
759 }
760
761 return 0;
762 }
763
764 /* nouveau_drv.c */
765 extern int nouveau_agpmode;
766 extern int nouveau_duallink;
767 extern int nouveau_uscript_lvds;
768 extern int nouveau_uscript_tmds;
769 extern int nouveau_vram_pushbuf;
770 extern int nouveau_vram_notify;
771 extern int nouveau_fbpercrtc;
772 extern int nouveau_tv_disable;
773 extern char *nouveau_tv_norm;
774 extern int nouveau_reg_debug;
775 extern char *nouveau_vbios;
776 extern int nouveau_ignorelid;
777 extern int nouveau_nofbaccel;
778 extern int nouveau_noaccel;
779 extern int nouveau_force_post;
780 extern int nouveau_override_conntype;
781 extern char *nouveau_perflvl;
782 extern int nouveau_perflvl_wr;
783 extern int nouveau_msi;
784
785 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
786 extern int nouveau_pci_resume(struct pci_dev *pdev);
787
788 /* nouveau_state.c */
789 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
790 extern int nouveau_load(struct drm_device *, unsigned long flags);
791 extern int nouveau_firstopen(struct drm_device *);
792 extern void nouveau_lastclose(struct drm_device *);
793 extern int nouveau_unload(struct drm_device *);
794 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
795 struct drm_file *);
796 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
797 struct drm_file *);
798 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
799 uint32_t reg, uint32_t mask, uint32_t val);
800 extern bool nouveau_wait_for_idle(struct drm_device *);
801 extern int nouveau_card_init(struct drm_device *);
802
803 /* nouveau_mem.c */
804 extern int nouveau_mem_vram_init(struct drm_device *);
805 extern void nouveau_mem_vram_fini(struct drm_device *);
806 extern int nouveau_mem_gart_init(struct drm_device *);
807 extern void nouveau_mem_gart_fini(struct drm_device *);
808 extern int nouveau_mem_init_agp(struct drm_device *);
809 extern int nouveau_mem_reset_agp(struct drm_device *);
810 extern void nouveau_mem_close(struct drm_device *);
811 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
812 struct drm_device *dev, uint32_t addr, uint32_t size,
813 uint32_t pitch, uint32_t flags);
814 extern void nv10_mem_put_tile_region(struct drm_device *dev,
815 struct nouveau_tile_reg *tile,
816 struct nouveau_fence *fence);
817 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
818 uint32_t size, uint32_t flags,
819 uint64_t phys);
820 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
821 uint32_t size);
822
823 /* nouveau_notifier.c */
824 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
825 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
826 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
827 int cout, uint32_t *offset);
828 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
829 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
830 struct drm_file *);
831 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
832 struct drm_file *);
833
834 /* nouveau_channel.c */
835 extern struct drm_ioctl_desc nouveau_ioctls[];
836 extern int nouveau_max_ioctl;
837 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
838 extern int nouveau_channel_alloc(struct drm_device *dev,
839 struct nouveau_channel **chan,
840 struct drm_file *file_priv,
841 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
842 extern struct nouveau_channel *
843 nouveau_channel_get_unlocked(struct nouveau_channel *);
844 extern struct nouveau_channel *
845 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
846 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
847 extern void nouveau_channel_put(struct nouveau_channel **);
848 extern void nouveau_channel_ref(struct nouveau_channel *chan,
849 struct nouveau_channel **pchan);
850
851 /* nouveau_object.c */
852 #define NVOBJ_CLASS(d,c,e) do { \
853 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
854 if (ret) \
855 return ret; \
856 } while(0)
857
858 #define NVOBJ_MTHD(d,c,m,e) do { \
859 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
860 if (ret) \
861 return ret; \
862 } while(0)
863
864 extern int nouveau_gpuobj_early_init(struct drm_device *);
865 extern int nouveau_gpuobj_init(struct drm_device *);
866 extern void nouveau_gpuobj_takedown(struct drm_device *);
867 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
868 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
869 extern void nouveau_gpuobj_resume(struct drm_device *dev);
870 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
871 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
872 int (*exec)(struct nouveau_channel *,
873 u32 class, u32 mthd, u32 data));
874 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
875 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
876 uint32_t vram_h, uint32_t tt_h);
877 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
878 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
879 uint32_t size, int align, uint32_t flags,
880 struct nouveau_gpuobj **);
881 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
882 struct nouveau_gpuobj **);
883 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
884 u32 size, u32 flags,
885 struct nouveau_gpuobj **);
886 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
887 uint64_t offset, uint64_t size, int access,
888 int target, struct nouveau_gpuobj **);
889 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
890 uint64_t offset, uint64_t size,
891 int access, struct nouveau_gpuobj **,
892 uint32_t *o_ret);
893 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
894 struct nouveau_gpuobj **);
895 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
896 struct drm_file *);
897 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
898 struct drm_file *);
899
900 /* nouveau_irq.c */
901 extern int nouveau_irq_init(struct drm_device *);
902 extern void nouveau_irq_fini(struct drm_device *);
903 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
904 extern void nouveau_irq_register(struct drm_device *, int status_bit,
905 void (*)(struct drm_device *));
906 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
907 extern void nouveau_irq_preinstall(struct drm_device *);
908 extern int nouveau_irq_postinstall(struct drm_device *);
909 extern void nouveau_irq_uninstall(struct drm_device *);
910
911 /* nouveau_sgdma.c */
912 extern int nouveau_sgdma_init(struct drm_device *);
913 extern void nouveau_sgdma_takedown(struct drm_device *);
914 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
915 uint32_t *page);
916 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
917
918 /* nouveau_debugfs.c */
919 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
920 extern int nouveau_debugfs_init(struct drm_minor *);
921 extern void nouveau_debugfs_takedown(struct drm_minor *);
922 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
923 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
924 #else
925 static inline int
926 nouveau_debugfs_init(struct drm_minor *minor)
927 {
928 return 0;
929 }
930
931 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
932 {
933 }
934
935 static inline int
936 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
937 {
938 return 0;
939 }
940
941 static inline void
942 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
943 {
944 }
945 #endif
946
947 /* nouveau_dma.c */
948 extern void nouveau_dma_pre_init(struct nouveau_channel *);
949 extern int nouveau_dma_init(struct nouveau_channel *);
950 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
951
952 /* nouveau_acpi.c */
953 #define ROM_BIOS_PAGE 4096
954 #if defined(CONFIG_ACPI)
955 void nouveau_register_dsm_handler(void);
956 void nouveau_unregister_dsm_handler(void);
957 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
958 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
959 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
960 #else
961 static inline void nouveau_register_dsm_handler(void) {}
962 static inline void nouveau_unregister_dsm_handler(void) {}
963 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
964 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
965 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
966 #endif
967
968 /* nouveau_backlight.c */
969 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
970 extern int nouveau_backlight_init(struct drm_device *);
971 extern void nouveau_backlight_exit(struct drm_device *);
972 #else
973 static inline int nouveau_backlight_init(struct drm_device *dev)
974 {
975 return 0;
976 }
977
978 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
979 #endif
980
981 /* nouveau_bios.c */
982 extern int nouveau_bios_init(struct drm_device *);
983 extern void nouveau_bios_takedown(struct drm_device *dev);
984 extern int nouveau_run_vbios_init(struct drm_device *);
985 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
986 struct dcb_entry *);
987 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
988 enum dcb_gpio_tag);
989 extern struct dcb_connector_table_entry *
990 nouveau_bios_connector_entry(struct drm_device *, int index);
991 extern u32 get_pll_register(struct drm_device *, enum pll_types);
992 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
993 struct pll_lims *);
994 extern int nouveau_bios_run_display_table(struct drm_device *,
995 struct dcb_entry *,
996 uint32_t script, int pxclk);
997 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
998 int *length);
999 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1000 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1001 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1002 bool *dl, bool *if_is_24bit);
1003 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1004 int head, int pxclk);
1005 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1006 enum LVDS_script, int pxclk);
1007
1008 /* nouveau_ttm.c */
1009 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1010 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1011 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1012
1013 /* nouveau_dp.c */
1014 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1015 uint8_t *data, int data_nr);
1016 bool nouveau_dp_detect(struct drm_encoder *);
1017 bool nouveau_dp_link_train(struct drm_encoder *);
1018
1019 /* nv04_fb.c */
1020 extern int nv04_fb_init(struct drm_device *);
1021 extern void nv04_fb_takedown(struct drm_device *);
1022
1023 /* nv10_fb.c */
1024 extern int nv10_fb_init(struct drm_device *);
1025 extern void nv10_fb_takedown(struct drm_device *);
1026 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1027 uint32_t addr, uint32_t size,
1028 uint32_t pitch, uint32_t flags);
1029 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1030 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1031
1032 /* nv30_fb.c */
1033 extern int nv30_fb_init(struct drm_device *);
1034 extern void nv30_fb_takedown(struct drm_device *);
1035 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1036 uint32_t addr, uint32_t size,
1037 uint32_t pitch, uint32_t flags);
1038 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1039
1040 /* nv40_fb.c */
1041 extern int nv40_fb_init(struct drm_device *);
1042 extern void nv40_fb_takedown(struct drm_device *);
1043 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1044
1045 /* nv50_fb.c */
1046 extern int nv50_fb_init(struct drm_device *);
1047 extern void nv50_fb_takedown(struct drm_device *);
1048 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
1049
1050 /* nvc0_fb.c */
1051 extern int nvc0_fb_init(struct drm_device *);
1052 extern void nvc0_fb_takedown(struct drm_device *);
1053
1054 /* nv04_fifo.c */
1055 extern int nv04_fifo_init(struct drm_device *);
1056 extern void nv04_fifo_disable(struct drm_device *);
1057 extern void nv04_fifo_enable(struct drm_device *);
1058 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1059 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1060 extern int nv04_fifo_channel_id(struct drm_device *);
1061 extern int nv04_fifo_create_context(struct nouveau_channel *);
1062 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1063 extern int nv04_fifo_load_context(struct nouveau_channel *);
1064 extern int nv04_fifo_unload_context(struct drm_device *);
1065
1066 /* nv10_fifo.c */
1067 extern int nv10_fifo_init(struct drm_device *);
1068 extern int nv10_fifo_channel_id(struct drm_device *);
1069 extern int nv10_fifo_create_context(struct nouveau_channel *);
1070 extern int nv10_fifo_load_context(struct nouveau_channel *);
1071 extern int nv10_fifo_unload_context(struct drm_device *);
1072
1073 /* nv40_fifo.c */
1074 extern int nv40_fifo_init(struct drm_device *);
1075 extern int nv40_fifo_create_context(struct nouveau_channel *);
1076 extern int nv40_fifo_load_context(struct nouveau_channel *);
1077 extern int nv40_fifo_unload_context(struct drm_device *);
1078
1079 /* nv50_fifo.c */
1080 extern int nv50_fifo_init(struct drm_device *);
1081 extern void nv50_fifo_takedown(struct drm_device *);
1082 extern int nv50_fifo_channel_id(struct drm_device *);
1083 extern int nv50_fifo_create_context(struct nouveau_channel *);
1084 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1085 extern int nv50_fifo_load_context(struct nouveau_channel *);
1086 extern int nv50_fifo_unload_context(struct drm_device *);
1087 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1088
1089 /* nvc0_fifo.c */
1090 extern int nvc0_fifo_init(struct drm_device *);
1091 extern void nvc0_fifo_takedown(struct drm_device *);
1092 extern void nvc0_fifo_disable(struct drm_device *);
1093 extern void nvc0_fifo_enable(struct drm_device *);
1094 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1095 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1096 extern int nvc0_fifo_channel_id(struct drm_device *);
1097 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1098 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1099 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1100 extern int nvc0_fifo_unload_context(struct drm_device *);
1101
1102 /* nv04_graph.c */
1103 extern int nv04_graph_init(struct drm_device *);
1104 extern void nv04_graph_takedown(struct drm_device *);
1105 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1106 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1107 extern int nv04_graph_create_context(struct nouveau_channel *);
1108 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1109 extern int nv04_graph_load_context(struct nouveau_channel *);
1110 extern int nv04_graph_unload_context(struct drm_device *);
1111 extern void nv04_graph_context_switch(struct drm_device *);
1112 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1113 u32 class, u32 mthd, u32 data);
1114
1115 /* nv10_graph.c */
1116 extern int nv10_graph_init(struct drm_device *);
1117 extern void nv10_graph_takedown(struct drm_device *);
1118 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1119 extern int nv10_graph_create_context(struct nouveau_channel *);
1120 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1121 extern int nv10_graph_load_context(struct nouveau_channel *);
1122 extern int nv10_graph_unload_context(struct drm_device *);
1123 extern void nv10_graph_context_switch(struct drm_device *);
1124 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1125
1126 /* nv20_graph.c */
1127 extern int nv20_graph_create_context(struct nouveau_channel *);
1128 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1129 extern int nv20_graph_load_context(struct nouveau_channel *);
1130 extern int nv20_graph_unload_context(struct drm_device *);
1131 extern int nv20_graph_init(struct drm_device *);
1132 extern void nv20_graph_takedown(struct drm_device *);
1133 extern int nv30_graph_init(struct drm_device *);
1134 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
1135
1136 /* nv40_graph.c */
1137 extern int nv40_graph_init(struct drm_device *);
1138 extern void nv40_graph_takedown(struct drm_device *);
1139 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1140 extern int nv40_graph_create_context(struct nouveau_channel *);
1141 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1142 extern int nv40_graph_load_context(struct nouveau_channel *);
1143 extern int nv40_graph_unload_context(struct drm_device *);
1144 extern void nv40_grctx_init(struct nouveau_grctx *);
1145 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
1146
1147 /* nv50_graph.c */
1148 extern int nv50_graph_init(struct drm_device *);
1149 extern void nv50_graph_takedown(struct drm_device *);
1150 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1151 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1152 extern int nv50_graph_create_context(struct nouveau_channel *);
1153 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1154 extern int nv50_graph_load_context(struct nouveau_channel *);
1155 extern int nv50_graph_unload_context(struct drm_device *);
1156 extern void nv50_graph_context_switch(struct drm_device *);
1157 extern int nv50_grctx_init(struct nouveau_grctx *);
1158 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1159 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1160
1161 /* nvc0_graph.c */
1162 extern int nvc0_graph_init(struct drm_device *);
1163 extern void nvc0_graph_takedown(struct drm_device *);
1164 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1165 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1166 extern int nvc0_graph_create_context(struct nouveau_channel *);
1167 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1168 extern int nvc0_graph_load_context(struct nouveau_channel *);
1169 extern int nvc0_graph_unload_context(struct drm_device *);
1170
1171 /* nv84_crypt.c */
1172 extern int nv84_crypt_init(struct drm_device *dev);
1173 extern void nv84_crypt_fini(struct drm_device *dev);
1174 extern int nv84_crypt_create_context(struct nouveau_channel *);
1175 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1176 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1177
1178 /* nv04_instmem.c */
1179 extern int nv04_instmem_init(struct drm_device *);
1180 extern void nv04_instmem_takedown(struct drm_device *);
1181 extern int nv04_instmem_suspend(struct drm_device *);
1182 extern void nv04_instmem_resume(struct drm_device *);
1183 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1184 u32 *size, u32 align);
1185 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1186 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1187 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1188 extern void nv04_instmem_flush(struct drm_device *);
1189
1190 /* nv50_instmem.c */
1191 extern int nv50_instmem_init(struct drm_device *);
1192 extern void nv50_instmem_takedown(struct drm_device *);
1193 extern int nv50_instmem_suspend(struct drm_device *);
1194 extern void nv50_instmem_resume(struct drm_device *);
1195 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1196 u32 *size, u32 align);
1197 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1198 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1199 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1200 extern void nv50_instmem_flush(struct drm_device *);
1201 extern void nv84_instmem_flush(struct drm_device *);
1202 extern void nv50_vm_flush(struct drm_device *, int engine);
1203
1204 /* nvc0_instmem.c */
1205 extern int nvc0_instmem_init(struct drm_device *);
1206 extern void nvc0_instmem_takedown(struct drm_device *);
1207 extern int nvc0_instmem_suspend(struct drm_device *);
1208 extern void nvc0_instmem_resume(struct drm_device *);
1209 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1210 u32 *size, u32 align);
1211 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1212 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1213 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1214 extern void nvc0_instmem_flush(struct drm_device *);
1215
1216 /* nv04_mc.c */
1217 extern int nv04_mc_init(struct drm_device *);
1218 extern void nv04_mc_takedown(struct drm_device *);
1219
1220 /* nv40_mc.c */
1221 extern int nv40_mc_init(struct drm_device *);
1222 extern void nv40_mc_takedown(struct drm_device *);
1223
1224 /* nv50_mc.c */
1225 extern int nv50_mc_init(struct drm_device *);
1226 extern void nv50_mc_takedown(struct drm_device *);
1227
1228 /* nv04_timer.c */
1229 extern int nv04_timer_init(struct drm_device *);
1230 extern uint64_t nv04_timer_read(struct drm_device *);
1231 extern void nv04_timer_takedown(struct drm_device *);
1232
1233 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1234 unsigned long arg);
1235
1236 /* nv04_dac.c */
1237 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1238 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1239 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1240 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1241 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1242
1243 /* nv04_dfp.c */
1244 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1245 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1246 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1247 int head, bool dl);
1248 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1249 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1250
1251 /* nv04_tv.c */
1252 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1253 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1254
1255 /* nv17_tv.c */
1256 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1257
1258 /* nv04_display.c */
1259 extern int nv04_display_early_init(struct drm_device *);
1260 extern void nv04_display_late_takedown(struct drm_device *);
1261 extern int nv04_display_create(struct drm_device *);
1262 extern int nv04_display_init(struct drm_device *);
1263 extern void nv04_display_destroy(struct drm_device *);
1264
1265 /* nv04_crtc.c */
1266 extern int nv04_crtc_create(struct drm_device *, int index);
1267
1268 /* nouveau_bo.c */
1269 extern struct ttm_bo_driver nouveau_bo_driver;
1270 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1271 int size, int align, uint32_t flags,
1272 uint32_t tile_mode, uint32_t tile_flags,
1273 bool no_vm, bool mappable, struct nouveau_bo **);
1274 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1275 extern int nouveau_bo_unpin(struct nouveau_bo *);
1276 extern int nouveau_bo_map(struct nouveau_bo *);
1277 extern void nouveau_bo_unmap(struct nouveau_bo *);
1278 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1279 uint32_t busy);
1280 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1281 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1282 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1283 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1284 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1285
1286 /* nouveau_fence.c */
1287 struct nouveau_fence;
1288 extern int nouveau_fence_init(struct drm_device *);
1289 extern void nouveau_fence_fini(struct drm_device *);
1290 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1291 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1292 extern void nouveau_fence_update(struct nouveau_channel *);
1293 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1294 bool emit);
1295 extern int nouveau_fence_emit(struct nouveau_fence *);
1296 extern void nouveau_fence_work(struct nouveau_fence *fence,
1297 void (*work)(void *priv, bool signalled),
1298 void *priv);
1299 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1300
1301 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1302 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1303 extern int __nouveau_fence_flush(void *obj, void *arg);
1304 extern void __nouveau_fence_unref(void **obj);
1305 extern void *__nouveau_fence_ref(void *obj);
1306
1307 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1308 {
1309 return __nouveau_fence_signalled(obj, NULL);
1310 }
1311 static inline int
1312 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1313 {
1314 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1315 }
1316 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1317 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1318 {
1319 return __nouveau_fence_flush(obj, NULL);
1320 }
1321 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1322 {
1323 __nouveau_fence_unref((void **)obj);
1324 }
1325 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1326 {
1327 return __nouveau_fence_ref(obj);
1328 }
1329
1330 /* nouveau_gem.c */
1331 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1332 int size, int align, uint32_t flags,
1333 uint32_t tile_mode, uint32_t tile_flags,
1334 bool no_vm, bool mappable, struct nouveau_bo **);
1335 extern int nouveau_gem_object_new(struct drm_gem_object *);
1336 extern void nouveau_gem_object_del(struct drm_gem_object *);
1337 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1338 struct drm_file *);
1339 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1340 struct drm_file *);
1341 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1342 struct drm_file *);
1343 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1344 struct drm_file *);
1345 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1346 struct drm_file *);
1347
1348 /* nouveau_display.c */
1349 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1350 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1351 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1352 struct drm_pending_vblank_event *event);
1353 int nouveau_finish_page_flip(struct nouveau_channel *,
1354 struct nouveau_page_flip_state *);
1355
1356 /* nv10_gpio.c */
1357 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1358 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1359
1360 /* nv50_gpio.c */
1361 int nv50_gpio_init(struct drm_device *dev);
1362 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1363 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1364 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1365
1366 /* nv50_calc. */
1367 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1368 int *N1, int *M1, int *N2, int *M2, int *P);
1369 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1370 int clk, int *N, int *fN, int *M, int *P);
1371
1372 #ifndef ioread32_native
1373 #ifdef __BIG_ENDIAN
1374 #define ioread16_native ioread16be
1375 #define iowrite16_native iowrite16be
1376 #define ioread32_native ioread32be
1377 #define iowrite32_native iowrite32be
1378 #else /* def __BIG_ENDIAN */
1379 #define ioread16_native ioread16
1380 #define iowrite16_native iowrite16
1381 #define ioread32_native ioread32
1382 #define iowrite32_native iowrite32
1383 #endif /* def __BIG_ENDIAN else */
1384 #endif /* !ioread32_native */
1385
1386 /* channel control reg access */
1387 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1388 {
1389 return ioread32_native(chan->user + reg);
1390 }
1391
1392 static inline void nvchan_wr32(struct nouveau_channel *chan,
1393 unsigned reg, u32 val)
1394 {
1395 iowrite32_native(val, chan->user + reg);
1396 }
1397
1398 /* register access */
1399 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1400 {
1401 struct drm_nouveau_private *dev_priv = dev->dev_private;
1402 return ioread32_native(dev_priv->mmio + reg);
1403 }
1404
1405 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1406 {
1407 struct drm_nouveau_private *dev_priv = dev->dev_private;
1408 iowrite32_native(val, dev_priv->mmio + reg);
1409 }
1410
1411 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1412 {
1413 u32 tmp = nv_rd32(dev, reg);
1414 nv_wr32(dev, reg, (tmp & ~mask) | val);
1415 return tmp;
1416 }
1417
1418 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1419 {
1420 struct drm_nouveau_private *dev_priv = dev->dev_private;
1421 return ioread8(dev_priv->mmio + reg);
1422 }
1423
1424 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1425 {
1426 struct drm_nouveau_private *dev_priv = dev->dev_private;
1427 iowrite8(val, dev_priv->mmio + reg);
1428 }
1429
1430 #define nv_wait(dev, reg, mask, val) \
1431 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1432
1433 /* PRAMIN access */
1434 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1435 {
1436 struct drm_nouveau_private *dev_priv = dev->dev_private;
1437 return ioread32_native(dev_priv->ramin + offset);
1438 }
1439
1440 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1441 {
1442 struct drm_nouveau_private *dev_priv = dev->dev_private;
1443 iowrite32_native(val, dev_priv->ramin + offset);
1444 }
1445
1446 /* object access */
1447 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1448 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1449
1450 /*
1451 * Logging
1452 * Argument d is (struct drm_device *).
1453 */
1454 #define NV_PRINTK(level, d, fmt, arg...) \
1455 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1456 pci_name(d->pdev), ##arg)
1457 #ifndef NV_DEBUG_NOTRACE
1458 #define NV_DEBUG(d, fmt, arg...) do { \
1459 if (drm_debug & DRM_UT_DRIVER) { \
1460 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1461 __LINE__, ##arg); \
1462 } \
1463 } while (0)
1464 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1465 if (drm_debug & DRM_UT_KMS) { \
1466 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1467 __LINE__, ##arg); \
1468 } \
1469 } while (0)
1470 #else
1471 #define NV_DEBUG(d, fmt, arg...) do { \
1472 if (drm_debug & DRM_UT_DRIVER) \
1473 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1474 } while (0)
1475 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1476 if (drm_debug & DRM_UT_KMS) \
1477 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1478 } while (0)
1479 #endif
1480 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1481 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1482 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1483 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1484 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1485
1486 /* nouveau_reg_debug bitmask */
1487 enum {
1488 NOUVEAU_REG_DEBUG_MC = 0x1,
1489 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1490 NOUVEAU_REG_DEBUG_FB = 0x4,
1491 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1492 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1493 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1494 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1495 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1496 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1497 NOUVEAU_REG_DEBUG_EVO = 0x200,
1498 };
1499
1500 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1501 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1502 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1503 } while (0)
1504
1505 static inline bool
1506 nv_two_heads(struct drm_device *dev)
1507 {
1508 struct drm_nouveau_private *dev_priv = dev->dev_private;
1509 const int impl = dev->pci_device & 0x0ff0;
1510
1511 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1512 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1513 return true;
1514
1515 return false;
1516 }
1517
1518 static inline bool
1519 nv_gf4_disp_arch(struct drm_device *dev)
1520 {
1521 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1522 }
1523
1524 static inline bool
1525 nv_two_reg_pll(struct drm_device *dev)
1526 {
1527 struct drm_nouveau_private *dev_priv = dev->dev_private;
1528 const int impl = dev->pci_device & 0x0ff0;
1529
1530 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1531 return true;
1532 return false;
1533 }
1534
1535 static inline bool
1536 nv_match_device(struct drm_device *dev, unsigned device,
1537 unsigned sub_vendor, unsigned sub_device)
1538 {
1539 return dev->pdev->device == device &&
1540 dev->pdev->subsystem_vendor == sub_vendor &&
1541 dev->pdev->subsystem_device == sub_device;
1542 }
1543
1544 #define NV_SW 0x0000506e
1545 #define NV_SW_DMA_SEMAPHORE 0x00000060
1546 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1547 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1548 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1549 #define NV_SW_YIELD 0x00000080
1550 #define NV_SW_DMA_VBLSEM 0x0000018c
1551 #define NV_SW_VBLSEM_OFFSET 0x00000400
1552 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1553 #define NV_SW_VBLSEM_RELEASE 0x00000408
1554 #define NV_SW_PAGE_FLIP 0x00000500
1555
1556 #endif /* __NOUVEAU_DRV_H__ */
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