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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / nouveau_state.c
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
41
42 static void nouveau_stub_takedown(struct drm_device *dev) {}
43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
44
45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.populate = nv04_instmem_populate;
57 engine->instmem.clear = nv04_instmem_clear;
58 engine->instmem.bind = nv04_instmem_bind;
59 engine->instmem.unbind = nv04_instmem_unbind;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->graph.grclass = nv04_graph_grclass;
69 engine->graph.init = nv04_graph_init;
70 engine->graph.takedown = nv04_graph_takedown;
71 engine->graph.fifo_access = nv04_graph_fifo_access;
72 engine->graph.channel = nv04_graph_channel;
73 engine->graph.create_context = nv04_graph_create_context;
74 engine->graph.destroy_context = nv04_graph_destroy_context;
75 engine->graph.load_context = nv04_graph_load_context;
76 engine->graph.unload_context = nv04_graph_unload_context;
77 engine->fifo.channels = 16;
78 engine->fifo.init = nv04_fifo_init;
79 engine->fifo.takedown = nouveau_stub_takedown;
80 engine->fifo.disable = nv04_fifo_disable;
81 engine->fifo.enable = nv04_fifo_enable;
82 engine->fifo.reassign = nv04_fifo_reassign;
83 engine->fifo.cache_pull = nv04_fifo_cache_pull;
84 engine->fifo.channel_id = nv04_fifo_channel_id;
85 engine->fifo.create_context = nv04_fifo_create_context;
86 engine->fifo.destroy_context = nv04_fifo_destroy_context;
87 engine->fifo.load_context = nv04_fifo_load_context;
88 engine->fifo.unload_context = nv04_fifo_unload_context;
89 engine->display.early_init = nv04_display_early_init;
90 engine->display.late_takedown = nv04_display_late_takedown;
91 engine->display.create = nv04_display_create;
92 engine->display.init = nv04_display_init;
93 engine->display.destroy = nv04_display_destroy;
94 engine->gpio.init = nouveau_stub_init;
95 engine->gpio.takedown = nouveau_stub_takedown;
96 engine->gpio.get = NULL;
97 engine->gpio.set = NULL;
98 engine->gpio.irq_enable = NULL;
99 engine->pm.clock_get = nv04_pm_clock_get;
100 engine->pm.clock_pre = nv04_pm_clock_pre;
101 engine->pm.clock_set = nv04_pm_clock_set;
102 break;
103 case 0x10:
104 engine->instmem.init = nv04_instmem_init;
105 engine->instmem.takedown = nv04_instmem_takedown;
106 engine->instmem.suspend = nv04_instmem_suspend;
107 engine->instmem.resume = nv04_instmem_resume;
108 engine->instmem.populate = nv04_instmem_populate;
109 engine->instmem.clear = nv04_instmem_clear;
110 engine->instmem.bind = nv04_instmem_bind;
111 engine->instmem.unbind = nv04_instmem_unbind;
112 engine->instmem.flush = nv04_instmem_flush;
113 engine->mc.init = nv04_mc_init;
114 engine->mc.takedown = nv04_mc_takedown;
115 engine->timer.init = nv04_timer_init;
116 engine->timer.read = nv04_timer_read;
117 engine->timer.takedown = nv04_timer_takedown;
118 engine->fb.init = nv10_fb_init;
119 engine->fb.takedown = nv10_fb_takedown;
120 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
121 engine->graph.grclass = nv10_graph_grclass;
122 engine->graph.init = nv10_graph_init;
123 engine->graph.takedown = nv10_graph_takedown;
124 engine->graph.channel = nv10_graph_channel;
125 engine->graph.create_context = nv10_graph_create_context;
126 engine->graph.destroy_context = nv10_graph_destroy_context;
127 engine->graph.fifo_access = nv04_graph_fifo_access;
128 engine->graph.load_context = nv10_graph_load_context;
129 engine->graph.unload_context = nv10_graph_unload_context;
130 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
131 engine->fifo.channels = 32;
132 engine->fifo.init = nv10_fifo_init;
133 engine->fifo.takedown = nouveau_stub_takedown;
134 engine->fifo.disable = nv04_fifo_disable;
135 engine->fifo.enable = nv04_fifo_enable;
136 engine->fifo.reassign = nv04_fifo_reassign;
137 engine->fifo.cache_pull = nv04_fifo_cache_pull;
138 engine->fifo.channel_id = nv10_fifo_channel_id;
139 engine->fifo.create_context = nv10_fifo_create_context;
140 engine->fifo.destroy_context = nv10_fifo_destroy_context;
141 engine->fifo.load_context = nv10_fifo_load_context;
142 engine->fifo.unload_context = nv10_fifo_unload_context;
143 engine->display.early_init = nv04_display_early_init;
144 engine->display.late_takedown = nv04_display_late_takedown;
145 engine->display.create = nv04_display_create;
146 engine->display.init = nv04_display_init;
147 engine->display.destroy = nv04_display_destroy;
148 engine->gpio.init = nouveau_stub_init;
149 engine->gpio.takedown = nouveau_stub_takedown;
150 engine->gpio.get = nv10_gpio_get;
151 engine->gpio.set = nv10_gpio_set;
152 engine->gpio.irq_enable = NULL;
153 engine->pm.clock_get = nv04_pm_clock_get;
154 engine->pm.clock_pre = nv04_pm_clock_pre;
155 engine->pm.clock_set = nv04_pm_clock_set;
156 break;
157 case 0x20:
158 engine->instmem.init = nv04_instmem_init;
159 engine->instmem.takedown = nv04_instmem_takedown;
160 engine->instmem.suspend = nv04_instmem_suspend;
161 engine->instmem.resume = nv04_instmem_resume;
162 engine->instmem.populate = nv04_instmem_populate;
163 engine->instmem.clear = nv04_instmem_clear;
164 engine->instmem.bind = nv04_instmem_bind;
165 engine->instmem.unbind = nv04_instmem_unbind;
166 engine->instmem.flush = nv04_instmem_flush;
167 engine->mc.init = nv04_mc_init;
168 engine->mc.takedown = nv04_mc_takedown;
169 engine->timer.init = nv04_timer_init;
170 engine->timer.read = nv04_timer_read;
171 engine->timer.takedown = nv04_timer_takedown;
172 engine->fb.init = nv10_fb_init;
173 engine->fb.takedown = nv10_fb_takedown;
174 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
175 engine->graph.grclass = nv20_graph_grclass;
176 engine->graph.init = nv20_graph_init;
177 engine->graph.takedown = nv20_graph_takedown;
178 engine->graph.channel = nv10_graph_channel;
179 engine->graph.create_context = nv20_graph_create_context;
180 engine->graph.destroy_context = nv20_graph_destroy_context;
181 engine->graph.fifo_access = nv04_graph_fifo_access;
182 engine->graph.load_context = nv20_graph_load_context;
183 engine->graph.unload_context = nv20_graph_unload_context;
184 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
185 engine->fifo.channels = 32;
186 engine->fifo.init = nv10_fifo_init;
187 engine->fifo.takedown = nouveau_stub_takedown;
188 engine->fifo.disable = nv04_fifo_disable;
189 engine->fifo.enable = nv04_fifo_enable;
190 engine->fifo.reassign = nv04_fifo_reassign;
191 engine->fifo.cache_pull = nv04_fifo_cache_pull;
192 engine->fifo.channel_id = nv10_fifo_channel_id;
193 engine->fifo.create_context = nv10_fifo_create_context;
194 engine->fifo.destroy_context = nv10_fifo_destroy_context;
195 engine->fifo.load_context = nv10_fifo_load_context;
196 engine->fifo.unload_context = nv10_fifo_unload_context;
197 engine->display.early_init = nv04_display_early_init;
198 engine->display.late_takedown = nv04_display_late_takedown;
199 engine->display.create = nv04_display_create;
200 engine->display.init = nv04_display_init;
201 engine->display.destroy = nv04_display_destroy;
202 engine->gpio.init = nouveau_stub_init;
203 engine->gpio.takedown = nouveau_stub_takedown;
204 engine->gpio.get = nv10_gpio_get;
205 engine->gpio.set = nv10_gpio_set;
206 engine->gpio.irq_enable = NULL;
207 engine->pm.clock_get = nv04_pm_clock_get;
208 engine->pm.clock_pre = nv04_pm_clock_pre;
209 engine->pm.clock_set = nv04_pm_clock_set;
210 break;
211 case 0x30:
212 engine->instmem.init = nv04_instmem_init;
213 engine->instmem.takedown = nv04_instmem_takedown;
214 engine->instmem.suspend = nv04_instmem_suspend;
215 engine->instmem.resume = nv04_instmem_resume;
216 engine->instmem.populate = nv04_instmem_populate;
217 engine->instmem.clear = nv04_instmem_clear;
218 engine->instmem.bind = nv04_instmem_bind;
219 engine->instmem.unbind = nv04_instmem_unbind;
220 engine->instmem.flush = nv04_instmem_flush;
221 engine->mc.init = nv04_mc_init;
222 engine->mc.takedown = nv04_mc_takedown;
223 engine->timer.init = nv04_timer_init;
224 engine->timer.read = nv04_timer_read;
225 engine->timer.takedown = nv04_timer_takedown;
226 engine->fb.init = nv30_fb_init;
227 engine->fb.takedown = nv30_fb_takedown;
228 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
229 engine->graph.grclass = nv30_graph_grclass;
230 engine->graph.init = nv30_graph_init;
231 engine->graph.takedown = nv20_graph_takedown;
232 engine->graph.fifo_access = nv04_graph_fifo_access;
233 engine->graph.channel = nv10_graph_channel;
234 engine->graph.create_context = nv20_graph_create_context;
235 engine->graph.destroy_context = nv20_graph_destroy_context;
236 engine->graph.load_context = nv20_graph_load_context;
237 engine->graph.unload_context = nv20_graph_unload_context;
238 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
239 engine->fifo.channels = 32;
240 engine->fifo.init = nv10_fifo_init;
241 engine->fifo.takedown = nouveau_stub_takedown;
242 engine->fifo.disable = nv04_fifo_disable;
243 engine->fifo.enable = nv04_fifo_enable;
244 engine->fifo.reassign = nv04_fifo_reassign;
245 engine->fifo.cache_pull = nv04_fifo_cache_pull;
246 engine->fifo.channel_id = nv10_fifo_channel_id;
247 engine->fifo.create_context = nv10_fifo_create_context;
248 engine->fifo.destroy_context = nv10_fifo_destroy_context;
249 engine->fifo.load_context = nv10_fifo_load_context;
250 engine->fifo.unload_context = nv10_fifo_unload_context;
251 engine->display.early_init = nv04_display_early_init;
252 engine->display.late_takedown = nv04_display_late_takedown;
253 engine->display.create = nv04_display_create;
254 engine->display.init = nv04_display_init;
255 engine->display.destroy = nv04_display_destroy;
256 engine->gpio.init = nouveau_stub_init;
257 engine->gpio.takedown = nouveau_stub_takedown;
258 engine->gpio.get = nv10_gpio_get;
259 engine->gpio.set = nv10_gpio_set;
260 engine->gpio.irq_enable = NULL;
261 engine->pm.clock_get = nv04_pm_clock_get;
262 engine->pm.clock_pre = nv04_pm_clock_pre;
263 engine->pm.clock_set = nv04_pm_clock_set;
264 engine->pm.voltage_get = nouveau_voltage_gpio_get;
265 engine->pm.voltage_set = nouveau_voltage_gpio_set;
266 break;
267 case 0x40:
268 case 0x60:
269 engine->instmem.init = nv04_instmem_init;
270 engine->instmem.takedown = nv04_instmem_takedown;
271 engine->instmem.suspend = nv04_instmem_suspend;
272 engine->instmem.resume = nv04_instmem_resume;
273 engine->instmem.populate = nv04_instmem_populate;
274 engine->instmem.clear = nv04_instmem_clear;
275 engine->instmem.bind = nv04_instmem_bind;
276 engine->instmem.unbind = nv04_instmem_unbind;
277 engine->instmem.flush = nv04_instmem_flush;
278 engine->mc.init = nv40_mc_init;
279 engine->mc.takedown = nv40_mc_takedown;
280 engine->timer.init = nv04_timer_init;
281 engine->timer.read = nv04_timer_read;
282 engine->timer.takedown = nv04_timer_takedown;
283 engine->fb.init = nv40_fb_init;
284 engine->fb.takedown = nv40_fb_takedown;
285 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
286 engine->graph.grclass = nv40_graph_grclass;
287 engine->graph.init = nv40_graph_init;
288 engine->graph.takedown = nv40_graph_takedown;
289 engine->graph.fifo_access = nv04_graph_fifo_access;
290 engine->graph.channel = nv40_graph_channel;
291 engine->graph.create_context = nv40_graph_create_context;
292 engine->graph.destroy_context = nv40_graph_destroy_context;
293 engine->graph.load_context = nv40_graph_load_context;
294 engine->graph.unload_context = nv40_graph_unload_context;
295 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
296 engine->fifo.channels = 32;
297 engine->fifo.init = nv40_fifo_init;
298 engine->fifo.takedown = nouveau_stub_takedown;
299 engine->fifo.disable = nv04_fifo_disable;
300 engine->fifo.enable = nv04_fifo_enable;
301 engine->fifo.reassign = nv04_fifo_reassign;
302 engine->fifo.cache_pull = nv04_fifo_cache_pull;
303 engine->fifo.channel_id = nv10_fifo_channel_id;
304 engine->fifo.create_context = nv40_fifo_create_context;
305 engine->fifo.destroy_context = nv40_fifo_destroy_context;
306 engine->fifo.load_context = nv40_fifo_load_context;
307 engine->fifo.unload_context = nv40_fifo_unload_context;
308 engine->display.early_init = nv04_display_early_init;
309 engine->display.late_takedown = nv04_display_late_takedown;
310 engine->display.create = nv04_display_create;
311 engine->display.init = nv04_display_init;
312 engine->display.destroy = nv04_display_destroy;
313 engine->gpio.init = nouveau_stub_init;
314 engine->gpio.takedown = nouveau_stub_takedown;
315 engine->gpio.get = nv10_gpio_get;
316 engine->gpio.set = nv10_gpio_set;
317 engine->gpio.irq_enable = NULL;
318 engine->pm.clock_get = nv04_pm_clock_get;
319 engine->pm.clock_pre = nv04_pm_clock_pre;
320 engine->pm.clock_set = nv04_pm_clock_set;
321 engine->pm.voltage_get = nouveau_voltage_gpio_get;
322 engine->pm.voltage_set = nouveau_voltage_gpio_set;
323 engine->pm.temp_get = nv40_temp_get;
324 break;
325 case 0x50:
326 case 0x80: /* gotta love NVIDIA's consistency.. */
327 case 0x90:
328 case 0xA0:
329 engine->instmem.init = nv50_instmem_init;
330 engine->instmem.takedown = nv50_instmem_takedown;
331 engine->instmem.suspend = nv50_instmem_suspend;
332 engine->instmem.resume = nv50_instmem_resume;
333 engine->instmem.populate = nv50_instmem_populate;
334 engine->instmem.clear = nv50_instmem_clear;
335 engine->instmem.bind = nv50_instmem_bind;
336 engine->instmem.unbind = nv50_instmem_unbind;
337 if (dev_priv->chipset == 0x50)
338 engine->instmem.flush = nv50_instmem_flush;
339 else
340 engine->instmem.flush = nv84_instmem_flush;
341 engine->mc.init = nv50_mc_init;
342 engine->mc.takedown = nv50_mc_takedown;
343 engine->timer.init = nv04_timer_init;
344 engine->timer.read = nv04_timer_read;
345 engine->timer.takedown = nv04_timer_takedown;
346 engine->fb.init = nv50_fb_init;
347 engine->fb.takedown = nv50_fb_takedown;
348 engine->graph.grclass = nv50_graph_grclass;
349 engine->graph.init = nv50_graph_init;
350 engine->graph.takedown = nv50_graph_takedown;
351 engine->graph.fifo_access = nv50_graph_fifo_access;
352 engine->graph.channel = nv50_graph_channel;
353 engine->graph.create_context = nv50_graph_create_context;
354 engine->graph.destroy_context = nv50_graph_destroy_context;
355 engine->graph.load_context = nv50_graph_load_context;
356 engine->graph.unload_context = nv50_graph_unload_context;
357 engine->fifo.channels = 128;
358 engine->fifo.init = nv50_fifo_init;
359 engine->fifo.takedown = nv50_fifo_takedown;
360 engine->fifo.disable = nv04_fifo_disable;
361 engine->fifo.enable = nv04_fifo_enable;
362 engine->fifo.reassign = nv04_fifo_reassign;
363 engine->fifo.channel_id = nv50_fifo_channel_id;
364 engine->fifo.create_context = nv50_fifo_create_context;
365 engine->fifo.destroy_context = nv50_fifo_destroy_context;
366 engine->fifo.load_context = nv50_fifo_load_context;
367 engine->fifo.unload_context = nv50_fifo_unload_context;
368 engine->display.early_init = nv50_display_early_init;
369 engine->display.late_takedown = nv50_display_late_takedown;
370 engine->display.create = nv50_display_create;
371 engine->display.init = nv50_display_init;
372 engine->display.destroy = nv50_display_destroy;
373 engine->gpio.init = nv50_gpio_init;
374 engine->gpio.takedown = nouveau_stub_takedown;
375 engine->gpio.get = nv50_gpio_get;
376 engine->gpio.set = nv50_gpio_set;
377 engine->gpio.irq_enable = nv50_gpio_irq_enable;
378 switch (dev_priv->chipset) {
379 case 0xa3:
380 case 0xa5:
381 case 0xa8:
382 case 0xaf:
383 engine->pm.clock_get = nva3_pm_clock_get;
384 engine->pm.clock_pre = nva3_pm_clock_pre;
385 engine->pm.clock_set = nva3_pm_clock_set;
386 break;
387 default:
388 engine->pm.clock_get = nv50_pm_clock_get;
389 engine->pm.clock_pre = nv50_pm_clock_pre;
390 engine->pm.clock_set = nv50_pm_clock_set;
391 break;
392 }
393 engine->pm.voltage_get = nouveau_voltage_gpio_get;
394 engine->pm.voltage_set = nouveau_voltage_gpio_set;
395 if (dev_priv->chipset >= 0x84)
396 engine->pm.temp_get = nv84_temp_get;
397 else
398 engine->pm.temp_get = nv40_temp_get;
399 break;
400 case 0xC0:
401 engine->instmem.init = nvc0_instmem_init;
402 engine->instmem.takedown = nvc0_instmem_takedown;
403 engine->instmem.suspend = nvc0_instmem_suspend;
404 engine->instmem.resume = nvc0_instmem_resume;
405 engine->instmem.populate = nvc0_instmem_populate;
406 engine->instmem.clear = nvc0_instmem_clear;
407 engine->instmem.bind = nvc0_instmem_bind;
408 engine->instmem.unbind = nvc0_instmem_unbind;
409 engine->instmem.flush = nvc0_instmem_flush;
410 engine->mc.init = nv50_mc_init;
411 engine->mc.takedown = nv50_mc_takedown;
412 engine->timer.init = nv04_timer_init;
413 engine->timer.read = nv04_timer_read;
414 engine->timer.takedown = nv04_timer_takedown;
415 engine->fb.init = nvc0_fb_init;
416 engine->fb.takedown = nvc0_fb_takedown;
417 engine->graph.grclass = NULL; //nvc0_graph_grclass;
418 engine->graph.init = nvc0_graph_init;
419 engine->graph.takedown = nvc0_graph_takedown;
420 engine->graph.fifo_access = nvc0_graph_fifo_access;
421 engine->graph.channel = nvc0_graph_channel;
422 engine->graph.create_context = nvc0_graph_create_context;
423 engine->graph.destroy_context = nvc0_graph_destroy_context;
424 engine->graph.load_context = nvc0_graph_load_context;
425 engine->graph.unload_context = nvc0_graph_unload_context;
426 engine->fifo.channels = 128;
427 engine->fifo.init = nvc0_fifo_init;
428 engine->fifo.takedown = nvc0_fifo_takedown;
429 engine->fifo.disable = nvc0_fifo_disable;
430 engine->fifo.enable = nvc0_fifo_enable;
431 engine->fifo.reassign = nvc0_fifo_reassign;
432 engine->fifo.channel_id = nvc0_fifo_channel_id;
433 engine->fifo.create_context = nvc0_fifo_create_context;
434 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
435 engine->fifo.load_context = nvc0_fifo_load_context;
436 engine->fifo.unload_context = nvc0_fifo_unload_context;
437 engine->display.early_init = nv50_display_early_init;
438 engine->display.late_takedown = nv50_display_late_takedown;
439 engine->display.create = nv50_display_create;
440 engine->display.init = nv50_display_init;
441 engine->display.destroy = nv50_display_destroy;
442 engine->gpio.init = nv50_gpio_init;
443 engine->gpio.takedown = nouveau_stub_takedown;
444 engine->gpio.get = nv50_gpio_get;
445 engine->gpio.set = nv50_gpio_set;
446 engine->gpio.irq_enable = nv50_gpio_irq_enable;
447 break;
448 default:
449 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
450 return 1;
451 }
452
453 return 0;
454 }
455
456 static unsigned int
457 nouveau_vga_set_decode(void *priv, bool state)
458 {
459 struct drm_device *dev = priv;
460 struct drm_nouveau_private *dev_priv = dev->dev_private;
461
462 if (dev_priv->chipset >= 0x40)
463 nv_wr32(dev, 0x88054, state);
464 else
465 nv_wr32(dev, 0x1854, state);
466
467 if (state)
468 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
469 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
470 else
471 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
472 }
473
474 static int
475 nouveau_card_init_channel(struct drm_device *dev)
476 {
477 struct drm_nouveau_private *dev_priv = dev->dev_private;
478 struct nouveau_gpuobj *gpuobj = NULL;
479 int ret;
480
481 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
482 (struct drm_file *)-2, NvDmaFB, NvDmaTT);
483 if (ret)
484 return ret;
485
486 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
487 0, dev_priv->vram_size,
488 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
489 &gpuobj);
490 if (ret)
491 goto out_err;
492
493 ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
494 nouveau_gpuobj_ref(NULL, &gpuobj);
495 if (ret)
496 goto out_err;
497
498 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
499 dev_priv->gart_info.aper_size,
500 NV_DMA_ACCESS_RW, &gpuobj, NULL);
501 if (ret)
502 goto out_err;
503
504 ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
505 nouveau_gpuobj_ref(NULL, &gpuobj);
506 if (ret)
507 goto out_err;
508
509 return 0;
510
511 out_err:
512 nouveau_channel_free(dev_priv->channel);
513 dev_priv->channel = NULL;
514 return ret;
515 }
516
517 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
518 enum vga_switcheroo_state state)
519 {
520 struct drm_device *dev = pci_get_drvdata(pdev);
521 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
522 if (state == VGA_SWITCHEROO_ON) {
523 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
524 nouveau_pci_resume(pdev);
525 drm_kms_helper_poll_enable(dev);
526 } else {
527 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
528 drm_kms_helper_poll_disable(dev);
529 nouveau_pci_suspend(pdev, pmm);
530 }
531 }
532
533 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
534 {
535 struct drm_device *dev = pci_get_drvdata(pdev);
536 bool can_switch;
537
538 spin_lock(&dev->count_lock);
539 can_switch = (dev->open_count == 0);
540 spin_unlock(&dev->count_lock);
541 return can_switch;
542 }
543
544 int
545 nouveau_card_init(struct drm_device *dev)
546 {
547 struct drm_nouveau_private *dev_priv = dev->dev_private;
548 struct nouveau_engine *engine;
549 int ret;
550
551 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
552 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
553 nouveau_switcheroo_can_switch);
554
555 /* Initialise internal driver API hooks */
556 ret = nouveau_init_engine_ptrs(dev);
557 if (ret)
558 goto out;
559 engine = &dev_priv->engine;
560 spin_lock_init(&dev_priv->context_switch_lock);
561
562 /* Make the CRTCs and I2C buses accessible */
563 ret = engine->display.early_init(dev);
564 if (ret)
565 goto out;
566
567 /* Parse BIOS tables / Run init tables if card not POSTed */
568 ret = nouveau_bios_init(dev);
569 if (ret)
570 goto out_display_early;
571
572 nouveau_pm_init(dev);
573
574 ret = nouveau_mem_vram_init(dev);
575 if (ret)
576 goto out_bios;
577
578 ret = nouveau_gpuobj_init(dev);
579 if (ret)
580 goto out_vram;
581
582 ret = engine->instmem.init(dev);
583 if (ret)
584 goto out_gpuobj;
585
586 ret = nouveau_mem_gart_init(dev);
587 if (ret)
588 goto out_instmem;
589
590 /* PMC */
591 ret = engine->mc.init(dev);
592 if (ret)
593 goto out_gart;
594
595 /* PGPIO */
596 ret = engine->gpio.init(dev);
597 if (ret)
598 goto out_mc;
599
600 /* PTIMER */
601 ret = engine->timer.init(dev);
602 if (ret)
603 goto out_gpio;
604
605 /* PFB */
606 ret = engine->fb.init(dev);
607 if (ret)
608 goto out_timer;
609
610 if (nouveau_noaccel)
611 engine->graph.accel_blocked = true;
612 else {
613 /* PGRAPH */
614 ret = engine->graph.init(dev);
615 if (ret)
616 goto out_fb;
617
618 /* PFIFO */
619 ret = engine->fifo.init(dev);
620 if (ret)
621 goto out_graph;
622 }
623
624 ret = engine->display.create(dev);
625 if (ret)
626 goto out_fifo;
627
628 /* this call irq_preinstall, register irq handler and
629 * call irq_postinstall
630 */
631 ret = drm_irq_install(dev);
632 if (ret)
633 goto out_display;
634
635 ret = drm_vblank_init(dev, 0);
636 if (ret)
637 goto out_irq;
638
639 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
640
641 if (!engine->graph.accel_blocked) {
642 ret = nouveau_fence_init(dev);
643 if (ret)
644 goto out_irq;
645
646 ret = nouveau_card_init_channel(dev);
647 if (ret)
648 goto out_fence;
649 }
650
651 ret = nouveau_backlight_init(dev);
652 if (ret)
653 NV_ERROR(dev, "Error %d registering backlight\n", ret);
654
655 nouveau_fbcon_init(dev);
656 drm_kms_helper_poll_init(dev);
657 return 0;
658
659 out_fence:
660 nouveau_fence_fini(dev);
661 out_irq:
662 drm_irq_uninstall(dev);
663 out_display:
664 engine->display.destroy(dev);
665 out_fifo:
666 if (!nouveau_noaccel)
667 engine->fifo.takedown(dev);
668 out_graph:
669 if (!nouveau_noaccel)
670 engine->graph.takedown(dev);
671 out_fb:
672 engine->fb.takedown(dev);
673 out_timer:
674 engine->timer.takedown(dev);
675 out_gpio:
676 engine->gpio.takedown(dev);
677 out_mc:
678 engine->mc.takedown(dev);
679 out_gart:
680 nouveau_mem_gart_fini(dev);
681 out_instmem:
682 engine->instmem.takedown(dev);
683 out_gpuobj:
684 nouveau_gpuobj_takedown(dev);
685 out_vram:
686 nouveau_mem_vram_fini(dev);
687 out_bios:
688 nouveau_pm_fini(dev);
689 nouveau_bios_takedown(dev);
690 out_display_early:
691 engine->display.late_takedown(dev);
692 out:
693 vga_client_register(dev->pdev, NULL, NULL, NULL);
694 return ret;
695 }
696
697 static void nouveau_card_takedown(struct drm_device *dev)
698 {
699 struct drm_nouveau_private *dev_priv = dev->dev_private;
700 struct nouveau_engine *engine = &dev_priv->engine;
701
702 nouveau_backlight_exit(dev);
703
704 if (!engine->graph.accel_blocked) {
705 nouveau_fence_fini(dev);
706 nouveau_channel_free(dev_priv->channel);
707 dev_priv->channel = NULL;
708 }
709
710 if (!nouveau_noaccel) {
711 engine->fifo.takedown(dev);
712 engine->graph.takedown(dev);
713 }
714 engine->fb.takedown(dev);
715 engine->timer.takedown(dev);
716 engine->gpio.takedown(dev);
717 engine->mc.takedown(dev);
718 engine->display.late_takedown(dev);
719
720 mutex_lock(&dev->struct_mutex);
721 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
722 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
723 mutex_unlock(&dev->struct_mutex);
724 nouveau_mem_gart_fini(dev);
725
726 engine->instmem.takedown(dev);
727 nouveau_gpuobj_takedown(dev);
728 nouveau_mem_vram_fini(dev);
729
730 drm_irq_uninstall(dev);
731
732 nouveau_pm_fini(dev);
733 nouveau_bios_takedown(dev);
734
735 vga_client_register(dev->pdev, NULL, NULL, NULL);
736 }
737
738 /* here a client dies, release the stuff that was allocated for its
739 * file_priv */
740 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
741 {
742 nouveau_channel_cleanup(dev, file_priv);
743 }
744
745 /* first module load, setup the mmio/fb mapping */
746 /* KMS: we need mmio at load time, not when the first drm client opens. */
747 int nouveau_firstopen(struct drm_device *dev)
748 {
749 return 0;
750 }
751
752 /* if we have an OF card, copy vbios to RAMIN */
753 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
754 {
755 #if defined(__powerpc__)
756 int size, i;
757 const uint32_t *bios;
758 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
759 if (!dn) {
760 NV_INFO(dev, "Unable to get the OF node\n");
761 return;
762 }
763
764 bios = of_get_property(dn, "NVDA,BMP", &size);
765 if (bios) {
766 for (i = 0; i < size; i += 4)
767 nv_wi32(dev, i, bios[i/4]);
768 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
769 } else {
770 NV_INFO(dev, "Unable to get the OF bios\n");
771 }
772 #endif
773 }
774
775 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
776 {
777 struct pci_dev *pdev = dev->pdev;
778 struct apertures_struct *aper = alloc_apertures(3);
779 if (!aper)
780 return NULL;
781
782 aper->ranges[0].base = pci_resource_start(pdev, 1);
783 aper->ranges[0].size = pci_resource_len(pdev, 1);
784 aper->count = 1;
785
786 if (pci_resource_len(pdev, 2)) {
787 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
788 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
789 aper->count++;
790 }
791
792 if (pci_resource_len(pdev, 3)) {
793 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
794 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
795 aper->count++;
796 }
797
798 return aper;
799 }
800
801 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
802 {
803 struct drm_nouveau_private *dev_priv = dev->dev_private;
804 bool primary = false;
805 dev_priv->apertures = nouveau_get_apertures(dev);
806 if (!dev_priv->apertures)
807 return -ENOMEM;
808
809 #ifdef CONFIG_X86
810 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
811 #endif
812
813 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
814 return 0;
815 }
816
817 int nouveau_load(struct drm_device *dev, unsigned long flags)
818 {
819 struct drm_nouveau_private *dev_priv;
820 uint32_t reg0;
821 resource_size_t mmio_start_offs;
822 int ret;
823
824 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
825 if (!dev_priv) {
826 ret = -ENOMEM;
827 goto err_out;
828 }
829 dev->dev_private = dev_priv;
830 dev_priv->dev = dev;
831
832 dev_priv->flags = flags & NOUVEAU_FLAGS;
833
834 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
835 dev->pci_vendor, dev->pci_device, dev->pdev->class);
836
837 dev_priv->wq = create_workqueue("nouveau");
838 if (!dev_priv->wq) {
839 ret = -EINVAL;
840 goto err_priv;
841 }
842
843 /* resource 0 is mmio regs */
844 /* resource 1 is linear FB */
845 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
846 /* resource 6 is bios */
847
848 /* map the mmio regs */
849 mmio_start_offs = pci_resource_start(dev->pdev, 0);
850 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
851 if (!dev_priv->mmio) {
852 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
853 "Please report your setup to " DRIVER_EMAIL "\n");
854 ret = -EINVAL;
855 goto err_wq;
856 }
857 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
858 (unsigned long long)mmio_start_offs);
859
860 #ifdef __BIG_ENDIAN
861 /* Put the card in BE mode if it's not */
862 if (nv_rd32(dev, NV03_PMC_BOOT_1))
863 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
864
865 DRM_MEMORYBARRIER();
866 #endif
867
868 /* Time to determine the card architecture */
869 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
870
871 /* We're dealing with >=NV10 */
872 if ((reg0 & 0x0f000000) > 0) {
873 /* Bit 27-20 contain the architecture in hex */
874 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
875 /* NV04 or NV05 */
876 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
877 if (reg0 & 0x00f00000)
878 dev_priv->chipset = 0x05;
879 else
880 dev_priv->chipset = 0x04;
881 } else
882 dev_priv->chipset = 0xff;
883
884 switch (dev_priv->chipset & 0xf0) {
885 case 0x00:
886 case 0x10:
887 case 0x20:
888 case 0x30:
889 dev_priv->card_type = dev_priv->chipset & 0xf0;
890 break;
891 case 0x40:
892 case 0x60:
893 dev_priv->card_type = NV_40;
894 break;
895 case 0x50:
896 case 0x80:
897 case 0x90:
898 case 0xa0:
899 dev_priv->card_type = NV_50;
900 break;
901 case 0xc0:
902 dev_priv->card_type = NV_C0;
903 break;
904 default:
905 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
906 ret = -EINVAL;
907 goto err_mmio;
908 }
909
910 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
911 dev_priv->card_type, reg0);
912
913 ret = nouveau_remove_conflicting_drivers(dev);
914 if (ret)
915 goto err_mmio;
916
917 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
918 if (dev_priv->card_type >= NV_40) {
919 int ramin_bar = 2;
920 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
921 ramin_bar = 3;
922
923 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
924 dev_priv->ramin =
925 ioremap(pci_resource_start(dev->pdev, ramin_bar),
926 dev_priv->ramin_size);
927 if (!dev_priv->ramin) {
928 NV_ERROR(dev, "Failed to PRAMIN BAR");
929 ret = -ENOMEM;
930 goto err_mmio;
931 }
932 } else {
933 dev_priv->ramin_size = 1 * 1024 * 1024;
934 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
935 dev_priv->ramin_size);
936 if (!dev_priv->ramin) {
937 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
938 ret = -ENOMEM;
939 goto err_mmio;
940 }
941 }
942
943 nouveau_OF_copy_vbios_to_ramin(dev);
944
945 /* Special flags */
946 if (dev->pci_device == 0x01a0)
947 dev_priv->flags |= NV_NFORCE;
948 else if (dev->pci_device == 0x01f0)
949 dev_priv->flags |= NV_NFORCE2;
950
951 /* For kernel modesetting, init card now and bring up fbcon */
952 ret = nouveau_card_init(dev);
953 if (ret)
954 goto err_ramin;
955
956 return 0;
957
958 err_ramin:
959 iounmap(dev_priv->ramin);
960 err_mmio:
961 iounmap(dev_priv->mmio);
962 err_wq:
963 destroy_workqueue(dev_priv->wq);
964 err_priv:
965 kfree(dev_priv);
966 dev->dev_private = NULL;
967 err_out:
968 return ret;
969 }
970
971 void nouveau_lastclose(struct drm_device *dev)
972 {
973 }
974
975 int nouveau_unload(struct drm_device *dev)
976 {
977 struct drm_nouveau_private *dev_priv = dev->dev_private;
978 struct nouveau_engine *engine = &dev_priv->engine;
979
980 drm_kms_helper_poll_fini(dev);
981 nouveau_fbcon_fini(dev);
982 engine->display.destroy(dev);
983 nouveau_card_takedown(dev);
984
985 iounmap(dev_priv->mmio);
986 iounmap(dev_priv->ramin);
987
988 kfree(dev_priv);
989 dev->dev_private = NULL;
990 return 0;
991 }
992
993 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
994 struct drm_file *file_priv)
995 {
996 struct drm_nouveau_private *dev_priv = dev->dev_private;
997 struct drm_nouveau_getparam *getparam = data;
998
999 switch (getparam->param) {
1000 case NOUVEAU_GETPARAM_CHIPSET_ID:
1001 getparam->value = dev_priv->chipset;
1002 break;
1003 case NOUVEAU_GETPARAM_PCI_VENDOR:
1004 getparam->value = dev->pci_vendor;
1005 break;
1006 case NOUVEAU_GETPARAM_PCI_DEVICE:
1007 getparam->value = dev->pci_device;
1008 break;
1009 case NOUVEAU_GETPARAM_BUS_TYPE:
1010 if (drm_device_is_agp(dev))
1011 getparam->value = NV_AGP;
1012 else if (drm_device_is_pcie(dev))
1013 getparam->value = NV_PCIE;
1014 else
1015 getparam->value = NV_PCI;
1016 break;
1017 case NOUVEAU_GETPARAM_FB_PHYSICAL:
1018 getparam->value = dev_priv->fb_phys;
1019 break;
1020 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
1021 getparam->value = dev_priv->gart_info.aper_base;
1022 break;
1023 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
1024 if (dev->sg) {
1025 getparam->value = (unsigned long)dev->sg->virtual;
1026 } else {
1027 NV_ERROR(dev, "Requested PCIGART address, "
1028 "while no PCIGART was created\n");
1029 return -EINVAL;
1030 }
1031 break;
1032 case NOUVEAU_GETPARAM_FB_SIZE:
1033 getparam->value = dev_priv->fb_available_size;
1034 break;
1035 case NOUVEAU_GETPARAM_AGP_SIZE:
1036 getparam->value = dev_priv->gart_info.aper_size;
1037 break;
1038 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1039 getparam->value = dev_priv->vm_vram_base;
1040 break;
1041 case NOUVEAU_GETPARAM_PTIMER_TIME:
1042 getparam->value = dev_priv->engine.timer.read(dev);
1043 break;
1044 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1045 /* NV40 and NV50 versions are quite different, but register
1046 * address is the same. User is supposed to know the card
1047 * family anyway... */
1048 if (dev_priv->chipset >= 0x40) {
1049 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1050 break;
1051 }
1052 /* FALLTHRU */
1053 default:
1054 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
1055 return -EINVAL;
1056 }
1057
1058 return 0;
1059 }
1060
1061 int
1062 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1063 struct drm_file *file_priv)
1064 {
1065 struct drm_nouveau_setparam *setparam = data;
1066
1067 switch (setparam->param) {
1068 default:
1069 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
1070 return -EINVAL;
1071 }
1072
1073 return 0;
1074 }
1075
1076 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1077 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
1078 uint32_t reg, uint32_t mask, uint32_t val)
1079 {
1080 struct drm_nouveau_private *dev_priv = dev->dev_private;
1081 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1082 uint64_t start = ptimer->read(dev);
1083
1084 do {
1085 if ((nv_rd32(dev, reg) & mask) == val)
1086 return true;
1087 } while (ptimer->read(dev) - start < timeout);
1088
1089 return false;
1090 }
1091
1092 /* Waits for PGRAPH to go completely idle */
1093 bool nouveau_wait_for_idle(struct drm_device *dev)
1094 {
1095 if (!nv_wait(dev, NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
1096 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1097 nv_rd32(dev, NV04_PGRAPH_STATUS));
1098 return false;
1099 }
1100
1101 return true;
1102 }
1103
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