drivers/gpu/drm/nouveau/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31
  32 #define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))
  33 #define NV04_RAMFC__SIZE 32
  34 #define NV04_RAMFC_DMA_PUT                                       0x00
  35 #define NV04_RAMFC_DMA_GET                                       0x04
  36 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
  37 #define NV04_RAMFC_DMA_STATE                                     0x0C
  38 #define NV04_RAMFC_DMA_FETCH                                     0x10
  39 #define NV04_RAMFC_ENGINE                                        0x14
  40 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
  41
  42 #define RAMFC_WR(offset, val) nv_wo32(chan->ramfc, NV04_RAMFC_##offset, (val))
  43 #define RAMFC_RD(offset)      nv_ro32(chan->ramfc, NV04_RAMFC_##offset)
  44
  45 void
  46 nv04_fifo_disable(struct drm_device *dev)
  47 {
  48         uint32_t tmp;
  49
  50         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
  51         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
  52         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
  53         tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
  54         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
  55 }
  56
  57 void
  58 nv04_fifo_enable(struct drm_device *dev)
  59 {
  60         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
  61         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
  62 }
  63
  64 bool
  65 nv04_fifo_reassign(struct drm_device *dev, bool enable)
  66 {
  67         uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
  68
  69         nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
  70         return (reassign == 1);
  71 }
  72
  73 bool
  74 nv04_fifo_cache_flush(struct drm_device *dev)
  75 {
  76         struct drm_nouveau_private *dev_priv = dev->dev_private;
  77         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  78         uint64_t start = ptimer->read(dev);
  79
  80         do {
  81                 if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
  82                     nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
  83                         return true;
  84
  85         } while (ptimer->read(dev) - start < 100000000);
  86
  87         NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
  88
  89         return false;
  90 }
  91
  92 bool
  93 nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
  94 {
  95         uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
  96
  97         if (enable) {
  98                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
  99         } else {
 100                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
 101                 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
 102         }
 103
 104         return !!(pull & 1);
 105 }
 106
 107 int
 108 nv04_fifo_channel_id(struct drm_device *dev)
 109 {
 110         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 111                         NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
 112 }
 113
 114 #ifdef __BIG_ENDIAN
 115 #define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
 116 #else
 117 #define DMA_FETCH_ENDIANNESS 0
 118 #endif
 119
 120 int
 121 nv04_fifo_create_context(struct nouveau_channel *chan)
 122 {
 123         struct drm_device *dev = chan->dev;
 124         struct drm_nouveau_private *dev_priv = dev->dev_private;
 125         unsigned long flags;
 126         int ret;
 127
 128         ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
 129                                                 NV04_RAMFC__SIZE,
 130                                                 NVOBJ_FLAG_ZERO_ALLOC |
 131                                                 NVOBJ_FLAG_ZERO_FREE,
 132                                                 &chan->ramfc);
 133         if (ret)
 134                 return ret;
 135
 136         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 137
 138         /* Setup initial state */
 139         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
 140         RAMFC_WR(DMA_GET, chan->pushbuf_base);
 141         RAMFC_WR(DMA_INSTANCE, chan->pushbuf->pinst >> 4);
 142         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 143                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 144                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 145                              DMA_FETCH_ENDIANNESS));
 146
 147         /* enable the fifo dma operation */
 148         nv_wr32(dev, NV04_PFIFO_MODE,
 149                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
 150
 151         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 152         return 0;
 153 }
 154
 155 void
 156 nv04_fifo_destroy_context(struct nouveau_channel *chan)
 157 {
 158         struct drm_device *dev = chan->dev;
 159
 160         nv_wr32(dev, NV04_PFIFO_MODE,
 161                 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
 162
 163         nouveau_gpuobj_ref(NULL, &chan->ramfc);
 164 }
 165
 166 static void
 167 nv04_fifo_do_load_context(struct drm_device *dev, int chid)
 168 {
 169         struct drm_nouveau_private *dev_priv = dev->dev_private;
 170         uint32_t fc = NV04_RAMFC(chid), tmp;
 171
 172         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
 173         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
 174         tmp = nv_ri32(dev, fc + 8);
 175         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
 176         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 177         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
 178         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
 179         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
 180         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
 181
 182         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 183         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 184 }
 185
 186 int
 187 nv04_fifo_load_context(struct nouveau_channel *chan)
 188 {
 189         uint32_t tmp;
 190
 191         nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
 192                            NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 193         nv04_fifo_do_load_context(chan->dev, chan->id);
 194         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 195
 196         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 197         tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 198         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 199
 200         return 0;
 201 }
 202
 203 int
 204 nv04_fifo_unload_context(struct drm_device *dev)
 205 {
 206         struct drm_nouveau_private *dev_priv = dev->dev_private;
 207         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 208         struct nouveau_channel *chan = NULL;
 209         uint32_t tmp;
 210         int chid;
 211
 212         chid = pfifo->channel_id(dev);
 213         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 214                 return 0;
 215
 216         chan = dev_priv->fifos[chid];
 217         if (!chan) {
 218                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 219                 return -EINVAL;
 220         }
 221
 222         RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 223         RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 224         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 225         tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
 226         RAMFC_WR(DMA_INSTANCE, tmp);
 227         RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 228         RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
 229         RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 230         RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 231
 232         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 233         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 234         return 0;
 235 }
 236
 237 static void
 238 nv04_fifo_init_reset(struct drm_device *dev)
 239 {
 240         nv_wr32(dev, NV03_PMC_ENABLE,
 241                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 242         nv_wr32(dev, NV03_PMC_ENABLE,
 243                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 244
 245         nv_wr32(dev, 0x003224, 0x000f0078);
 246         nv_wr32(dev, 0x002044, 0x0101ffff);
 247         nv_wr32(dev, 0x002040, 0x000000ff);
 248         nv_wr32(dev, 0x002500, 0x00000000);
 249         nv_wr32(dev, 0x003000, 0x00000000);
 250         nv_wr32(dev, 0x003050, 0x00000000);
 251         nv_wr32(dev, 0x003200, 0x00000000);
 252         nv_wr32(dev, 0x003250, 0x00000000);
 253         nv_wr32(dev, 0x003220, 0x00000000);
 254
 255         nv_wr32(dev, 0x003250, 0x00000000);
 256         nv_wr32(dev, 0x003270, 0x00000000);
 257         nv_wr32(dev, 0x003210, 0x00000000);
 258 }
 259
 260 static void
 261 nv04_fifo_init_ramxx(struct drm_device *dev)
 262 {
 263         struct drm_nouveau_private *dev_priv = dev->dev_private;
 264
 265         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 266                                        ((dev_priv->ramht->bits - 9) << 16) |
 267                                        (dev_priv->ramht->gpuobj->pinst >> 8));
 268         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
 269         nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
 270 }
 271
 272 static void
 273 nv04_fifo_init_intr(struct drm_device *dev)
 274 {
 275         nv_wr32(dev, 0x002100, 0xffffffff);
 276         nv_wr32(dev, 0x002140, 0xffffffff);
 277 }
 278
 279 int
 280 nv04_fifo_init(struct drm_device *dev)
 281 {
 282         struct drm_nouveau_private *dev_priv = dev->dev_private;
 283         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 284         int i;
 285
 286         nv04_fifo_init_reset(dev);
 287         nv04_fifo_init_ramxx(dev);
 288
 289         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 290         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 291
 292         nv04_fifo_init_intr(dev);
 293         pfifo->enable(dev);
 294         pfifo->reassign(dev, true);
 295
 296         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 297                 if (dev_priv->fifos[i]) {
 298                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 299                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 300                 }
 301         }
 302
 303         return 0;
 304 }
 305