drivers/gpu/drm/nouveau/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31 #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
  32 #define NV04_RAMFC__SIZE 32
  33 #define NV04_RAMFC_DMA_PUT                                       0x00
  34 #define NV04_RAMFC_DMA_GET                                       0x04
  35 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
  36 #define NV04_RAMFC_DMA_STATE                                     0x0C
  37 #define NV04_RAMFC_DMA_FETCH                                     0x10
  38 #define NV04_RAMFC_ENGINE                                        0x14
  39 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
  40
  41 #define RAMFC_WR(offset, val) nv_wo32(chan->ramfc, NV04_RAMFC_##offset, (val))
  42 #define RAMFC_RD(offset)      nv_ro32(chan->ramfc, NV04_RAMFC_##offset)
  43
  44 void
  45 nv04_fifo_disable(struct drm_device *dev)
  46 {
  47         uint32_t tmp;
  48
  49         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
  50         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
  51         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
  52         tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
  53         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
  54 }
  55
  56 void
  57 nv04_fifo_enable(struct drm_device *dev)
  58 {
  59         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
  60         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
  61 }
  62
  63 bool
  64 nv04_fifo_reassign(struct drm_device *dev, bool enable)
  65 {
  66         uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
  67
  68         nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
  69         return (reassign == 1);
  70 }
  71
  72 bool
  73 nv04_fifo_cache_flush(struct drm_device *dev)
  74 {
  75         struct drm_nouveau_private *dev_priv = dev->dev_private;
  76         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  77         uint64_t start = ptimer->read(dev);
  78
  79         do {
  80                 if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
  81                     nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
  82                         return true;
  83
  84         } while (ptimer->read(dev) - start < 100000000);
  85
  86         NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
  87
  88         return false;
  89 }
  90
  91 bool
  92 nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
  93 {
  94         uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
  95
  96         if (enable) {
  97                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
  98         } else {
  99                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
 100                 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
 101         }
 102
 103         return !!(pull & 1);
 104 }
 105
 106 int
 107 nv04_fifo_channel_id(struct drm_device *dev)
 108 {
 109         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 110                         NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
 111 }
 112
 113 #ifdef __BIG_ENDIAN
 114 #define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
 115 #else
 116 #define DMA_FETCH_ENDIANNESS 0
 117 #endif
 118
 119 int
 120 nv04_fifo_create_context(struct nouveau_channel *chan)
 121 {
 122         struct drm_device *dev = chan->dev;
 123         struct drm_nouveau_private *dev_priv = dev->dev_private;
 124         unsigned long flags;
 125         int ret;
 126
 127         ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
 128                                                 NV04_RAMFC__SIZE,
 129                                                 NVOBJ_FLAG_ZERO_ALLOC |
 130                                                 NVOBJ_FLAG_ZERO_FREE,
 131                                                 &chan->ramfc);
 132         if (ret)
 133                 return ret;
 134
 135         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 136
 137         /* Setup initial state */
 138         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
 139         RAMFC_WR(DMA_GET, chan->pushbuf_base);
 140         RAMFC_WR(DMA_INSTANCE, chan->pushbuf->pinst >> 4);
 141         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 142                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 143                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 144                              DMA_FETCH_ENDIANNESS));
 145
 146         /* enable the fifo dma operation */
 147         nv_wr32(dev, NV04_PFIFO_MODE,
 148                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
 149
 150         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 151         return 0;
 152 }
 153
 154 void
 155 nv04_fifo_destroy_context(struct nouveau_channel *chan)
 156 {
 157         struct drm_device *dev = chan->dev;
 158
 159         nv_wr32(dev, NV04_PFIFO_MODE,
 160                 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
 161
 162         nouveau_gpuobj_ref(NULL, &chan->ramfc);
 163 }
 164
 165 static void
 166 nv04_fifo_do_load_context(struct drm_device *dev, int chid)
 167 {
 168         struct drm_nouveau_private *dev_priv = dev->dev_private;
 169         uint32_t fc = NV04_RAMFC(chid), tmp;
 170
 171         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
 172         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
 173         tmp = nv_ri32(dev, fc + 8);
 174         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
 175         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 176         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
 177         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
 178         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
 179         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
 180
 181         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 182         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 183 }
 184
 185 int
 186 nv04_fifo_load_context(struct nouveau_channel *chan)
 187 {
 188         uint32_t tmp;
 189
 190         nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
 191                            NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 192         nv04_fifo_do_load_context(chan->dev, chan->id);
 193         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 194
 195         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 196         tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 197         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 198
 199         return 0;
 200 }
 201
 202 int
 203 nv04_fifo_unload_context(struct drm_device *dev)
 204 {
 205         struct drm_nouveau_private *dev_priv = dev->dev_private;
 206         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 207         struct nouveau_channel *chan = NULL;
 208         uint32_t tmp;
 209         int chid;
 210
 211         chid = pfifo->channel_id(dev);
 212         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 213                 return 0;
 214
 215         chan = dev_priv->fifos[chid];
 216         if (!chan) {
 217                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 218                 return -EINVAL;
 219         }
 220
 221         RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 222         RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 223         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 224         tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
 225         RAMFC_WR(DMA_INSTANCE, tmp);
 226         RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 227         RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
 228         RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 229         RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 230
 231         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 232         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 233         return 0;
 234 }
 235
 236 static void
 237 nv04_fifo_init_reset(struct drm_device *dev)
 238 {
 239         nv_wr32(dev, NV03_PMC_ENABLE,
 240                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 241         nv_wr32(dev, NV03_PMC_ENABLE,
 242                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 243
 244         nv_wr32(dev, 0x003224, 0x000f0078);
 245         nv_wr32(dev, 0x002044, 0x0101ffff);
 246         nv_wr32(dev, 0x002040, 0x000000ff);
 247         nv_wr32(dev, 0x002500, 0x00000000);
 248         nv_wr32(dev, 0x003000, 0x00000000);
 249         nv_wr32(dev, 0x003050, 0x00000000);
 250         nv_wr32(dev, 0x003200, 0x00000000);
 251         nv_wr32(dev, 0x003250, 0x00000000);
 252         nv_wr32(dev, 0x003220, 0x00000000);
 253
 254         nv_wr32(dev, 0x003250, 0x00000000);
 255         nv_wr32(dev, 0x003270, 0x00000000);
 256         nv_wr32(dev, 0x003210, 0x00000000);
 257 }
 258
 259 static void
 260 nv04_fifo_init_ramxx(struct drm_device *dev)
 261 {
 262         struct drm_nouveau_private *dev_priv = dev->dev_private;
 263
 264         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 265                                        ((dev_priv->ramht_bits - 9) << 16) |
 266                                        (dev_priv->ramht_offset >> 8));
 267         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
 268         nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);
 269 }
 270
 271 static void
 272 nv04_fifo_init_intr(struct drm_device *dev)
 273 {
 274         nv_wr32(dev, 0x002100, 0xffffffff);
 275         nv_wr32(dev, 0x002140, 0xffffffff);
 276 }
 277
 278 int
 279 nv04_fifo_init(struct drm_device *dev)
 280 {
 281         struct drm_nouveau_private *dev_priv = dev->dev_private;
 282         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 283         int i;
 284
 285         nv04_fifo_init_reset(dev);
 286         nv04_fifo_init_ramxx(dev);
 287
 288         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 289         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 290
 291         nv04_fifo_init_intr(dev);
 292         pfifo->enable(dev);
 293         pfifo->reassign(dev, true);
 294
 295         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 296                 if (dev_priv->fifos[i]) {
 297                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 298                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 299                 }
 300         }
 301
 302         return 0;
 303 }
 304