2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_ramht.h"
32 #define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE))
33 #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
36 nv10_fifo_channel_id(struct drm_device
*dev
)
38 return nv_rd32(dev
, NV03_PFIFO_CACHE1_PUSH1
) &
39 NV10_PFIFO_CACHE1_PUSH1_CHID_MASK
;
43 nv10_fifo_create_context(struct nouveau_channel
*chan
)
45 struct drm_nouveau_private
*dev_priv
= chan
->dev
->dev_private
;
46 struct drm_device
*dev
= chan
->dev
;
47 uint32_t fc
= NV10_RAMFC(chan
->id
);
50 ret
= nouveau_gpuobj_new_fake(dev
, NV10_RAMFC(chan
->id
), ~0,
51 NV10_RAMFC__SIZE
, NVOBJ_FLAG_ZERO_ALLOC
|
52 NVOBJ_FLAG_ZERO_FREE
, &chan
->ramfc
);
56 /* Fill entries that are seen filled in dumps of nvidia driver just
57 * after channel's is put into DMA mode
59 nv_wi32(dev
, fc
+ 0, chan
->pushbuf_base
);
60 nv_wi32(dev
, fc
+ 4, chan
->pushbuf_base
);
61 nv_wi32(dev
, fc
+ 12, chan
->pushbuf
->pinst
>> 4);
62 nv_wi32(dev
, fc
+ 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES
|
63 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES
|
64 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8
|
66 NV_PFIFO_CACHE1_BIG_ENDIAN
|
70 /* enable the fifo dma operation */
71 nv_wr32(dev
, NV04_PFIFO_MODE
,
72 nv_rd32(dev
, NV04_PFIFO_MODE
) | (1 << chan
->id
));
77 nv10_fifo_destroy_context(struct nouveau_channel
*chan
)
79 struct drm_device
*dev
= chan
->dev
;
81 nv_wr32(dev
, NV04_PFIFO_MODE
,
82 nv_rd32(dev
, NV04_PFIFO_MODE
) & ~(1 << chan
->id
));
84 nouveau_gpuobj_ref(NULL
, &chan
->ramfc
);
88 nv10_fifo_do_load_context(struct drm_device
*dev
, int chid
)
90 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
91 uint32_t fc
= NV10_RAMFC(chid
), tmp
;
93 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_PUT
, nv_ri32(dev
, fc
+ 0));
94 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_GET
, nv_ri32(dev
, fc
+ 4));
95 nv_wr32(dev
, NV10_PFIFO_CACHE1_REF_CNT
, nv_ri32(dev
, fc
+ 8));
97 tmp
= nv_ri32(dev
, fc
+ 12);
98 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_INSTANCE
, tmp
& 0xFFFF);
99 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_DCOUNT
, tmp
>> 16);
101 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_STATE
, nv_ri32(dev
, fc
+ 16));
102 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_FETCH
, nv_ri32(dev
, fc
+ 20));
103 nv_wr32(dev
, NV04_PFIFO_CACHE1_ENGINE
, nv_ri32(dev
, fc
+ 24));
104 nv_wr32(dev
, NV04_PFIFO_CACHE1_PULL1
, nv_ri32(dev
, fc
+ 28));
106 if (dev_priv
->chipset
< 0x17)
109 nv_wr32(dev
, NV10_PFIFO_CACHE1_ACQUIRE_VALUE
, nv_ri32(dev
, fc
+ 32));
110 tmp
= nv_ri32(dev
, fc
+ 36);
111 nv_wr32(dev
, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP
, tmp
);
112 nv_wr32(dev
, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT
, nv_ri32(dev
, fc
+ 40));
113 nv_wr32(dev
, NV10_PFIFO_CACHE1_SEMAPHORE
, nv_ri32(dev
, fc
+ 44));
114 nv_wr32(dev
, NV10_PFIFO_CACHE1_DMA_SUBROUTINE
, nv_ri32(dev
, fc
+ 48));
117 nv_wr32(dev
, NV03_PFIFO_CACHE1_GET
, 0);
118 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUT
, 0);
122 nv10_fifo_load_context(struct nouveau_channel
*chan
)
124 struct drm_device
*dev
= chan
->dev
;
127 nv10_fifo_do_load_context(dev
, chan
->id
);
129 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH1
,
130 NV03_PFIFO_CACHE1_PUSH1_DMA
| chan
->id
);
131 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_PUSH
, 1);
133 /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
134 tmp
= nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_CTL
) & ~(1 << 31);
135 nv_wr32(dev
, NV04_PFIFO_CACHE1_DMA_CTL
, tmp
);
141 nv10_fifo_unload_context(struct drm_device
*dev
)
143 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
144 struct nouveau_fifo_engine
*pfifo
= &dev_priv
->engine
.fifo
;
148 chid
= pfifo
->channel_id(dev
);
149 if (chid
< 0 || chid
>= dev_priv
->engine
.fifo
.channels
)
151 fc
= NV10_RAMFC(chid
);
153 nv_wi32(dev
, fc
+ 0, nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_PUT
));
154 nv_wi32(dev
, fc
+ 4, nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_GET
));
155 nv_wi32(dev
, fc
+ 8, nv_rd32(dev
, NV10_PFIFO_CACHE1_REF_CNT
));
156 tmp
= nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_INSTANCE
) & 0xFFFF;
157 tmp
|= (nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_DCOUNT
) << 16);
158 nv_wi32(dev
, fc
+ 12, tmp
);
159 nv_wi32(dev
, fc
+ 16, nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_STATE
));
160 nv_wi32(dev
, fc
+ 20, nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_FETCH
));
161 nv_wi32(dev
, fc
+ 24, nv_rd32(dev
, NV04_PFIFO_CACHE1_ENGINE
));
162 nv_wi32(dev
, fc
+ 28, nv_rd32(dev
, NV04_PFIFO_CACHE1_PULL1
));
164 if (dev_priv
->chipset
< 0x17)
167 nv_wi32(dev
, fc
+ 32, nv_rd32(dev
, NV10_PFIFO_CACHE1_ACQUIRE_VALUE
));
168 tmp
= nv_rd32(dev
, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP
);
169 nv_wi32(dev
, fc
+ 36, tmp
);
170 nv_wi32(dev
, fc
+ 40, nv_rd32(dev
, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT
));
171 nv_wi32(dev
, fc
+ 44, nv_rd32(dev
, NV10_PFIFO_CACHE1_SEMAPHORE
));
172 nv_wi32(dev
, fc
+ 48, nv_rd32(dev
, NV04_PFIFO_CACHE1_DMA_GET
));
175 nv10_fifo_do_load_context(dev
, pfifo
->channels
- 1);
176 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH1
, pfifo
->channels
- 1);
181 nv10_fifo_init_reset(struct drm_device
*dev
)
183 nv_wr32(dev
, NV03_PMC_ENABLE
,
184 nv_rd32(dev
, NV03_PMC_ENABLE
) & ~NV_PMC_ENABLE_PFIFO
);
185 nv_wr32(dev
, NV03_PMC_ENABLE
,
186 nv_rd32(dev
, NV03_PMC_ENABLE
) | NV_PMC_ENABLE_PFIFO
);
188 nv_wr32(dev
, 0x003224, 0x000f0078);
189 nv_wr32(dev
, 0x002044, 0x0101ffff);
190 nv_wr32(dev
, 0x002040, 0x000000ff);
191 nv_wr32(dev
, 0x002500, 0x00000000);
192 nv_wr32(dev
, 0x003000, 0x00000000);
193 nv_wr32(dev
, 0x003050, 0x00000000);
195 nv_wr32(dev
, 0x003258, 0x00000000);
196 nv_wr32(dev
, 0x003210, 0x00000000);
197 nv_wr32(dev
, 0x003270, 0x00000000);
201 nv10_fifo_init_ramxx(struct drm_device
*dev
)
203 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
205 nv_wr32(dev
, NV03_PFIFO_RAMHT
, (0x03 << 24) /* search 128 */ |
206 ((dev_priv
->ramht
->bits
- 9) << 16) |
207 (dev_priv
->ramht
->gpuobj
->pinst
>> 8));
208 nv_wr32(dev
, NV03_PFIFO_RAMRO
, dev_priv
->ramro
->pinst
>> 8);
210 if (dev_priv
->chipset
< 0x17) {
211 nv_wr32(dev
, NV03_PFIFO_RAMFC
, dev_priv
->ramfc
->pinst
>> 8);
213 nv_wr32(dev
, NV03_PFIFO_RAMFC
, (dev_priv
->ramfc
->pinst
>> 8) |
214 (1 << 16) /* 64 Bytes entry*/);
215 /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
220 nv10_fifo_init_intr(struct drm_device
*dev
)
222 nv_wr32(dev
, 0x002100, 0xffffffff);
223 nv_wr32(dev
, 0x002140, 0xffffffff);
227 nv10_fifo_init(struct drm_device
*dev
)
229 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
230 struct nouveau_fifo_engine
*pfifo
= &dev_priv
->engine
.fifo
;
233 nv10_fifo_init_reset(dev
);
234 nv10_fifo_init_ramxx(dev
);
236 nv10_fifo_do_load_context(dev
, pfifo
->channels
- 1);
237 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH1
, pfifo
->channels
- 1);
239 nv10_fifo_init_intr(dev
);
241 pfifo
->reassign(dev
, true);
243 for (i
= 0; i
< dev_priv
->engine
.fifo
.channels
; i
++) {
244 if (dev_priv
->fifos
[i
]) {
245 uint32_t mode
= nv_rd32(dev
, NV04_PFIFO_MODE
);
246 nv_wr32(dev
, NV04_PFIFO_MODE
, mode
| (1 << i
));