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Merge tag 'imx-drm-next-2016-11-10' of git://git.pengutronix.de/git/pza/linux into...
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / nouveau / nv50_display.c
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/dma-mapping.h>
26
27 #include <drm/drmP.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_dp_helper.h>
32 #include <drm/drm_fb_helper.h>
33 #include <drm/drm_plane_helper.h>
34
35 #include <nvif/class.h>
36 #include <nvif/cl0002.h>
37 #include <nvif/cl5070.h>
38 #include <nvif/cl507a.h>
39 #include <nvif/cl507b.h>
40 #include <nvif/cl507c.h>
41 #include <nvif/cl507d.h>
42 #include <nvif/cl507e.h>
43 #include <nvif/event.h>
44
45 #include "nouveau_drv.h"
46 #include "nouveau_dma.h"
47 #include "nouveau_gem.h"
48 #include "nouveau_connector.h"
49 #include "nouveau_encoder.h"
50 #include "nouveau_crtc.h"
51 #include "nouveau_fence.h"
52 #include "nouveau_fbcon.h"
53 #include "nv50_display.h"
54
55 #define EVO_DMA_NR 9
56
57 #define EVO_MASTER (0x00)
58 #define EVO_FLIP(c) (0x01 + (c))
59 #define EVO_OVLY(c) (0x05 + (c))
60 #define EVO_OIMM(c) (0x09 + (c))
61 #define EVO_CURS(c) (0x0d + (c))
62
63 /* offsets in shared sync bo of various structures */
64 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
65 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
66 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
67 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
68 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
69 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
70
71 /******************************************************************************
72 * Atomic state
73 *****************************************************************************/
74 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
75
76 struct nv50_atom {
77 struct drm_atomic_state state;
78
79 struct list_head outp;
80 bool lock_core;
81 bool flush_disable;
82 };
83
84 struct nv50_outp_atom {
85 struct list_head head;
86
87 struct drm_encoder *encoder;
88 bool flush_disable;
89
90 union {
91 struct {
92 bool ctrl:1;
93 };
94 u8 mask;
95 } clr;
96
97 union {
98 struct {
99 bool ctrl:1;
100 };
101 u8 mask;
102 } set;
103 };
104
105 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
106
107 struct nv50_head_atom {
108 struct drm_crtc_state state;
109
110 struct {
111 u16 iW;
112 u16 iH;
113 u16 oW;
114 u16 oH;
115 } view;
116
117 struct nv50_head_mode {
118 bool interlace;
119 u32 clock;
120 struct {
121 u16 active;
122 u16 synce;
123 u16 blanke;
124 u16 blanks;
125 } h;
126 struct {
127 u32 active;
128 u16 synce;
129 u16 blanke;
130 u16 blanks;
131 u16 blank2s;
132 u16 blank2e;
133 u16 blankus;
134 } v;
135 } mode;
136
137 struct {
138 u32 handle;
139 u64 offset:40;
140 } lut;
141
142 struct {
143 bool visible;
144 u32 handle;
145 u64 offset:40;
146 u8 format;
147 u8 kind:7;
148 u8 layout:1;
149 u8 block:4;
150 u32 pitch:20;
151 u16 x;
152 u16 y;
153 u16 w;
154 u16 h;
155 } core;
156
157 struct {
158 bool visible;
159 u32 handle;
160 u64 offset:40;
161 u8 layout:1;
162 u8 format:1;
163 } curs;
164
165 struct {
166 u8 depth;
167 u8 cpp;
168 u16 x;
169 u16 y;
170 u16 w;
171 u16 h;
172 } base;
173
174 struct {
175 u8 cpp;
176 } ovly;
177
178 struct {
179 bool enable:1;
180 u8 bits:2;
181 u8 mode:4;
182 } dither;
183
184 struct {
185 struct {
186 u16 cos:12;
187 u16 sin:12;
188 } sat;
189 } procamp;
190
191 union {
192 struct {
193 bool core:1;
194 bool curs:1;
195 };
196 u8 mask;
197 } clr;
198
199 union {
200 struct {
201 bool core:1;
202 bool curs:1;
203 bool view:1;
204 bool mode:1;
205 bool base:1;
206 bool ovly:1;
207 bool dither:1;
208 bool procamp:1;
209 };
210 u16 mask;
211 } set;
212 };
213
214 static inline struct nv50_head_atom *
215 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
216 {
217 struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
218 if (IS_ERR(statec))
219 return (void *)statec;
220 return nv50_head_atom(statec);
221 }
222
223 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
224
225 struct nv50_wndw_atom {
226 struct drm_plane_state state;
227 u8 interval;
228
229 struct drm_rect clip;
230
231 struct {
232 u32 handle;
233 u16 offset:12;
234 bool awaken:1;
235 } ntfy;
236
237 struct {
238 u32 handle;
239 u16 offset:12;
240 u32 acquire;
241 u32 release;
242 } sema;
243
244 struct {
245 u8 enable:2;
246 } lut;
247
248 struct {
249 u8 mode:2;
250 u8 interval:4;
251
252 u8 format;
253 u8 kind:7;
254 u8 layout:1;
255 u8 block:4;
256 u32 pitch:20;
257 u16 w;
258 u16 h;
259
260 u32 handle;
261 u64 offset;
262 } image;
263
264 struct {
265 u16 x;
266 u16 y;
267 } point;
268
269 union {
270 struct {
271 bool ntfy:1;
272 bool sema:1;
273 bool image:1;
274 };
275 u8 mask;
276 } clr;
277
278 union {
279 struct {
280 bool ntfy:1;
281 bool sema:1;
282 bool image:1;
283 bool lut:1;
284 bool point:1;
285 };
286 u8 mask;
287 } set;
288 };
289
290 /******************************************************************************
291 * EVO channel
292 *****************************************************************************/
293
294 struct nv50_chan {
295 struct nvif_object user;
296 struct nvif_device *device;
297 };
298
299 static int
300 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
301 const s32 *oclass, u8 head, void *data, u32 size,
302 struct nv50_chan *chan)
303 {
304 struct nvif_sclass *sclass;
305 int ret, i, n;
306
307 chan->device = device;
308
309 ret = n = nvif_object_sclass_get(disp, &sclass);
310 if (ret < 0)
311 return ret;
312
313 while (oclass[0]) {
314 for (i = 0; i < n; i++) {
315 if (sclass[i].oclass == oclass[0]) {
316 ret = nvif_object_init(disp, 0, oclass[0],
317 data, size, &chan->user);
318 if (ret == 0)
319 nvif_object_map(&chan->user);
320 nvif_object_sclass_put(&sclass);
321 return ret;
322 }
323 }
324 oclass++;
325 }
326
327 nvif_object_sclass_put(&sclass);
328 return -ENOSYS;
329 }
330
331 static void
332 nv50_chan_destroy(struct nv50_chan *chan)
333 {
334 nvif_object_fini(&chan->user);
335 }
336
337 /******************************************************************************
338 * PIO EVO channel
339 *****************************************************************************/
340
341 struct nv50_pioc {
342 struct nv50_chan base;
343 };
344
345 static void
346 nv50_pioc_destroy(struct nv50_pioc *pioc)
347 {
348 nv50_chan_destroy(&pioc->base);
349 }
350
351 static int
352 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
353 const s32 *oclass, u8 head, void *data, u32 size,
354 struct nv50_pioc *pioc)
355 {
356 return nv50_chan_create(device, disp, oclass, head, data, size,
357 &pioc->base);
358 }
359
360 /******************************************************************************
361 * Overlay Immediate
362 *****************************************************************************/
363
364 struct nv50_oimm {
365 struct nv50_pioc base;
366 };
367
368 static int
369 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
370 int head, struct nv50_oimm *oimm)
371 {
372 struct nv50_disp_cursor_v0 args = {
373 .head = head,
374 };
375 static const s32 oclass[] = {
376 GK104_DISP_OVERLAY,
377 GF110_DISP_OVERLAY,
378 GT214_DISP_OVERLAY,
379 G82_DISP_OVERLAY,
380 NV50_DISP_OVERLAY,
381 0
382 };
383
384 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
385 &oimm->base);
386 }
387
388 /******************************************************************************
389 * DMA EVO channel
390 *****************************************************************************/
391
392 struct nv50_dmac_ctxdma {
393 struct list_head head;
394 struct nvif_object object;
395 };
396
397 struct nv50_dmac {
398 struct nv50_chan base;
399 dma_addr_t handle;
400 u32 *ptr;
401
402 struct nvif_object sync;
403 struct nvif_object vram;
404 struct list_head ctxdma;
405
406 /* Protects against concurrent pushbuf access to this channel, lock is
407 * grabbed by evo_wait (if the pushbuf reservation is successful) and
408 * dropped again by evo_kick. */
409 struct mutex lock;
410 };
411
412 static void
413 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
414 {
415 nvif_object_fini(&ctxdma->object);
416 list_del(&ctxdma->head);
417 kfree(ctxdma);
418 }
419
420 static struct nv50_dmac_ctxdma *
421 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
422 {
423 struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
424 struct nv50_dmac_ctxdma *ctxdma;
425 const u8 kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
426 const u32 handle = 0xfb000000 | kind;
427 struct {
428 struct nv_dma_v0 base;
429 union {
430 struct nv50_dma_v0 nv50;
431 struct gf100_dma_v0 gf100;
432 struct gf119_dma_v0 gf119;
433 };
434 } args = {};
435 u32 argc = sizeof(args.base);
436 int ret;
437
438 list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
439 if (ctxdma->object.handle == handle)
440 return ctxdma;
441 }
442
443 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
444 return ERR_PTR(-ENOMEM);
445 list_add(&ctxdma->head, &dmac->ctxdma);
446
447 args.base.target = NV_DMA_V0_TARGET_VRAM;
448 args.base.access = NV_DMA_V0_ACCESS_RDWR;
449 args.base.start = 0;
450 args.base.limit = drm->device.info.ram_user - 1;
451
452 if (drm->device.info.chipset < 0x80) {
453 args.nv50.part = NV50_DMA_V0_PART_256;
454 argc += sizeof(args.nv50);
455 } else
456 if (drm->device.info.chipset < 0xc0) {
457 args.nv50.part = NV50_DMA_V0_PART_256;
458 args.nv50.kind = kind;
459 argc += sizeof(args.nv50);
460 } else
461 if (drm->device.info.chipset < 0xd0) {
462 args.gf100.kind = kind;
463 argc += sizeof(args.gf100);
464 } else {
465 args.gf119.page = GF119_DMA_V0_PAGE_LP;
466 args.gf119.kind = kind;
467 argc += sizeof(args.gf119);
468 }
469
470 ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
471 &args, argc, &ctxdma->object);
472 if (ret) {
473 nv50_dmac_ctxdma_del(ctxdma);
474 return ERR_PTR(ret);
475 }
476
477 return ctxdma;
478 }
479
480 static void
481 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
482 {
483 struct nvif_device *device = dmac->base.device;
484 struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
485
486 list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
487 nv50_dmac_ctxdma_del(ctxdma);
488 }
489
490 nvif_object_fini(&dmac->vram);
491 nvif_object_fini(&dmac->sync);
492
493 nv50_chan_destroy(&dmac->base);
494
495 if (dmac->ptr) {
496 struct device *dev = nvxx_device(device)->dev;
497 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
498 }
499 }
500
501 static int
502 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
503 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
504 struct nv50_dmac *dmac)
505 {
506 struct nv50_disp_core_channel_dma_v0 *args = data;
507 struct nvif_object pushbuf;
508 int ret;
509
510 mutex_init(&dmac->lock);
511
512 dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
513 &dmac->handle, GFP_KERNEL);
514 if (!dmac->ptr)
515 return -ENOMEM;
516
517 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
518 &(struct nv_dma_v0) {
519 .target = NV_DMA_V0_TARGET_PCI_US,
520 .access = NV_DMA_V0_ACCESS_RD,
521 .start = dmac->handle + 0x0000,
522 .limit = dmac->handle + 0x0fff,
523 }, sizeof(struct nv_dma_v0), &pushbuf);
524 if (ret)
525 return ret;
526
527 args->pushbuf = nvif_handle(&pushbuf);
528
529 ret = nv50_chan_create(device, disp, oclass, head, data, size,
530 &dmac->base);
531 nvif_object_fini(&pushbuf);
532 if (ret)
533 return ret;
534
535 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
536 &(struct nv_dma_v0) {
537 .target = NV_DMA_V0_TARGET_VRAM,
538 .access = NV_DMA_V0_ACCESS_RDWR,
539 .start = syncbuf + 0x0000,
540 .limit = syncbuf + 0x0fff,
541 }, sizeof(struct nv_dma_v0),
542 &dmac->sync);
543 if (ret)
544 return ret;
545
546 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
547 &(struct nv_dma_v0) {
548 .target = NV_DMA_V0_TARGET_VRAM,
549 .access = NV_DMA_V0_ACCESS_RDWR,
550 .start = 0,
551 .limit = device->info.ram_user - 1,
552 }, sizeof(struct nv_dma_v0),
553 &dmac->vram);
554 if (ret)
555 return ret;
556
557 INIT_LIST_HEAD(&dmac->ctxdma);
558 return ret;
559 }
560
561 /******************************************************************************
562 * Core
563 *****************************************************************************/
564
565 struct nv50_mast {
566 struct nv50_dmac base;
567 };
568
569 static int
570 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
571 u64 syncbuf, struct nv50_mast *core)
572 {
573 struct nv50_disp_core_channel_dma_v0 args = {
574 .pushbuf = 0xb0007d00,
575 };
576 static const s32 oclass[] = {
577 GP104_DISP_CORE_CHANNEL_DMA,
578 GP100_DISP_CORE_CHANNEL_DMA,
579 GM200_DISP_CORE_CHANNEL_DMA,
580 GM107_DISP_CORE_CHANNEL_DMA,
581 GK110_DISP_CORE_CHANNEL_DMA,
582 GK104_DISP_CORE_CHANNEL_DMA,
583 GF110_DISP_CORE_CHANNEL_DMA,
584 GT214_DISP_CORE_CHANNEL_DMA,
585 GT206_DISP_CORE_CHANNEL_DMA,
586 GT200_DISP_CORE_CHANNEL_DMA,
587 G82_DISP_CORE_CHANNEL_DMA,
588 NV50_DISP_CORE_CHANNEL_DMA,
589 0
590 };
591
592 return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
593 syncbuf, &core->base);
594 }
595
596 /******************************************************************************
597 * Base
598 *****************************************************************************/
599
600 struct nv50_sync {
601 struct nv50_dmac base;
602 u32 addr;
603 u32 data;
604 };
605
606 static int
607 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
608 int head, u64 syncbuf, struct nv50_sync *base)
609 {
610 struct nv50_disp_base_channel_dma_v0 args = {
611 .pushbuf = 0xb0007c00 | head,
612 .head = head,
613 };
614 static const s32 oclass[] = {
615 GK110_DISP_BASE_CHANNEL_DMA,
616 GK104_DISP_BASE_CHANNEL_DMA,
617 GF110_DISP_BASE_CHANNEL_DMA,
618 GT214_DISP_BASE_CHANNEL_DMA,
619 GT200_DISP_BASE_CHANNEL_DMA,
620 G82_DISP_BASE_CHANNEL_DMA,
621 NV50_DISP_BASE_CHANNEL_DMA,
622 0
623 };
624
625 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
626 syncbuf, &base->base);
627 }
628
629 /******************************************************************************
630 * Overlay
631 *****************************************************************************/
632
633 struct nv50_ovly {
634 struct nv50_dmac base;
635 };
636
637 static int
638 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
639 int head, u64 syncbuf, struct nv50_ovly *ovly)
640 {
641 struct nv50_disp_overlay_channel_dma_v0 args = {
642 .pushbuf = 0xb0007e00 | head,
643 .head = head,
644 };
645 static const s32 oclass[] = {
646 GK104_DISP_OVERLAY_CONTROL_DMA,
647 GF110_DISP_OVERLAY_CONTROL_DMA,
648 GT214_DISP_OVERLAY_CHANNEL_DMA,
649 GT200_DISP_OVERLAY_CHANNEL_DMA,
650 G82_DISP_OVERLAY_CHANNEL_DMA,
651 NV50_DISP_OVERLAY_CHANNEL_DMA,
652 0
653 };
654
655 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
656 syncbuf, &ovly->base);
657 }
658
659 struct nv50_head {
660 struct nouveau_crtc base;
661 struct nv50_ovly ovly;
662 struct nv50_oimm oimm;
663 };
664
665 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
666 #define nv50_ovly(c) (&nv50_head(c)->ovly)
667 #define nv50_oimm(c) (&nv50_head(c)->oimm)
668 #define nv50_chan(c) (&(c)->base.base)
669 #define nv50_vers(c) nv50_chan(c)->user.oclass
670
671 struct nv50_disp {
672 struct nvif_object *disp;
673 struct nv50_mast mast;
674
675 struct nouveau_bo *sync;
676
677 struct mutex mutex;
678 };
679
680 static struct nv50_disp *
681 nv50_disp(struct drm_device *dev)
682 {
683 return nouveau_display(dev)->priv;
684 }
685
686 #define nv50_mast(d) (&nv50_disp(d)->mast)
687
688 /******************************************************************************
689 * EVO channel helpers
690 *****************************************************************************/
691 static u32 *
692 evo_wait(void *evoc, int nr)
693 {
694 struct nv50_dmac *dmac = evoc;
695 struct nvif_device *device = dmac->base.device;
696 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
697
698 mutex_lock(&dmac->lock);
699 if (put + nr >= (PAGE_SIZE / 4) - 8) {
700 dmac->ptr[put] = 0x20000000;
701
702 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
703 if (nvif_msec(device, 2000,
704 if (!nvif_rd32(&dmac->base.user, 0x0004))
705 break;
706 ) < 0) {
707 mutex_unlock(&dmac->lock);
708 printk(KERN_ERR "nouveau: evo channel stalled\n");
709 return NULL;
710 }
711
712 put = 0;
713 }
714
715 return dmac->ptr + put;
716 }
717
718 static void
719 evo_kick(u32 *push, void *evoc)
720 {
721 struct nv50_dmac *dmac = evoc;
722 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
723 mutex_unlock(&dmac->lock);
724 }
725
726 #define evo_mthd(p,m,s) do { \
727 const u32 _m = (m), _s = (s); \
728 if (drm_debug & DRM_UT_KMS) \
729 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \
730 *((p)++) = ((_s << 18) | _m); \
731 } while(0)
732
733 #define evo_data(p,d) do { \
734 const u32 _d = (d); \
735 if (drm_debug & DRM_UT_KMS) \
736 printk(KERN_ERR "\t%08x\n", _d); \
737 *((p)++) = _d; \
738 } while(0)
739
740 /******************************************************************************
741 * Plane
742 *****************************************************************************/
743 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
744
745 struct nv50_wndw {
746 const struct nv50_wndw_func *func;
747 struct nv50_dmac *dmac;
748
749 struct drm_plane plane;
750
751 struct nvif_notify notify;
752 u16 ntfy;
753 u16 sema;
754 u32 data;
755 };
756
757 struct nv50_wndw_func {
758 void *(*dtor)(struct nv50_wndw *);
759 int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
760 struct nv50_head_atom *asyh);
761 void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
762 struct nv50_head_atom *asyh);
763 void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
764 struct nv50_wndw_atom *asyw);
765
766 void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
767 void (*sema_clr)(struct nv50_wndw *);
768 void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
769 void (*ntfy_clr)(struct nv50_wndw *);
770 int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
771 void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
772 void (*image_clr)(struct nv50_wndw *);
773 void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
774 void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
775
776 u32 (*update)(struct nv50_wndw *, u32 interlock);
777 };
778
779 static int
780 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
781 {
782 if (asyw->set.ntfy)
783 return wndw->func->ntfy_wait_begun(wndw, asyw);
784 return 0;
785 }
786
787 static u32
788 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
789 struct nv50_wndw_atom *asyw)
790 {
791 if (asyw->clr.sema && (!asyw->set.sema || flush))
792 wndw->func->sema_clr(wndw);
793 if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
794 wndw->func->ntfy_clr(wndw);
795 if (asyw->clr.image && (!asyw->set.image || flush))
796 wndw->func->image_clr(wndw);
797
798 return flush ? wndw->func->update(wndw, interlock) : 0;
799 }
800
801 static u32
802 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
803 struct nv50_wndw_atom *asyw)
804 {
805 if (interlock) {
806 asyw->image.mode = 0;
807 asyw->image.interval = 1;
808 }
809
810 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
811 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
812 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
813 if (asyw->set.lut ) wndw->func->lut (wndw, asyw);
814 if (asyw->set.point) wndw->func->point (wndw, asyw);
815
816 return wndw->func->update(wndw, interlock);
817 }
818
819 static void
820 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
821 struct nv50_wndw_atom *asyw,
822 struct nv50_head_atom *asyh)
823 {
824 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
825 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
826 wndw->func->release(wndw, asyw, asyh);
827 asyw->ntfy.handle = 0;
828 asyw->sema.handle = 0;
829 }
830
831 static int
832 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
833 struct nv50_wndw_atom *asyw,
834 struct nv50_head_atom *asyh)
835 {
836 struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
837 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
838 int ret;
839
840 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
841 asyw->clip.x1 = 0;
842 asyw->clip.y1 = 0;
843 asyw->clip.x2 = asyh->state.mode.hdisplay;
844 asyw->clip.y2 = asyh->state.mode.vdisplay;
845
846 asyw->image.w = fb->base.width;
847 asyw->image.h = fb->base.height;
848 asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
849 if (asyw->image.kind) {
850 asyw->image.layout = 0;
851 if (drm->device.info.chipset >= 0xc0)
852 asyw->image.block = fb->nvbo->tile_mode >> 4;
853 else
854 asyw->image.block = fb->nvbo->tile_mode;
855 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
856 } else {
857 asyw->image.layout = 1;
858 asyw->image.block = 0;
859 asyw->image.pitch = fb->base.pitches[0];
860 }
861
862 ret = wndw->func->acquire(wndw, asyw, asyh);
863 if (ret)
864 return ret;
865
866 if (asyw->set.image) {
867 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
868 asyw->image.interval = asyw->interval;
869 else
870 asyw->image.interval = 0;
871 }
872
873 return 0;
874 }
875
876 static int
877 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
878 {
879 struct nouveau_drm *drm = nouveau_drm(plane->dev);
880 struct nv50_wndw *wndw = nv50_wndw(plane);
881 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
882 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
883 struct nv50_head_atom *harm = NULL, *asyh = NULL;
884 bool varm = false, asyv = false, asym = false;
885 int ret;
886
887 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
888 if (asyw->state.crtc) {
889 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
890 if (IS_ERR(asyh))
891 return PTR_ERR(asyh);
892 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
893 asyv = asyh->state.active;
894 }
895
896 if (armw->state.crtc) {
897 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
898 if (IS_ERR(harm))
899 return PTR_ERR(harm);
900 varm = harm->state.crtc->state->active;
901 }
902
903 if (asyv) {
904 asyw->point.x = asyw->state.crtc_x;
905 asyw->point.y = asyw->state.crtc_y;
906 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
907 asyw->set.point = true;
908
909 if (!varm || asym || armw->state.fb != asyw->state.fb) {
910 ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
911 if (ret)
912 return ret;
913 }
914 } else
915 if (varm) {
916 nv50_wndw_atomic_check_release(wndw, asyw, harm);
917 } else {
918 return 0;
919 }
920
921 if (!asyv || asym) {
922 asyw->clr.ntfy = armw->ntfy.handle != 0;
923 asyw->clr.sema = armw->sema.handle != 0;
924 if (wndw->func->image_clr)
925 asyw->clr.image = armw->image.handle != 0;
926 asyw->set.lut = wndw->func->lut && asyv;
927 }
928
929 return 0;
930 }
931
932 static void
933 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
934 {
935 struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
936 struct nouveau_drm *drm = nouveau_drm(plane->dev);
937
938 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
939 if (!old_state->fb)
940 return;
941
942 nouveau_bo_unpin(fb->nvbo);
943 }
944
945 static int
946 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
947 {
948 struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
949 struct nouveau_drm *drm = nouveau_drm(plane->dev);
950 struct nv50_wndw *wndw = nv50_wndw(plane);
951 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
952 struct nv50_head_atom *asyh;
953 struct nv50_dmac_ctxdma *ctxdma;
954 int ret;
955
956 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
957 if (!asyw->state.fb)
958 return 0;
959
960 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
961 if (ret)
962 return ret;
963
964 ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
965 if (IS_ERR(ctxdma)) {
966 nouveau_bo_unpin(fb->nvbo);
967 return PTR_ERR(ctxdma);
968 }
969
970 asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
971 asyw->image.handle = ctxdma->object.handle;
972 asyw->image.offset = fb->nvbo->bo.offset;
973
974 if (wndw->func->prepare) {
975 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
976 if (IS_ERR(asyh))
977 return PTR_ERR(asyh);
978
979 wndw->func->prepare(wndw, asyh, asyw);
980 }
981
982 return 0;
983 }
984
985 static const struct drm_plane_helper_funcs
986 nv50_wndw_helper = {
987 .prepare_fb = nv50_wndw_prepare_fb,
988 .cleanup_fb = nv50_wndw_cleanup_fb,
989 .atomic_check = nv50_wndw_atomic_check,
990 };
991
992 static void
993 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
994 struct drm_plane_state *state)
995 {
996 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
997 __drm_atomic_helper_plane_destroy_state(&asyw->state);
998 dma_fence_put(asyw->state.fence);
999 kfree(asyw);
1000 }
1001
1002 static struct drm_plane_state *
1003 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1004 {
1005 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1006 struct nv50_wndw_atom *asyw;
1007 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1008 return NULL;
1009 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1010 asyw->state.fence = NULL;
1011 asyw->interval = 1;
1012 asyw->sema = armw->sema;
1013 asyw->ntfy = armw->ntfy;
1014 asyw->image = armw->image;
1015 asyw->point = armw->point;
1016 asyw->lut = armw->lut;
1017 asyw->clr.mask = 0;
1018 asyw->set.mask = 0;
1019 return &asyw->state;
1020 }
1021
1022 static void
1023 nv50_wndw_reset(struct drm_plane *plane)
1024 {
1025 struct nv50_wndw_atom *asyw;
1026
1027 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1028 return;
1029
1030 if (plane->state)
1031 plane->funcs->atomic_destroy_state(plane, plane->state);
1032 plane->state = &asyw->state;
1033 plane->state->plane = plane;
1034 plane->state->rotation = DRM_ROTATE_0;
1035 }
1036
1037 static void
1038 nv50_wndw_destroy(struct drm_plane *plane)
1039 {
1040 struct nv50_wndw *wndw = nv50_wndw(plane);
1041 void *data;
1042 nvif_notify_fini(&wndw->notify);
1043 data = wndw->func->dtor(wndw);
1044 drm_plane_cleanup(&wndw->plane);
1045 kfree(data);
1046 }
1047
1048 static const struct drm_plane_funcs
1049 nv50_wndw = {
1050 .update_plane = drm_atomic_helper_update_plane,
1051 .disable_plane = drm_atomic_helper_disable_plane,
1052 .destroy = nv50_wndw_destroy,
1053 .reset = nv50_wndw_reset,
1054 .set_property = drm_atomic_helper_plane_set_property,
1055 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1056 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1057 };
1058
1059 static void
1060 nv50_wndw_fini(struct nv50_wndw *wndw)
1061 {
1062 nvif_notify_put(&wndw->notify);
1063 }
1064
1065 static void
1066 nv50_wndw_init(struct nv50_wndw *wndw)
1067 {
1068 nvif_notify_get(&wndw->notify);
1069 }
1070
1071 static int
1072 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1073 enum drm_plane_type type, const char *name, int index,
1074 struct nv50_dmac *dmac, const u32 *format, int nformat,
1075 struct nv50_wndw *wndw)
1076 {
1077 int ret;
1078
1079 wndw->func = func;
1080 wndw->dmac = dmac;
1081
1082 ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format,
1083 nformat, type, "%s-%d", name, index);
1084 if (ret)
1085 return ret;
1086
1087 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1088 return 0;
1089 }
1090
1091 /******************************************************************************
1092 * Cursor plane
1093 *****************************************************************************/
1094 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1095
1096 struct nv50_curs {
1097 struct nv50_wndw wndw;
1098 struct nvif_object chan;
1099 };
1100
1101 static u32
1102 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1103 {
1104 struct nv50_curs *curs = nv50_curs(wndw);
1105 nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1106 return 0;
1107 }
1108
1109 static void
1110 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1111 {
1112 struct nv50_curs *curs = nv50_curs(wndw);
1113 nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1114 }
1115
1116 static void
1117 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1118 struct nv50_wndw_atom *asyw)
1119 {
1120 asyh->curs.handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1121 asyh->curs.offset = asyw->image.offset;
1122 asyh->set.curs = asyh->curs.visible;
1123 }
1124
1125 static void
1126 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1127 struct nv50_head_atom *asyh)
1128 {
1129 asyh->curs.visible = false;
1130 }
1131
1132 static int
1133 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1134 struct nv50_head_atom *asyh)
1135 {
1136 int ret;
1137
1138 ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1139 DRM_PLANE_HELPER_NO_SCALING,
1140 DRM_PLANE_HELPER_NO_SCALING,
1141 true, true);
1142 asyh->curs.visible = asyw->state.visible;
1143 if (ret || !asyh->curs.visible)
1144 return ret;
1145
1146 switch (asyw->state.fb->width) {
1147 case 32: asyh->curs.layout = 0; break;
1148 case 64: asyh->curs.layout = 1; break;
1149 default:
1150 return -EINVAL;
1151 }
1152
1153 if (asyw->state.fb->width != asyw->state.fb->height)
1154 return -EINVAL;
1155
1156 switch (asyw->state.fb->pixel_format) {
1157 case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1158 default:
1159 WARN_ON(1);
1160 return -EINVAL;
1161 }
1162
1163 return 0;
1164 }
1165
1166 static void *
1167 nv50_curs_dtor(struct nv50_wndw *wndw)
1168 {
1169 struct nv50_curs *curs = nv50_curs(wndw);
1170 nvif_object_fini(&curs->chan);
1171 return curs;
1172 }
1173
1174 static const u32
1175 nv50_curs_format[] = {
1176 DRM_FORMAT_ARGB8888,
1177 };
1178
1179 static const struct nv50_wndw_func
1180 nv50_curs = {
1181 .dtor = nv50_curs_dtor,
1182 .acquire = nv50_curs_acquire,
1183 .release = nv50_curs_release,
1184 .prepare = nv50_curs_prepare,
1185 .point = nv50_curs_point,
1186 .update = nv50_curs_update,
1187 };
1188
1189 static int
1190 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1191 struct nv50_curs **pcurs)
1192 {
1193 static const struct nvif_mclass curses[] = {
1194 { GK104_DISP_CURSOR, 0 },
1195 { GF110_DISP_CURSOR, 0 },
1196 { GT214_DISP_CURSOR, 0 },
1197 { G82_DISP_CURSOR, 0 },
1198 { NV50_DISP_CURSOR, 0 },
1199 {}
1200 };
1201 struct nv50_disp_cursor_v0 args = {
1202 .head = head->base.index,
1203 };
1204 struct nv50_disp *disp = nv50_disp(drm->dev);
1205 struct nv50_curs *curs;
1206 int cid, ret;
1207
1208 cid = nvif_mclass(disp->disp, curses);
1209 if (cid < 0) {
1210 NV_ERROR(drm, "No supported cursor immediate class\n");
1211 return cid;
1212 }
1213
1214 if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1215 return -ENOMEM;
1216
1217 ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1218 "curs", head->base.index, &disp->mast.base,
1219 nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1220 &curs->wndw);
1221 if (ret) {
1222 kfree(curs);
1223 return ret;
1224 }
1225
1226 ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1227 sizeof(args), &curs->chan);
1228 if (ret) {
1229 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1230 curses[cid].oclass, ret);
1231 return ret;
1232 }
1233
1234 return 0;
1235 }
1236
1237 /******************************************************************************
1238 * Primary plane
1239 *****************************************************************************/
1240 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1241
1242 struct nv50_base {
1243 struct nv50_wndw wndw;
1244 struct nv50_sync chan;
1245 int id;
1246 };
1247
1248 static int
1249 nv50_base_notify(struct nvif_notify *notify)
1250 {
1251 return NVIF_NOTIFY_KEEP;
1252 }
1253
1254 static void
1255 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1256 {
1257 struct nv50_base *base = nv50_base(wndw);
1258 u32 *push;
1259 if ((push = evo_wait(&base->chan, 2))) {
1260 evo_mthd(push, 0x00e0, 1);
1261 evo_data(push, asyw->lut.enable << 30);
1262 evo_kick(push, &base->chan);
1263 }
1264 }
1265
1266 static void
1267 nv50_base_image_clr(struct nv50_wndw *wndw)
1268 {
1269 struct nv50_base *base = nv50_base(wndw);
1270 u32 *push;
1271 if ((push = evo_wait(&base->chan, 4))) {
1272 evo_mthd(push, 0x0084, 1);
1273 evo_data(push, 0x00000000);
1274 evo_mthd(push, 0x00c0, 1);
1275 evo_data(push, 0x00000000);
1276 evo_kick(push, &base->chan);
1277 }
1278 }
1279
1280 static void
1281 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1282 {
1283 struct nv50_base *base = nv50_base(wndw);
1284 const s32 oclass = base->chan.base.base.user.oclass;
1285 u32 *push;
1286 if ((push = evo_wait(&base->chan, 10))) {
1287 evo_mthd(push, 0x0084, 1);
1288 evo_data(push, (asyw->image.mode << 8) |
1289 (asyw->image.interval << 4));
1290 evo_mthd(push, 0x00c0, 1);
1291 evo_data(push, asyw->image.handle);
1292 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1293 evo_mthd(push, 0x0800, 5);
1294 evo_data(push, asyw->image.offset >> 8);
1295 evo_data(push, 0x00000000);
1296 evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1297 evo_data(push, (asyw->image.layout << 20) |
1298 asyw->image.pitch |
1299 asyw->image.block);
1300 evo_data(push, (asyw->image.kind << 16) |
1301 (asyw->image.format << 8));
1302 } else
1303 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1304 evo_mthd(push, 0x0800, 5);
1305 evo_data(push, asyw->image.offset >> 8);
1306 evo_data(push, 0x00000000);
1307 evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1308 evo_data(push, (asyw->image.layout << 20) |
1309 asyw->image.pitch |
1310 asyw->image.block);
1311 evo_data(push, asyw->image.format << 8);
1312 } else {
1313 evo_mthd(push, 0x0400, 5);
1314 evo_data(push, asyw->image.offset >> 8);
1315 evo_data(push, 0x00000000);
1316 evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1317 evo_data(push, (asyw->image.layout << 24) |
1318 asyw->image.pitch |
1319 asyw->image.block);
1320 evo_data(push, asyw->image.format << 8);
1321 }
1322 evo_kick(push, &base->chan);
1323 }
1324 }
1325
1326 static void
1327 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1328 {
1329 struct nv50_base *base = nv50_base(wndw);
1330 u32 *push;
1331 if ((push = evo_wait(&base->chan, 2))) {
1332 evo_mthd(push, 0x00a4, 1);
1333 evo_data(push, 0x00000000);
1334 evo_kick(push, &base->chan);
1335 }
1336 }
1337
1338 static void
1339 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1340 {
1341 struct nv50_base *base = nv50_base(wndw);
1342 u32 *push;
1343 if ((push = evo_wait(&base->chan, 3))) {
1344 evo_mthd(push, 0x00a0, 2);
1345 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1346 evo_data(push, asyw->ntfy.handle);
1347 evo_kick(push, &base->chan);
1348 }
1349 }
1350
1351 static void
1352 nv50_base_sema_clr(struct nv50_wndw *wndw)
1353 {
1354 struct nv50_base *base = nv50_base(wndw);
1355 u32 *push;
1356 if ((push = evo_wait(&base->chan, 2))) {
1357 evo_mthd(push, 0x0094, 1);
1358 evo_data(push, 0x00000000);
1359 evo_kick(push, &base->chan);
1360 }
1361 }
1362
1363 static void
1364 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1365 {
1366 struct nv50_base *base = nv50_base(wndw);
1367 u32 *push;
1368 if ((push = evo_wait(&base->chan, 5))) {
1369 evo_mthd(push, 0x0088, 4);
1370 evo_data(push, asyw->sema.offset);
1371 evo_data(push, asyw->sema.acquire);
1372 evo_data(push, asyw->sema.release);
1373 evo_data(push, asyw->sema.handle);
1374 evo_kick(push, &base->chan);
1375 }
1376 }
1377
1378 static u32
1379 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1380 {
1381 struct nv50_base *base = nv50_base(wndw);
1382 u32 *push;
1383
1384 if (!(push = evo_wait(&base->chan, 2)))
1385 return 0;
1386 evo_mthd(push, 0x0080, 1);
1387 evo_data(push, interlock);
1388 evo_kick(push, &base->chan);
1389
1390 if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1391 return interlock ? 2 << (base->id * 8) : 0;
1392 return interlock ? 2 << (base->id * 4) : 0;
1393 }
1394
1395 static int
1396 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1397 {
1398 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1399 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1400 if (nvif_msec(&drm->device, 2000ULL,
1401 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1402 if ((data & 0xc0000000) == 0x40000000)
1403 break;
1404 usleep_range(1, 2);
1405 ) < 0)
1406 return -ETIMEDOUT;
1407 return 0;
1408 }
1409
1410 static void
1411 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1412 struct nv50_head_atom *asyh)
1413 {
1414 asyh->base.cpp = 0;
1415 }
1416
1417 static int
1418 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1419 struct nv50_head_atom *asyh)
1420 {
1421 const u32 format = asyw->state.fb->pixel_format;
1422 const struct drm_format_info *info;
1423 int ret;
1424
1425 info = drm_format_info(format);
1426 if (!info || !info->depth)
1427 return -EINVAL;
1428
1429 ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1430 DRM_PLANE_HELPER_NO_SCALING,
1431 DRM_PLANE_HELPER_NO_SCALING,
1432 false, true);
1433 if (ret)
1434 return ret;
1435
1436 asyh->base.depth = info->depth;
1437 asyh->base.cpp = info->cpp[0];
1438 asyh->base.x = asyw->state.src.x1 >> 16;
1439 asyh->base.y = asyw->state.src.y1 >> 16;
1440 asyh->base.w = asyw->state.fb->width;
1441 asyh->base.h = asyw->state.fb->height;
1442
1443 switch (format) {
1444 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
1445 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
1446 case DRM_FORMAT_XRGB1555 :
1447 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
1448 case DRM_FORMAT_XRGB8888 :
1449 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
1450 case DRM_FORMAT_XBGR2101010:
1451 case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1452 case DRM_FORMAT_XBGR8888 :
1453 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
1454 default:
1455 WARN_ON(1);
1456 return -EINVAL;
1457 }
1458
1459 asyw->lut.enable = 1;
1460 asyw->set.image = true;
1461 return 0;
1462 }
1463
1464 static void *
1465 nv50_base_dtor(struct nv50_wndw *wndw)
1466 {
1467 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1468 struct nv50_base *base = nv50_base(wndw);
1469 nv50_dmac_destroy(&base->chan.base, disp->disp);
1470 return base;
1471 }
1472
1473 static const u32
1474 nv50_base_format[] = {
1475 DRM_FORMAT_C8,
1476 DRM_FORMAT_RGB565,
1477 DRM_FORMAT_XRGB1555,
1478 DRM_FORMAT_ARGB1555,
1479 DRM_FORMAT_XRGB8888,
1480 DRM_FORMAT_ARGB8888,
1481 DRM_FORMAT_XBGR2101010,
1482 DRM_FORMAT_ABGR2101010,
1483 DRM_FORMAT_XBGR8888,
1484 DRM_FORMAT_ABGR8888,
1485 };
1486
1487 static const struct nv50_wndw_func
1488 nv50_base = {
1489 .dtor = nv50_base_dtor,
1490 .acquire = nv50_base_acquire,
1491 .release = nv50_base_release,
1492 .sema_set = nv50_base_sema_set,
1493 .sema_clr = nv50_base_sema_clr,
1494 .ntfy_set = nv50_base_ntfy_set,
1495 .ntfy_clr = nv50_base_ntfy_clr,
1496 .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1497 .image_set = nv50_base_image_set,
1498 .image_clr = nv50_base_image_clr,
1499 .lut = nv50_base_lut,
1500 .update = nv50_base_update,
1501 };
1502
1503 static int
1504 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1505 struct nv50_base **pbase)
1506 {
1507 struct nv50_disp *disp = nv50_disp(drm->dev);
1508 struct nv50_base *base;
1509 int ret;
1510
1511 if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1512 return -ENOMEM;
1513 base->id = head->base.index;
1514 base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1515 base->wndw.sema = EVO_FLIP_SEM0(base->id);
1516 base->wndw.data = 0x00000000;
1517
1518 ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1519 "base", base->id, &base->chan.base,
1520 nv50_base_format, ARRAY_SIZE(nv50_base_format),
1521 &base->wndw);
1522 if (ret) {
1523 kfree(base);
1524 return ret;
1525 }
1526
1527 ret = nv50_base_create(&drm->device, disp->disp, base->id,
1528 disp->sync->bo.offset, &base->chan);
1529 if (ret)
1530 return ret;
1531
1532 return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1533 false,
1534 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1535 &(struct nvif_notify_uevent_req) {},
1536 sizeof(struct nvif_notify_uevent_req),
1537 sizeof(struct nvif_notify_uevent_rep),
1538 &base->wndw.notify);
1539 }
1540
1541 /******************************************************************************
1542 * Head
1543 *****************************************************************************/
1544 static void
1545 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1546 {
1547 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1548 u32 *push;
1549 if ((push = evo_wait(core, 2))) {
1550 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1551 evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1552 else
1553 evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1554 evo_data(push, (asyh->procamp.sat.sin << 20) |
1555 (asyh->procamp.sat.cos << 8));
1556 evo_kick(push, core);
1557 }
1558 }
1559
1560 static void
1561 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1562 {
1563 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1564 u32 *push;
1565 if ((push = evo_wait(core, 2))) {
1566 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1567 evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1568 else
1569 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1570 evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1571 else
1572 evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1573 evo_data(push, (asyh->dither.mode << 3) |
1574 (asyh->dither.bits << 1) |
1575 asyh->dither.enable);
1576 evo_kick(push, core);
1577 }
1578 }
1579
1580 static void
1581 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1582 {
1583 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1584 u32 bounds = 0;
1585 u32 *push;
1586
1587 if (asyh->base.cpp) {
1588 switch (asyh->base.cpp) {
1589 case 8: bounds |= 0x00000500; break;
1590 case 4: bounds |= 0x00000300; break;
1591 case 2: bounds |= 0x00000100; break;
1592 default:
1593 WARN_ON(1);
1594 break;
1595 }
1596 bounds |= 0x00000001;
1597 }
1598
1599 if ((push = evo_wait(core, 2))) {
1600 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1601 evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1602 else
1603 evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1604 evo_data(push, bounds);
1605 evo_kick(push, core);
1606 }
1607 }
1608
1609 static void
1610 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1611 {
1612 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1613 u32 bounds = 0;
1614 u32 *push;
1615
1616 if (asyh->base.cpp) {
1617 switch (asyh->base.cpp) {
1618 case 8: bounds |= 0x00000500; break;
1619 case 4: bounds |= 0x00000300; break;
1620 case 2: bounds |= 0x00000100; break;
1621 case 1: bounds |= 0x00000000; break;
1622 default:
1623 WARN_ON(1);
1624 break;
1625 }
1626 bounds |= 0x00000001;
1627 }
1628
1629 if ((push = evo_wait(core, 2))) {
1630 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1631 evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1632 else
1633 evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1634 evo_data(push, bounds);
1635 evo_kick(push, core);
1636 }
1637 }
1638
1639 static void
1640 nv50_head_curs_clr(struct nv50_head *head)
1641 {
1642 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1643 u32 *push;
1644 if ((push = evo_wait(core, 4))) {
1645 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1646 evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1647 evo_data(push, 0x05000000);
1648 } else
1649 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1650 evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1651 evo_data(push, 0x05000000);
1652 evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1653 evo_data(push, 0x00000000);
1654 } else {
1655 evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1656 evo_data(push, 0x05000000);
1657 evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1658 evo_data(push, 0x00000000);
1659 }
1660 evo_kick(push, core);
1661 }
1662 }
1663
1664 static void
1665 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1666 {
1667 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1668 u32 *push;
1669 if ((push = evo_wait(core, 5))) {
1670 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1671 evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1672 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1673 (asyh->curs.format << 24));
1674 evo_data(push, asyh->curs.offset >> 8);
1675 } else
1676 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1677 evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1678 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1679 (asyh->curs.format << 24));
1680 evo_data(push, asyh->curs.offset >> 8);
1681 evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1682 evo_data(push, asyh->curs.handle);
1683 } else {
1684 evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1685 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1686 (asyh->curs.format << 24));
1687 evo_data(push, asyh->curs.offset >> 8);
1688 evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1689 evo_data(push, asyh->curs.handle);
1690 }
1691 evo_kick(push, core);
1692 }
1693 }
1694
1695 static void
1696 nv50_head_core_clr(struct nv50_head *head)
1697 {
1698 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1699 u32 *push;
1700 if ((push = evo_wait(core, 2))) {
1701 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1702 evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1703 else
1704 evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1705 evo_data(push, 0x00000000);
1706 evo_kick(push, core);
1707 }
1708 }
1709
1710 static void
1711 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1712 {
1713 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1714 u32 *push;
1715 if ((push = evo_wait(core, 9))) {
1716 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1717 evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1718 evo_data(push, asyh->core.offset >> 8);
1719 evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1720 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1721 evo_data(push, asyh->core.layout << 20 |
1722 (asyh->core.pitch >> 8) << 8 |
1723 asyh->core.block);
1724 evo_data(push, asyh->core.kind << 16 |
1725 asyh->core.format << 8);
1726 evo_data(push, asyh->core.handle);
1727 evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1728 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1729 } else
1730 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1731 evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1732 evo_data(push, asyh->core.offset >> 8);
1733 evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1734 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1735 evo_data(push, asyh->core.layout << 20 |
1736 (asyh->core.pitch >> 8) << 8 |
1737 asyh->core.block);
1738 evo_data(push, asyh->core.format << 8);
1739 evo_data(push, asyh->core.handle);
1740 evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1741 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1742 } else {
1743 evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1744 evo_data(push, asyh->core.offset >> 8);
1745 evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1746 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1747 evo_data(push, asyh->core.layout << 24 |
1748 (asyh->core.pitch >> 8) << 8 |
1749 asyh->core.block);
1750 evo_data(push, asyh->core.format << 8);
1751 evo_data(push, asyh->core.handle);
1752 evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1753 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1754 }
1755 evo_kick(push, core);
1756 }
1757 }
1758
1759 static void
1760 nv50_head_lut_clr(struct nv50_head *head)
1761 {
1762 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1763 u32 *push;
1764 if ((push = evo_wait(core, 4))) {
1765 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1766 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1767 evo_data(push, 0x40000000);
1768 } else
1769 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1770 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1771 evo_data(push, 0x40000000);
1772 evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1773 evo_data(push, 0x00000000);
1774 } else {
1775 evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1776 evo_data(push, 0x03000000);
1777 evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1778 evo_data(push, 0x00000000);
1779 }
1780 evo_kick(push, core);
1781 }
1782 }
1783
1784 static void
1785 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1786 {
1787 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1788 u32 *push;
1789 if ((push = evo_wait(core, 7))) {
1790 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1791 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1792 evo_data(push, 0xc0000000);
1793 evo_data(push, asyh->lut.offset >> 8);
1794 } else
1795 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1796 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1797 evo_data(push, 0xc0000000);
1798 evo_data(push, asyh->lut.offset >> 8);
1799 evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1800 evo_data(push, asyh->lut.handle);
1801 } else {
1802 evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1803 evo_data(push, 0x83000000);
1804 evo_data(push, asyh->lut.offset >> 8);
1805 evo_data(push, 0x00000000);
1806 evo_data(push, 0x00000000);
1807 evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1808 evo_data(push, asyh->lut.handle);
1809 }
1810 evo_kick(push, core);
1811 }
1812 }
1813
1814 static void
1815 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1816 {
1817 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1818 struct nv50_head_mode *m = &asyh->mode;
1819 u32 *push;
1820 if ((push = evo_wait(core, 14))) {
1821 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1822 evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1823 evo_data(push, 0x00800000 | m->clock);
1824 evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1825 evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1826 evo_data(push, 0x00000000);
1827 evo_data(push, (m->v.active << 16) | m->h.active );
1828 evo_data(push, (m->v.synce << 16) | m->h.synce );
1829 evo_data(push, (m->v.blanke << 16) | m->h.blanke );
1830 evo_data(push, (m->v.blanks << 16) | m->h.blanks );
1831 evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1832 evo_data(push, asyh->mode.v.blankus);
1833 evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1834 evo_data(push, 0x00000000);
1835 } else {
1836 evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1837 evo_data(push, 0x00000000);
1838 evo_data(push, (m->v.active << 16) | m->h.active );
1839 evo_data(push, (m->v.synce << 16) | m->h.synce );
1840 evo_data(push, (m->v.blanke << 16) | m->h.blanke );
1841 evo_data(push, (m->v.blanks << 16) | m->h.blanks );
1842 evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1843 evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1844 evo_data(push, 0x00000000); /* ??? */
1845 evo_data(push, 0xffffff00);
1846 evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1847 evo_data(push, m->clock * 1000);
1848 evo_data(push, 0x00200000); /* ??? */
1849 evo_data(push, m->clock * 1000);
1850 }
1851 evo_kick(push, core);
1852 }
1853 }
1854
1855 static void
1856 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1857 {
1858 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1859 u32 *push;
1860 if ((push = evo_wait(core, 10))) {
1861 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1862 evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1863 evo_data(push, 0x00000000);
1864 evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1865 evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1866 evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1867 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1868 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1869 } else {
1870 evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1871 evo_data(push, 0x00000000);
1872 evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1873 evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1874 evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1875 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1876 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1877 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1878 }
1879 evo_kick(push, core);
1880 }
1881 }
1882
1883 static void
1884 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1885 {
1886 if (asyh->clr.core && (!asyh->set.core || y))
1887 nv50_head_lut_clr(head);
1888 if (asyh->clr.core && (!asyh->set.core || y))
1889 nv50_head_core_clr(head);
1890 if (asyh->clr.curs && (!asyh->set.curs || y))
1891 nv50_head_curs_clr(head);
1892 }
1893
1894 static void
1895 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1896 {
1897 if (asyh->set.view ) nv50_head_view (head, asyh);
1898 if (asyh->set.mode ) nv50_head_mode (head, asyh);
1899 if (asyh->set.core ) nv50_head_lut_set (head, asyh);
1900 if (asyh->set.core ) nv50_head_core_set(head, asyh);
1901 if (asyh->set.curs ) nv50_head_curs_set(head, asyh);
1902 if (asyh->set.base ) nv50_head_base (head, asyh);
1903 if (asyh->set.ovly ) nv50_head_ovly (head, asyh);
1904 if (asyh->set.dither ) nv50_head_dither (head, asyh);
1905 if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1906 }
1907
1908 static void
1909 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1910 struct nv50_head_atom *asyh,
1911 struct nouveau_conn_atom *asyc)
1912 {
1913 const int vib = asyc->procamp.color_vibrance - 100;
1914 const int hue = asyc->procamp.vibrant_hue - 90;
1915 const int adj = (vib > 0) ? 50 : 0;
1916 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1917 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1918 asyh->set.procamp = true;
1919 }
1920
1921 static void
1922 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1923 struct nv50_head_atom *asyh,
1924 struct nouveau_conn_atom *asyc)
1925 {
1926 struct drm_connector *connector = asyc->state.connector;
1927 u32 mode = 0x00;
1928
1929 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1930 if (asyh->base.depth > connector->display_info.bpc * 3)
1931 mode = DITHERING_MODE_DYNAMIC2X2;
1932 } else {
1933 mode = asyc->dither.mode;
1934 }
1935
1936 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
1937 if (connector->display_info.bpc >= 8)
1938 mode |= DITHERING_DEPTH_8BPC;
1939 } else {
1940 mode |= asyc->dither.depth;
1941 }
1942
1943 asyh->dither.enable = mode;
1944 asyh->dither.bits = mode >> 1;
1945 asyh->dither.mode = mode >> 3;
1946 asyh->set.dither = true;
1947 }
1948
1949 static void
1950 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1951 struct nv50_head_atom *asyh,
1952 struct nouveau_conn_atom *asyc)
1953 {
1954 struct drm_connector *connector = asyc->state.connector;
1955 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1956 struct drm_display_mode *umode = &asyh->state.mode;
1957 int mode = asyc->scaler.mode;
1958 struct edid *edid;
1959
1960 if (connector->edid_blob_ptr)
1961 edid = (struct edid *)connector->edid_blob_ptr->data;
1962 else
1963 edid = NULL;
1964
1965 if (!asyc->scaler.full) {
1966 if (mode == DRM_MODE_SCALE_NONE)
1967 omode = umode;
1968 } else {
1969 /* Non-EDID LVDS/eDP mode. */
1970 mode = DRM_MODE_SCALE_FULLSCREEN;
1971 }
1972
1973 asyh->view.iW = umode->hdisplay;
1974 asyh->view.iH = umode->vdisplay;
1975 asyh->view.oW = omode->hdisplay;
1976 asyh->view.oH = omode->vdisplay;
1977 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
1978 asyh->view.oH *= 2;
1979
1980 /* Add overscan compensation if necessary, will keep the aspect
1981 * ratio the same as the backend mode unless overridden by the
1982 * user setting both hborder and vborder properties.
1983 */
1984 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
1985 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
1986 drm_detect_hdmi_monitor(edid)))) {
1987 u32 bX = asyc->scaler.underscan.hborder;
1988 u32 bY = asyc->scaler.underscan.vborder;
1989 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
1990
1991 if (bX) {
1992 asyh->view.oW -= (bX * 2);
1993 if (bY) asyh->view.oH -= (bY * 2);
1994 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
1995 } else {
1996 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
1997 if (bY) asyh->view.oH -= (bY * 2);
1998 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
1999 }
2000 }
2001
2002 /* Handle CENTER/ASPECT scaling, taking into account the areas
2003 * removed already for overscan compensation.
2004 */
2005 switch (mode) {
2006 case DRM_MODE_SCALE_CENTER:
2007 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2008 asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH);
2009 /* fall-through */
2010 case DRM_MODE_SCALE_ASPECT:
2011 if (asyh->view.oH < asyh->view.oW) {
2012 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2013 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2014 } else {
2015 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2016 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2017 }
2018 break;
2019 default:
2020 break;
2021 }
2022
2023 asyh->set.view = true;
2024 }
2025
2026 static void
2027 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2028 {
2029 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2030 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
2031 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
2032 u32 hbackp = mode->htotal - mode->hsync_end;
2033 u32 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
2034 u32 hfrontp = mode->hsync_start - mode->hdisplay;
2035 u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
2036 struct nv50_head_mode *m = &asyh->mode;
2037
2038 m->h.active = mode->htotal;
2039 m->h.synce = mode->hsync_end - mode->hsync_start - 1;
2040 m->h.blanke = m->h.synce + hbackp;
2041 m->h.blanks = mode->htotal - hfrontp - 1;
2042
2043 m->v.active = mode->vtotal * vscan / ilace;
2044 m->v.synce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
2045 m->v.blanke = m->v.synce + vbackp;
2046 m->v.blanks = m->v.active - vfrontp - 1;
2047
2048 /*XXX: Safe underestimate, even "0" works */
2049 m->v.blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
2050 m->v.blankus *= 1000;
2051 m->v.blankus /= mode->clock;
2052
2053 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2054 m->v.blank2e = m->v.active + m->v.synce + vbackp;
2055 m->v.blank2s = m->v.blank2e + (mode->vdisplay * vscan / ilace);
2056 m->v.active = (m->v.active * 2) + 1;
2057 m->interlace = true;
2058 } else {
2059 m->v.blank2e = 0;
2060 m->v.blank2s = 1;
2061 m->interlace = false;
2062 }
2063 m->clock = mode->clock;
2064
2065 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
2066 asyh->set.mode = true;
2067 }
2068
2069 static int
2070 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2071 {
2072 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2073 struct nv50_disp *disp = nv50_disp(crtc->dev);
2074 struct nv50_head *head = nv50_head(crtc);
2075 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2076 struct nv50_head_atom *asyh = nv50_head_atom(state);
2077 struct nouveau_conn_atom *asyc = NULL;
2078 struct drm_connector_state *conns;
2079 struct drm_connector *conn;
2080 int i;
2081
2082 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2083 if (asyh->state.active) {
2084 for_each_connector_in_state(asyh->state.state, conn, conns, i) {
2085 if (conns->crtc == crtc) {
2086 asyc = nouveau_conn_atom(conns);
2087 break;
2088 }
2089 }
2090
2091 if (armh->state.active) {
2092 if (asyc) {
2093 if (asyh->state.mode_changed)
2094 asyc->set.scaler = true;
2095 if (armh->base.depth != asyh->base.depth)
2096 asyc->set.dither = true;
2097 }
2098 } else {
2099 asyc->set.mask = ~0;
2100 asyh->set.mask = ~0;
2101 }
2102
2103 if (asyh->state.mode_changed)
2104 nv50_head_atomic_check_mode(head, asyh);
2105
2106 if (asyc) {
2107 if (asyc->set.scaler)
2108 nv50_head_atomic_check_view(armh, asyh, asyc);
2109 if (asyc->set.dither)
2110 nv50_head_atomic_check_dither(armh, asyh, asyc);
2111 if (asyc->set.procamp)
2112 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2113 }
2114
2115 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2116 asyh->core.x = asyh->base.x;
2117 asyh->core.y = asyh->base.y;
2118 asyh->core.w = asyh->base.w;
2119 asyh->core.h = asyh->base.h;
2120 } else
2121 if ((asyh->core.visible = asyh->curs.visible)) {
2122 /*XXX: We need to either find some way of having the
2123 * primary base layer appear black, while still
2124 * being able to display the other layers, or we
2125 * need to allocate a dummy black surface here.
2126 */
2127 asyh->core.x = 0;
2128 asyh->core.y = 0;
2129 asyh->core.w = asyh->state.mode.hdisplay;
2130 asyh->core.h = asyh->state.mode.vdisplay;
2131 }
2132 asyh->core.handle = disp->mast.base.vram.handle;
2133 asyh->core.offset = 0;
2134 asyh->core.format = 0xcf;
2135 asyh->core.kind = 0;
2136 asyh->core.layout = 1;
2137 asyh->core.block = 0;
2138 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2139 asyh->lut.handle = disp->mast.base.vram.handle;
2140 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
2141 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2142 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2143 } else {
2144 asyh->core.visible = false;
2145 asyh->curs.visible = false;
2146 asyh->base.cpp = 0;
2147 asyh->ovly.cpp = 0;
2148 }
2149
2150 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2151 if (asyh->core.visible) {
2152 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2153 asyh->set.core = true;
2154 } else
2155 if (armh->core.visible) {
2156 asyh->clr.core = true;
2157 }
2158
2159 if (asyh->curs.visible) {
2160 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2161 asyh->set.curs = true;
2162 } else
2163 if (armh->curs.visible) {
2164 asyh->clr.curs = true;
2165 }
2166 } else {
2167 asyh->clr.core = armh->core.visible;
2168 asyh->clr.curs = armh->curs.visible;
2169 asyh->set.core = asyh->core.visible;
2170 asyh->set.curs = asyh->curs.visible;
2171 }
2172
2173 if (asyh->clr.mask || asyh->set.mask)
2174 nv50_atom(asyh->state.state)->lock_core = true;
2175 return 0;
2176 }
2177
2178 static void
2179 nv50_head_lut_load(struct drm_crtc *crtc)
2180 {
2181 struct nv50_disp *disp = nv50_disp(crtc->dev);
2182 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2183 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
2184 int i;
2185
2186 for (i = 0; i < 256; i++) {
2187 u16 r = nv_crtc->lut.r[i] >> 2;
2188 u16 g = nv_crtc->lut.g[i] >> 2;
2189 u16 b = nv_crtc->lut.b[i] >> 2;
2190
2191 if (disp->disp->oclass < GF110_DISP) {
2192 writew(r + 0x0000, lut + (i * 0x08) + 0);
2193 writew(g + 0x0000, lut + (i * 0x08) + 2);
2194 writew(b + 0x0000, lut + (i * 0x08) + 4);
2195 } else {
2196 writew(r + 0x6000, lut + (i * 0x20) + 0);
2197 writew(g + 0x6000, lut + (i * 0x20) + 2);
2198 writew(b + 0x6000, lut + (i * 0x20) + 4);
2199 }
2200 }
2201 }
2202
2203 static int
2204 nv50_head_mode_set_base_atomic(struct drm_crtc *crtc,
2205 struct drm_framebuffer *fb, int x, int y,
2206 enum mode_set_atomic state)
2207 {
2208 WARN_ON(1);
2209 return 0;
2210 }
2211
2212 static const struct drm_crtc_helper_funcs
2213 nv50_head_help = {
2214 .mode_set_base_atomic = nv50_head_mode_set_base_atomic,
2215 .load_lut = nv50_head_lut_load,
2216 .atomic_check = nv50_head_atomic_check,
2217 };
2218
2219 /* This is identical to the version in the atomic helpers, except that
2220 * it supports non-vblanked ("async") page flips.
2221 */
2222 static int
2223 nv50_head_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 struct drm_pending_vblank_event *event, u32 flags)
2225 {
2226 struct drm_plane *plane = crtc->primary;
2227 struct drm_atomic_state *state;
2228 struct drm_plane_state *plane_state;
2229 struct drm_crtc_state *crtc_state;
2230 int ret = 0;
2231
2232 state = drm_atomic_state_alloc(plane->dev);
2233 if (!state)
2234 return -ENOMEM;
2235
2236 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
2237 retry:
2238 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2239 if (IS_ERR(crtc_state)) {
2240 ret = PTR_ERR(crtc_state);
2241 goto fail;
2242 }
2243 crtc_state->event = event;
2244
2245 plane_state = drm_atomic_get_plane_state(state, plane);
2246 if (IS_ERR(plane_state)) {
2247 ret = PTR_ERR(plane_state);
2248 goto fail;
2249 }
2250
2251 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
2252 if (ret != 0)
2253 goto fail;
2254 drm_atomic_set_fb_for_plane(plane_state, fb);
2255
2256 /* Make sure we don't accidentally do a full modeset. */
2257 state->allow_modeset = false;
2258 if (!crtc_state->active) {
2259 DRM_DEBUG_ATOMIC("[CRTC:%d] disabled, rejecting legacy flip\n",
2260 crtc->base.id);
2261 ret = -EINVAL;
2262 goto fail;
2263 }
2264
2265 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
2266 nv50_wndw_atom(plane_state)->interval = 0;
2267
2268 ret = drm_atomic_nonblocking_commit(state);
2269 fail:
2270 if (ret == -EDEADLK)
2271 goto backoff;
2272
2273 drm_atomic_state_put(state);
2274 return ret;
2275
2276 backoff:
2277 drm_atomic_state_clear(state);
2278 drm_atomic_legacy_backoff(state);
2279
2280 /*
2281 * Someone might have exchanged the framebuffer while we dropped locks
2282 * in the backoff code. We need to fix up the fb refcount tracking the
2283 * core does for us.
2284 */
2285 plane->old_fb = plane->fb;
2286
2287 goto retry;
2288 }
2289
2290 static int
2291 nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
2292 uint32_t size)
2293 {
2294 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2295 u32 i;
2296
2297 for (i = 0; i < size; i++) {
2298 nv_crtc->lut.r[i] = r[i];
2299 nv_crtc->lut.g[i] = g[i];
2300 nv_crtc->lut.b[i] = b[i];
2301 }
2302
2303 nv50_head_lut_load(crtc);
2304 return 0;
2305 }
2306
2307 static void
2308 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2309 struct drm_crtc_state *state)
2310 {
2311 struct nv50_head_atom *asyh = nv50_head_atom(state);
2312 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2313 kfree(asyh);
2314 }
2315
2316 static struct drm_crtc_state *
2317 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2318 {
2319 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2320 struct nv50_head_atom *asyh;
2321 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2322 return NULL;
2323 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2324 asyh->view = armh->view;
2325 asyh->mode = armh->mode;
2326 asyh->lut = armh->lut;
2327 asyh->core = armh->core;
2328 asyh->curs = armh->curs;
2329 asyh->base = armh->base;
2330 asyh->ovly = armh->ovly;
2331 asyh->dither = armh->dither;
2332 asyh->procamp = armh->procamp;
2333 asyh->clr.mask = 0;
2334 asyh->set.mask = 0;
2335 return &asyh->state;
2336 }
2337
2338 static void
2339 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2340 struct drm_crtc_state *state)
2341 {
2342 if (crtc->state)
2343 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2344 crtc->state = state;
2345 crtc->state->crtc = crtc;
2346 }
2347
2348 static void
2349 nv50_head_reset(struct drm_crtc *crtc)
2350 {
2351 struct nv50_head_atom *asyh;
2352
2353 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2354 return;
2355
2356 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2357 }
2358
2359 static void
2360 nv50_head_destroy(struct drm_crtc *crtc)
2361 {
2362 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2363 struct nv50_disp *disp = nv50_disp(crtc->dev);
2364 struct nv50_head *head = nv50_head(crtc);
2365
2366 nv50_dmac_destroy(&head->ovly.base, disp->disp);
2367 nv50_pioc_destroy(&head->oimm.base);
2368
2369 nouveau_bo_unmap(nv_crtc->lut.nvbo);
2370 if (nv_crtc->lut.nvbo)
2371 nouveau_bo_unpin(nv_crtc->lut.nvbo);
2372 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
2373
2374 drm_crtc_cleanup(crtc);
2375 kfree(crtc);
2376 }
2377
2378 static const struct drm_crtc_funcs
2379 nv50_head_func = {
2380 .reset = nv50_head_reset,
2381 .gamma_set = nv50_head_gamma_set,
2382 .destroy = nv50_head_destroy,
2383 .set_config = drm_atomic_helper_set_config,
2384 .page_flip = nv50_head_page_flip,
2385 .set_property = drm_atomic_helper_crtc_set_property,
2386 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2387 .atomic_destroy_state = nv50_head_atomic_destroy_state,
2388 };
2389
2390 static int
2391 nv50_head_create(struct drm_device *dev, int index)
2392 {
2393 struct nouveau_drm *drm = nouveau_drm(dev);
2394 struct nvif_device *device = &drm->device;
2395 struct nv50_disp *disp = nv50_disp(dev);
2396 struct nv50_head *head;
2397 struct nv50_base *base;
2398 struct nv50_curs *curs;
2399 struct drm_crtc *crtc;
2400 int ret, i;
2401
2402 head = kzalloc(sizeof(*head), GFP_KERNEL);
2403 if (!head)
2404 return -ENOMEM;
2405
2406 head->base.index = index;
2407 for (i = 0; i < 256; i++) {
2408 head->base.lut.r[i] = i << 8;
2409 head->base.lut.g[i] = i << 8;
2410 head->base.lut.b[i] = i << 8;
2411 }
2412
2413 ret = nv50_base_new(drm, head, &base);
2414 if (ret == 0)
2415 ret = nv50_curs_new(drm, head, &curs);
2416 if (ret) {
2417 kfree(head);
2418 return ret;
2419 }
2420
2421 crtc = &head->base.base;
2422 drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2423 &curs->wndw.plane, &nv50_head_func,
2424 "head-%d", head->base.index);
2425 drm_crtc_helper_add(crtc, &nv50_head_help);
2426 drm_mode_crtc_set_gamma_size(crtc, 256);
2427
2428 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
2429 0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
2430 if (!ret) {
2431 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
2432 if (!ret) {
2433 ret = nouveau_bo_map(head->base.lut.nvbo);
2434 if (ret)
2435 nouveau_bo_unpin(head->base.lut.nvbo);
2436 }
2437 if (ret)
2438 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
2439 }
2440
2441 if (ret)
2442 goto out;
2443
2444 /* allocate overlay resources */
2445 ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2446 if (ret)
2447 goto out;
2448
2449 ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2450 &head->ovly);
2451 if (ret)
2452 goto out;
2453
2454 out:
2455 if (ret)
2456 nv50_head_destroy(crtc);
2457 return ret;
2458 }
2459
2460 /******************************************************************************
2461 * Output path helpers
2462 *****************************************************************************/
2463 static int
2464 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2465 struct drm_crtc_state *crtc_state,
2466 struct drm_connector_state *conn_state,
2467 struct drm_display_mode *native_mode)
2468 {
2469 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2470 struct drm_display_mode *mode = &crtc_state->mode;
2471 struct drm_connector *connector = conn_state->connector;
2472 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2473 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2474
2475 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2476 asyc->scaler.full = false;
2477 if (!native_mode)
2478 return 0;
2479
2480 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2481 switch (connector->connector_type) {
2482 case DRM_MODE_CONNECTOR_LVDS:
2483 case DRM_MODE_CONNECTOR_eDP:
2484 /* Force use of scaler for non-EDID modes. */
2485 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2486 break;
2487 mode = native_mode;
2488 asyc->scaler.full = true;
2489 break;
2490 default:
2491 break;
2492 }
2493 } else {
2494 mode = native_mode;
2495 }
2496
2497 if (!drm_mode_equal(adjusted_mode, mode)) {
2498 drm_mode_copy(adjusted_mode, mode);
2499 crtc_state->mode_changed = true;
2500 }
2501
2502 return 0;
2503 }
2504
2505 static int
2506 nv50_outp_atomic_check(struct drm_encoder *encoder,
2507 struct drm_crtc_state *crtc_state,
2508 struct drm_connector_state *conn_state)
2509 {
2510 struct nouveau_connector *nv_connector =
2511 nouveau_connector(conn_state->connector);
2512 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2513 nv_connector->native_mode);
2514 }
2515
2516 /******************************************************************************
2517 * DAC
2518 *****************************************************************************/
2519 static void
2520 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
2521 {
2522 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2523 struct nv50_disp *disp = nv50_disp(encoder->dev);
2524 struct {
2525 struct nv50_disp_mthd_v1 base;
2526 struct nv50_disp_dac_pwr_v0 pwr;
2527 } args = {
2528 .base.version = 1,
2529 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
2530 .base.hasht = nv_encoder->dcb->hasht,
2531 .base.hashm = nv_encoder->dcb->hashm,
2532 .pwr.state = 1,
2533 .pwr.data = 1,
2534 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
2535 mode != DRM_MODE_DPMS_OFF),
2536 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
2537 mode != DRM_MODE_DPMS_OFF),
2538 };
2539
2540 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2541 }
2542
2543 static void
2544 nv50_dac_disable(struct drm_encoder *encoder)
2545 {
2546 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2547 struct nv50_mast *mast = nv50_mast(encoder->dev);
2548 const int or = nv_encoder->or;
2549 u32 *push;
2550
2551 if (nv_encoder->crtc) {
2552 push = evo_wait(mast, 4);
2553 if (push) {
2554 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2555 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2556 evo_data(push, 0x00000000);
2557 } else {
2558 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2559 evo_data(push, 0x00000000);
2560 }
2561 evo_kick(push, mast);
2562 }
2563 }
2564
2565 nv_encoder->crtc = NULL;
2566 }
2567
2568 static void
2569 nv50_dac_enable(struct drm_encoder *encoder)
2570 {
2571 struct nv50_mast *mast = nv50_mast(encoder->dev);
2572 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2573 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2574 struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2575 u32 *push;
2576
2577 push = evo_wait(mast, 8);
2578 if (push) {
2579 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2580 u32 syncs = 0x00000000;
2581
2582 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2583 syncs |= 0x00000001;
2584 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2585 syncs |= 0x00000002;
2586
2587 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2588 evo_data(push, 1 << nv_crtc->index);
2589 evo_data(push, syncs);
2590 } else {
2591 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2592 u32 syncs = 0x00000001;
2593
2594 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2595 syncs |= 0x00000008;
2596 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2597 syncs |= 0x00000010;
2598
2599 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2600 magic |= 0x00000001;
2601
2602 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2603 evo_data(push, syncs);
2604 evo_data(push, magic);
2605 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2606 evo_data(push, 1 << nv_crtc->index);
2607 }
2608
2609 evo_kick(push, mast);
2610 }
2611
2612 nv_encoder->crtc = encoder->crtc;
2613 }
2614
2615 static enum drm_connector_status
2616 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2617 {
2618 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2619 struct nv50_disp *disp = nv50_disp(encoder->dev);
2620 struct {
2621 struct nv50_disp_mthd_v1 base;
2622 struct nv50_disp_dac_load_v0 load;
2623 } args = {
2624 .base.version = 1,
2625 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2626 .base.hasht = nv_encoder->dcb->hasht,
2627 .base.hashm = nv_encoder->dcb->hashm,
2628 };
2629 int ret;
2630
2631 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2632 if (args.load.data == 0)
2633 args.load.data = 340;
2634
2635 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2636 if (ret || !args.load.load)
2637 return connector_status_disconnected;
2638
2639 return connector_status_connected;
2640 }
2641
2642 static const struct drm_encoder_helper_funcs
2643 nv50_dac_help = {
2644 .dpms = nv50_dac_dpms,
2645 .atomic_check = nv50_outp_atomic_check,
2646 .enable = nv50_dac_enable,
2647 .disable = nv50_dac_disable,
2648 .detect = nv50_dac_detect
2649 };
2650
2651 static void
2652 nv50_dac_destroy(struct drm_encoder *encoder)
2653 {
2654 drm_encoder_cleanup(encoder);
2655 kfree(encoder);
2656 }
2657
2658 static const struct drm_encoder_funcs
2659 nv50_dac_func = {
2660 .destroy = nv50_dac_destroy,
2661 };
2662
2663 static int
2664 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2665 {
2666 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2667 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2668 struct nvkm_i2c_bus *bus;
2669 struct nouveau_encoder *nv_encoder;
2670 struct drm_encoder *encoder;
2671 int type = DRM_MODE_ENCODER_DAC;
2672
2673 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2674 if (!nv_encoder)
2675 return -ENOMEM;
2676 nv_encoder->dcb = dcbe;
2677 nv_encoder->or = ffs(dcbe->or) - 1;
2678
2679 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2680 if (bus)
2681 nv_encoder->i2c = &bus->i2c;
2682
2683 encoder = to_drm_encoder(nv_encoder);
2684 encoder->possible_crtcs = dcbe->heads;
2685 encoder->possible_clones = 0;
2686 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2687 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2688 drm_encoder_helper_add(encoder, &nv50_dac_help);
2689
2690 drm_mode_connector_attach_encoder(connector, encoder);
2691 return 0;
2692 }
2693
2694 /******************************************************************************
2695 * Audio
2696 *****************************************************************************/
2697 static void
2698 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2699 {
2700 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2701 struct nv50_disp *disp = nv50_disp(encoder->dev);
2702 struct {
2703 struct nv50_disp_mthd_v1 base;
2704 struct nv50_disp_sor_hda_eld_v0 eld;
2705 } args = {
2706 .base.version = 1,
2707 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2708 .base.hasht = nv_encoder->dcb->hasht,
2709 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2710 (0x0100 << nv_crtc->index),
2711 };
2712
2713 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2714 }
2715
2716 static void
2717 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2718 {
2719 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2720 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2721 struct nouveau_connector *nv_connector;
2722 struct nv50_disp *disp = nv50_disp(encoder->dev);
2723 struct __packed {
2724 struct {
2725 struct nv50_disp_mthd_v1 mthd;
2726 struct nv50_disp_sor_hda_eld_v0 eld;
2727 } base;
2728 u8 data[sizeof(nv_connector->base.eld)];
2729 } args = {
2730 .base.mthd.version = 1,
2731 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2732 .base.mthd.hasht = nv_encoder->dcb->hasht,
2733 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2734 (0x0100 << nv_crtc->index),
2735 };
2736
2737 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2738 if (!drm_detect_monitor_audio(nv_connector->edid))
2739 return;
2740
2741 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
2742 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2743
2744 nvif_mthd(disp->disp, 0, &args,
2745 sizeof(args.base) + drm_eld_size(args.data));
2746 }
2747
2748 /******************************************************************************
2749 * HDMI
2750 *****************************************************************************/
2751 static void
2752 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2753 {
2754 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2755 struct nv50_disp *disp = nv50_disp(encoder->dev);
2756 struct {
2757 struct nv50_disp_mthd_v1 base;
2758 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2759 } args = {
2760 .base.version = 1,
2761 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2762 .base.hasht = nv_encoder->dcb->hasht,
2763 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2764 (0x0100 << nv_crtc->index),
2765 };
2766
2767 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2768 }
2769
2770 static void
2771 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2772 {
2773 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2774 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2775 struct nv50_disp *disp = nv50_disp(encoder->dev);
2776 struct {
2777 struct nv50_disp_mthd_v1 base;
2778 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2779 } args = {
2780 .base.version = 1,
2781 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2782 .base.hasht = nv_encoder->dcb->hasht,
2783 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2784 (0x0100 << nv_crtc->index),
2785 .pwr.state = 1,
2786 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2787 };
2788 struct nouveau_connector *nv_connector;
2789 u32 max_ac_packet;
2790
2791 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2792 if (!drm_detect_hdmi_monitor(nv_connector->edid))
2793 return;
2794
2795 max_ac_packet = mode->htotal - mode->hdisplay;
2796 max_ac_packet -= args.pwr.rekey;
2797 max_ac_packet -= 18; /* constant from tegra */
2798 args.pwr.max_ac_packet = max_ac_packet / 32;
2799
2800 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2801 nv50_audio_enable(encoder, mode);
2802 }
2803
2804 /******************************************************************************
2805 * MST
2806 *****************************************************************************/
2807 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2808 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2809 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2810
2811 struct nv50_mstm {
2812 struct nouveau_encoder *outp;
2813
2814 struct drm_dp_mst_topology_mgr mgr;
2815 struct nv50_msto *msto[4];
2816
2817 bool modified;
2818 };
2819
2820 struct nv50_mstc {
2821 struct nv50_mstm *mstm;
2822 struct drm_dp_mst_port *port;
2823 struct drm_connector connector;
2824
2825 struct drm_display_mode *native;
2826 struct edid *edid;
2827
2828 int pbn;
2829 };
2830
2831 struct nv50_msto {
2832 struct drm_encoder encoder;
2833
2834 struct nv50_head *head;
2835 struct nv50_mstc *mstc;
2836 bool disabled;
2837 };
2838
2839 static struct drm_dp_payload *
2840 nv50_msto_payload(struct nv50_msto *msto)
2841 {
2842 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2843 struct nv50_mstc *mstc = msto->mstc;
2844 struct nv50_mstm *mstm = mstc->mstm;
2845 int vcpi = mstc->port->vcpi.vcpi, i;
2846
2847 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2848 for (i = 0; i < mstm->mgr.max_payloads; i++) {
2849 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2850 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2851 mstm->outp->base.base.name, i, payload->vcpi,
2852 payload->start_slot, payload->num_slots);
2853 }
2854
2855 for (i = 0; i < mstm->mgr.max_payloads; i++) {
2856 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2857 if (payload->vcpi == vcpi)
2858 return payload;
2859 }
2860
2861 return NULL;
2862 }
2863
2864 static void
2865 nv50_msto_cleanup(struct nv50_msto *msto)
2866 {
2867 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2868 struct nv50_mstc *mstc = msto->mstc;
2869 struct nv50_mstm *mstm = mstc->mstm;
2870
2871 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2872 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2873 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2874 if (msto->disabled) {
2875 msto->mstc = NULL;
2876 msto->head = NULL;
2877 msto->disabled = false;
2878 }
2879 }
2880
2881 static void
2882 nv50_msto_prepare(struct nv50_msto *msto)
2883 {
2884 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2885 struct nv50_mstc *mstc = msto->mstc;
2886 struct nv50_mstm *mstm = mstc->mstm;
2887 struct {
2888 struct nv50_disp_mthd_v1 base;
2889 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2890 } args = {
2891 .base.version = 1,
2892 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2893 .base.hasht = mstm->outp->dcb->hasht,
2894 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
2895 (0x0100 << msto->head->base.index),
2896 };
2897
2898 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2899 if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2900 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2901 if (payload) {
2902 args.vcpi.start_slot = payload->start_slot;
2903 args.vcpi.num_slots = payload->num_slots;
2904 args.vcpi.pbn = mstc->port->vcpi.pbn;
2905 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2906 }
2907 }
2908
2909 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2910 msto->encoder.name, msto->head->base.base.name,
2911 args.vcpi.start_slot, args.vcpi.num_slots,
2912 args.vcpi.pbn, args.vcpi.aligned_pbn);
2913 nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2914 }
2915
2916 static int
2917 nv50_msto_atomic_check(struct drm_encoder *encoder,
2918 struct drm_crtc_state *crtc_state,
2919 struct drm_connector_state *conn_state)
2920 {
2921 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2922 struct nv50_mstm *mstm = mstc->mstm;
2923 int bpp = conn_state->connector->display_info.bpc * 3;
2924 int slots;
2925
2926 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2927
2928 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2929 if (slots < 0)
2930 return slots;
2931
2932 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2933 mstc->native);
2934 }
2935
2936 static void
2937 nv50_msto_enable(struct drm_encoder *encoder)
2938 {
2939 struct nv50_head *head = nv50_head(encoder->crtc);
2940 struct nv50_msto *msto = nv50_msto(encoder);
2941 struct nv50_mstc *mstc = NULL;
2942 struct nv50_mstm *mstm = NULL;
2943 struct drm_connector *connector;
2944 u8 proto, depth;
2945 int slots;
2946 bool r;
2947
2948 drm_for_each_connector(connector, encoder->dev) {
2949 if (connector->state->best_encoder == &msto->encoder) {
2950 mstc = nv50_mstc(connector);
2951 mstm = mstc->mstm;
2952 break;
2953 }
2954 }
2955
2956 if (WARN_ON(!mstc))
2957 return;
2958
2959 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, &slots);
2960 WARN_ON(!r);
2961
2962 if (mstm->outp->dcb->sorconf.link & 1)
2963 proto = 0x8;
2964 else
2965 proto = 0x9;
2966
2967 switch (mstc->connector.display_info.bpc) {
2968 case 6: depth = 0x2; break;
2969 case 8: depth = 0x5; break;
2970 case 10:
2971 default: depth = 0x6; break;
2972 }
2973
2974 mstm->outp->update(mstm->outp, head->base.index,
2975 &head->base.base.state->adjusted_mode, proto, depth);
2976
2977 msto->head = head;
2978 msto->mstc = mstc;
2979 mstm->modified = true;
2980 }
2981
2982 static void
2983 nv50_msto_disable(struct drm_encoder *encoder)
2984 {
2985 struct nv50_msto *msto = nv50_msto(encoder);
2986 struct nv50_mstc *mstc = msto->mstc;
2987 struct nv50_mstm *mstm = mstc->mstm;
2988
2989 if (mstc->port)
2990 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
2991
2992 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
2993 mstm->modified = true;
2994 msto->disabled = true;
2995 }
2996
2997 static const struct drm_encoder_helper_funcs
2998 nv50_msto_help = {
2999 .disable = nv50_msto_disable,
3000 .enable = nv50_msto_enable,
3001 .atomic_check = nv50_msto_atomic_check,
3002 };
3003
3004 static void
3005 nv50_msto_destroy(struct drm_encoder *encoder)
3006 {
3007 struct nv50_msto *msto = nv50_msto(encoder);
3008 drm_encoder_cleanup(&msto->encoder);
3009 kfree(msto);
3010 }
3011
3012 static const struct drm_encoder_funcs
3013 nv50_msto = {
3014 .destroy = nv50_msto_destroy,
3015 };
3016
3017 static int
3018 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
3019 struct nv50_msto **pmsto)
3020 {
3021 struct nv50_msto *msto;
3022 int ret;
3023
3024 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
3025 return -ENOMEM;
3026
3027 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
3028 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
3029 if (ret) {
3030 kfree(*pmsto);
3031 *pmsto = NULL;
3032 return ret;
3033 }
3034
3035 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
3036 msto->encoder.possible_crtcs = heads;
3037 return 0;
3038 }
3039
3040 static struct drm_encoder *
3041 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
3042 struct drm_connector_state *connector_state)
3043 {
3044 struct nv50_head *head = nv50_head(connector_state->crtc);
3045 struct nv50_mstc *mstc = nv50_mstc(connector);
3046 if (mstc->port) {
3047 struct nv50_mstm *mstm = mstc->mstm;
3048 return &mstm->msto[head->base.index]->encoder;
3049 }
3050 return NULL;
3051 }
3052
3053 static struct drm_encoder *
3054 nv50_mstc_best_encoder(struct drm_connector *connector)
3055 {
3056 struct nv50_mstc *mstc = nv50_mstc(connector);
3057 if (mstc->port) {
3058 struct nv50_mstm *mstm = mstc->mstm;
3059 return &mstm->msto[0]->encoder;
3060 }
3061 return NULL;
3062 }
3063
3064 static enum drm_mode_status
3065 nv50_mstc_mode_valid(struct drm_connector *connector,
3066 struct drm_display_mode *mode)
3067 {
3068 return MODE_OK;
3069 }
3070
3071 static int
3072 nv50_mstc_get_modes(struct drm_connector *connector)
3073 {
3074 struct nv50_mstc *mstc = nv50_mstc(connector);
3075 int ret = 0;
3076
3077 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3078 drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3079 if (mstc->edid) {
3080 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3081 drm_edid_to_eld(&mstc->connector, mstc->edid);
3082 }
3083
3084 if (!mstc->connector.display_info.bpc)
3085 mstc->connector.display_info.bpc = 8;
3086
3087 if (mstc->native)
3088 drm_mode_destroy(mstc->connector.dev, mstc->native);
3089 mstc->native = nouveau_conn_native_mode(&mstc->connector);
3090 return ret;
3091 }
3092
3093 static const struct drm_connector_helper_funcs
3094 nv50_mstc_help = {
3095 .get_modes = nv50_mstc_get_modes,
3096 .mode_valid = nv50_mstc_mode_valid,
3097 .best_encoder = nv50_mstc_best_encoder,
3098 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3099 };
3100
3101 static enum drm_connector_status
3102 nv50_mstc_detect(struct drm_connector *connector, bool force)
3103 {
3104 struct nv50_mstc *mstc = nv50_mstc(connector);
3105 if (!mstc->port)
3106 return connector_status_disconnected;
3107 return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3108 }
3109
3110 static void
3111 nv50_mstc_destroy(struct drm_connector *connector)
3112 {
3113 struct nv50_mstc *mstc = nv50_mstc(connector);
3114 drm_connector_cleanup(&mstc->connector);
3115 kfree(mstc);
3116 }
3117
3118 static const struct drm_connector_funcs
3119 nv50_mstc = {
3120 .dpms = drm_atomic_helper_connector_dpms,
3121 .reset = nouveau_conn_reset,
3122 .detect = nv50_mstc_detect,
3123 .fill_modes = drm_helper_probe_single_connector_modes,
3124 .set_property = drm_atomic_helper_connector_set_property,
3125 .destroy = nv50_mstc_destroy,
3126 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3127 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3128 .atomic_set_property = nouveau_conn_atomic_set_property,
3129 .atomic_get_property = nouveau_conn_atomic_get_property,
3130 };
3131
3132 static int
3133 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3134 const char *path, struct nv50_mstc **pmstc)
3135 {
3136 struct drm_device *dev = mstm->outp->base.base.dev;
3137 struct nv50_mstc *mstc;
3138 int ret, i;
3139
3140 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3141 return -ENOMEM;
3142 mstc->mstm = mstm;
3143 mstc->port = port;
3144
3145 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3146 DRM_MODE_CONNECTOR_DisplayPort);
3147 if (ret) {
3148 kfree(*pmstc);
3149 *pmstc = NULL;
3150 return ret;
3151 }
3152
3153 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3154
3155 mstc->connector.funcs->reset(&mstc->connector);
3156 nouveau_conn_attach_properties(&mstc->connector);
3157
3158 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++)
3159 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3160
3161 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3162 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3163 drm_mode_connector_set_path_property(&mstc->connector, path);
3164 return 0;
3165 }
3166
3167 static void
3168 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3169 {
3170 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3171 struct drm_encoder *encoder;
3172 int ret;
3173
3174 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3175 ret = drm_dp_check_act_status(&mstm->mgr);
3176
3177 ret = drm_dp_update_payload_part2(&mstm->mgr);
3178
3179 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3180 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3181 struct nv50_msto *msto = nv50_msto(encoder);
3182 struct nv50_mstc *mstc = msto->mstc;
3183 if (mstc && mstc->mstm == mstm)
3184 nv50_msto_cleanup(msto);
3185 }
3186 }
3187
3188 mstm->modified = false;
3189 }
3190
3191 static void
3192 nv50_mstm_prepare(struct nv50_mstm *mstm)
3193 {
3194 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3195 struct drm_encoder *encoder;
3196 int ret;
3197
3198 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3199 ret = drm_dp_update_payload_part1(&mstm->mgr);
3200
3201 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3202 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3203 struct nv50_msto *msto = nv50_msto(encoder);
3204 struct nv50_mstc *mstc = msto->mstc;
3205 if (mstc && mstc->mstm == mstm)
3206 nv50_msto_prepare(msto);
3207 }
3208 }
3209 }
3210
3211 static void
3212 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3213 {
3214 struct nv50_mstm *mstm = nv50_mstm(mgr);
3215 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3216 }
3217
3218 static void
3219 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3220 struct drm_connector *connector)
3221 {
3222 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3223 struct nv50_mstc *mstc = nv50_mstc(connector);
3224
3225 drm_connector_unregister(&mstc->connector);
3226
3227 drm_modeset_lock_all(drm->dev);
3228 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3229 mstc->port = NULL;
3230 drm_modeset_unlock_all(drm->dev);
3231
3232 drm_connector_unreference(&mstc->connector);
3233 }
3234
3235 static void
3236 nv50_mstm_register_connector(struct drm_connector *connector)
3237 {
3238 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3239
3240 drm_modeset_lock_all(drm->dev);
3241 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3242 drm_modeset_unlock_all(drm->dev);
3243
3244 drm_connector_register(connector);
3245 }
3246
3247 static struct drm_connector *
3248 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3249 struct drm_dp_mst_port *port, const char *path)
3250 {
3251 struct nv50_mstm *mstm = nv50_mstm(mgr);
3252 struct nv50_mstc *mstc;
3253 int ret;
3254
3255 ret = nv50_mstc_new(mstm, port, path, &mstc);
3256 if (ret) {
3257 if (mstc)
3258 mstc->connector.funcs->destroy(&mstc->connector);
3259 return NULL;
3260 }
3261
3262 return &mstc->connector;
3263 }
3264
3265 static const struct drm_dp_mst_topology_cbs
3266 nv50_mstm = {
3267 .add_connector = nv50_mstm_add_connector,
3268 .register_connector = nv50_mstm_register_connector,
3269 .destroy_connector = nv50_mstm_destroy_connector,
3270 .hotplug = nv50_mstm_hotplug,
3271 };
3272
3273 void
3274 nv50_mstm_service(struct nv50_mstm *mstm)
3275 {
3276 struct drm_dp_aux *aux = mstm->mgr.aux;
3277 bool handled = true;
3278 int ret;
3279 u8 esi[8] = {};
3280
3281 while (handled) {
3282 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3283 if (ret != 8) {
3284 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3285 return;
3286 }
3287
3288 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3289 if (!handled)
3290 break;
3291
3292 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3293 }
3294 }
3295
3296 void
3297 nv50_mstm_remove(struct nv50_mstm *mstm)
3298 {
3299 if (mstm)
3300 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3301 }
3302
3303 static int
3304 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3305 {
3306 struct nouveau_encoder *outp = mstm->outp;
3307 struct {
3308 struct nv50_disp_mthd_v1 base;
3309 struct nv50_disp_sor_dp_mst_link_v0 mst;
3310 } args = {
3311 .base.version = 1,
3312 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3313 .base.hasht = outp->dcb->hasht,
3314 .base.hashm = outp->dcb->hashm,
3315 .mst.state = state,
3316 };
3317 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3318 struct nvif_object *disp = &drm->display->disp;
3319 int ret;
3320
3321 if (dpcd >= 0x12) {
3322 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3323 if (ret < 0)
3324 return ret;
3325
3326 dpcd &= ~DP_MST_EN;
3327 if (state)
3328 dpcd |= DP_MST_EN;
3329
3330 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3331 if (ret < 0)
3332 return ret;
3333 }
3334
3335 return nvif_mthd(disp, 0, &args, sizeof(args));
3336 }
3337
3338 int
3339 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3340 {
3341 int ret, state = 0;
3342
3343 if (!mstm)
3344 return 0;
3345
3346 if (dpcd[0] >= 0x12 && allow) {
3347 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3348 if (ret < 0)
3349 return ret;
3350
3351 state = dpcd[1] & DP_MST_CAP;
3352 }
3353
3354 ret = nv50_mstm_enable(mstm, dpcd[0], state);
3355 if (ret)
3356 return ret;
3357
3358 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3359 if (ret)
3360 return nv50_mstm_enable(mstm, dpcd[0], 0);
3361
3362 return mstm->mgr.mst_state;
3363 }
3364
3365 static void
3366 nv50_mstm_fini(struct nv50_mstm *mstm)
3367 {
3368 if (mstm && mstm->mgr.mst_state)
3369 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3370 }
3371
3372 static void
3373 nv50_mstm_init(struct nv50_mstm *mstm)
3374 {
3375 if (mstm && mstm->mgr.mst_state)
3376 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3377 }
3378
3379 static void
3380 nv50_mstm_del(struct nv50_mstm **pmstm)
3381 {
3382 struct nv50_mstm *mstm = *pmstm;
3383 if (mstm) {
3384 kfree(*pmstm);
3385 *pmstm = NULL;
3386 }
3387 }
3388
3389 static int
3390 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3391 int conn_base_id, struct nv50_mstm **pmstm)
3392 {
3393 const int max_payloads = hweight8(outp->dcb->heads);
3394 struct drm_device *dev = outp->base.base.dev;
3395 struct nv50_mstm *mstm;
3396 int ret, i;
3397 u8 dpcd;
3398
3399 /* This is a workaround for some monitors not functioning
3400 * correctly in MST mode on initial module load. I think
3401 * some bad interaction with the VBIOS may be responsible.
3402 *
3403 * A good ol' off and on again seems to work here ;)
3404 */
3405 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3406 if (ret >= 0 && dpcd >= 0x12)
3407 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3408
3409 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3410 return -ENOMEM;
3411 mstm->outp = outp;
3412 mstm->mgr.cbs = &nv50_mstm;
3413
3414 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev->dev, aux, aux_max,
3415 max_payloads, conn_base_id);
3416 if (ret)
3417 return ret;
3418
3419 for (i = 0; i < max_payloads; i++) {
3420 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3421 i, &mstm->msto[i]);
3422 if (ret)
3423 return ret;
3424 }
3425
3426 return 0;
3427 }
3428
3429 /******************************************************************************
3430 * SOR
3431 *****************************************************************************/
3432 static void
3433 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
3434 {
3435 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3436 struct nv50_disp *disp = nv50_disp(encoder->dev);
3437 struct {
3438 struct nv50_disp_mthd_v1 base;
3439 struct nv50_disp_sor_pwr_v0 pwr;
3440 } args = {
3441 .base.version = 1,
3442 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
3443 .base.hasht = nv_encoder->dcb->hasht,
3444 .base.hashm = nv_encoder->dcb->hashm,
3445 .pwr.state = mode == DRM_MODE_DPMS_ON,
3446 };
3447
3448 nvif_mthd(disp->disp, 0, &args, sizeof(args));
3449 }
3450
3451 static void
3452 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3453 struct drm_display_mode *mode, u8 proto, u8 depth)
3454 {
3455 struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3456 u32 *push;
3457
3458 if (!mode) {
3459 nv_encoder->ctrl &= ~BIT(head);
3460 if (!(nv_encoder->ctrl & 0x0000000f))
3461 nv_encoder->ctrl = 0;
3462 } else {
3463 nv_encoder->ctrl |= proto << 8;
3464 nv_encoder->ctrl |= BIT(head);
3465 }
3466
3467 if ((push = evo_wait(core, 6))) {
3468 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3469 if (mode) {
3470 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3471 nv_encoder->ctrl |= 0x00001000;
3472 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3473 nv_encoder->ctrl |= 0x00002000;
3474 nv_encoder->ctrl |= depth << 16;
3475 }
3476 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3477 } else {
3478 if (mode) {
3479 u32 magic = 0x31ec6000 | (head << 25);
3480 u32 syncs = 0x00000001;
3481 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3482 syncs |= 0x00000008;
3483 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3484 syncs |= 0x00000010;
3485 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3486 magic |= 0x00000001;
3487
3488 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3489 evo_data(push, syncs | (depth << 6));
3490 evo_data(push, magic);
3491 }
3492 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3493 }
3494 evo_data(push, nv_encoder->ctrl);
3495 evo_kick(push, core);
3496 }
3497 }
3498
3499 static void
3500 nv50_sor_disable(struct drm_encoder *encoder)
3501 {
3502 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3503 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3504
3505 nv_encoder->crtc = NULL;
3506
3507 if (nv_crtc) {
3508 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3509 u8 pwr;
3510
3511 if (aux) {
3512 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3513 if (ret == 0) {
3514 pwr &= ~DP_SET_POWER_MASK;
3515 pwr |= DP_SET_POWER_D3;
3516 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3517 }
3518 }
3519
3520 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3521 nv50_audio_disable(encoder, nv_crtc);
3522 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3523 }
3524 }
3525
3526 static void
3527 nv50_sor_enable(struct drm_encoder *encoder)
3528 {
3529 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3530 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3531 struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3532 struct {
3533 struct nv50_disp_mthd_v1 base;
3534 struct nv50_disp_sor_lvds_script_v0 lvds;
3535 } lvds = {
3536 .base.version = 1,
3537 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3538 .base.hasht = nv_encoder->dcb->hasht,
3539 .base.hashm = nv_encoder->dcb->hashm,
3540 };
3541 struct nv50_disp *disp = nv50_disp(encoder->dev);
3542 struct drm_device *dev = encoder->dev;
3543 struct nouveau_drm *drm = nouveau_drm(dev);
3544 struct nouveau_connector *nv_connector;
3545 struct nvbios *bios = &drm->vbios;
3546 u8 proto = 0xf;
3547 u8 depth = 0x0;
3548
3549 nv_connector = nouveau_encoder_connector_get(nv_encoder);
3550 nv_encoder->crtc = encoder->crtc;
3551
3552 switch (nv_encoder->dcb->type) {
3553 case DCB_OUTPUT_TMDS:
3554 if (nv_encoder->dcb->sorconf.link & 1) {
3555 proto = 0x1;
3556 /* Only enable dual-link if:
3557 * - Need to (i.e. rate > 165MHz)
3558 * - DCB says we can
3559 * - Not an HDMI monitor, since there's no dual-link
3560 * on HDMI.
3561 */
3562 if (mode->clock >= 165000 &&
3563 nv_encoder->dcb->duallink_possible &&
3564 !drm_detect_hdmi_monitor(nv_connector->edid))
3565 proto |= 0x4;
3566 } else {
3567 proto = 0x2;
3568 }
3569
3570 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3571 break;
3572 case DCB_OUTPUT_LVDS:
3573 proto = 0x0;
3574
3575 if (bios->fp_no_ddc) {
3576 if (bios->fp.dual_link)
3577 lvds.lvds.script |= 0x0100;
3578 if (bios->fp.if_is_24bit)
3579 lvds.lvds.script |= 0x0200;
3580 } else {
3581 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3582 if (((u8 *)nv_connector->edid)[121] == 2)
3583 lvds.lvds.script |= 0x0100;
3584 } else
3585 if (mode->clock >= bios->fp.duallink_transition_clk) {
3586 lvds.lvds.script |= 0x0100;
3587 }
3588
3589 if (lvds.lvds.script & 0x0100) {
3590 if (bios->fp.strapless_is_24bit & 2)
3591 lvds.lvds.script |= 0x0200;
3592 } else {
3593 if (bios->fp.strapless_is_24bit & 1)
3594 lvds.lvds.script |= 0x0200;
3595 }
3596
3597 if (nv_connector->base.display_info.bpc == 8)
3598 lvds.lvds.script |= 0x0200;
3599 }
3600
3601 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3602 break;
3603 case DCB_OUTPUT_DP:
3604 if (nv_connector->base.display_info.bpc == 6)
3605 depth = 0x2;
3606 else
3607 if (nv_connector->base.display_info.bpc == 8)
3608 depth = 0x5;
3609 else
3610 depth = 0x6;
3611
3612 if (nv_encoder->dcb->sorconf.link & 1)
3613 proto = 0x8;
3614 else
3615 proto = 0x9;
3616
3617 nv50_audio_enable(encoder, mode);
3618 break;
3619 default:
3620 BUG_ON(1);
3621 break;
3622 }
3623
3624 nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3625 }
3626
3627 static const struct drm_encoder_helper_funcs
3628 nv50_sor_help = {
3629 .dpms = nv50_sor_dpms,
3630 .atomic_check = nv50_outp_atomic_check,
3631 .enable = nv50_sor_enable,
3632 .disable = nv50_sor_disable,
3633 };
3634
3635 static void
3636 nv50_sor_destroy(struct drm_encoder *encoder)
3637 {
3638 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3639 nv50_mstm_del(&nv_encoder->dp.mstm);
3640 drm_encoder_cleanup(encoder);
3641 kfree(encoder);
3642 }
3643
3644 static const struct drm_encoder_funcs
3645 nv50_sor_func = {
3646 .destroy = nv50_sor_destroy,
3647 };
3648
3649 static int
3650 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3651 {
3652 struct nouveau_connector *nv_connector = nouveau_connector(connector);
3653 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3654 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
3655 struct nouveau_encoder *nv_encoder;
3656 struct drm_encoder *encoder;
3657 int type, ret;
3658
3659 switch (dcbe->type) {
3660 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3661 case DCB_OUTPUT_TMDS:
3662 case DCB_OUTPUT_DP:
3663 default:
3664 type = DRM_MODE_ENCODER_TMDS;
3665 break;
3666 }
3667
3668 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3669 if (!nv_encoder)
3670 return -ENOMEM;
3671 nv_encoder->dcb = dcbe;
3672 nv_encoder->or = ffs(dcbe->or) - 1;
3673 nv_encoder->update = nv50_sor_update;
3674
3675 encoder = to_drm_encoder(nv_encoder);
3676 encoder->possible_crtcs = dcbe->heads;
3677 encoder->possible_clones = 0;
3678 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3679 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3680 drm_encoder_helper_add(encoder, &nv50_sor_help);
3681
3682 drm_mode_connector_attach_encoder(connector, encoder);
3683
3684 if (dcbe->type == DCB_OUTPUT_DP) {
3685 struct nvkm_i2c_aux *aux =
3686 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3687 if (aux) {
3688 nv_encoder->i2c = &aux->i2c;
3689 nv_encoder->aux = aux;
3690 }
3691
3692 /*TODO: Use DP Info Table to check for support. */
3693 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
3694 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3695 nv_connector->base.base.id,
3696 &nv_encoder->dp.mstm);
3697 if (ret)
3698 return ret;
3699 }
3700 } else {
3701 struct nvkm_i2c_bus *bus =
3702 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3703 if (bus)
3704 nv_encoder->i2c = &bus->i2c;
3705 }
3706
3707 return 0;
3708 }
3709
3710 /******************************************************************************
3711 * PIOR
3712 *****************************************************************************/
3713 static void
3714 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
3715 {
3716 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3717 struct nv50_disp *disp = nv50_disp(encoder->dev);
3718 struct {
3719 struct nv50_disp_mthd_v1 base;
3720 struct nv50_disp_pior_pwr_v0 pwr;
3721 } args = {
3722 .base.version = 1,
3723 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
3724 .base.hasht = nv_encoder->dcb->hasht,
3725 .base.hashm = nv_encoder->dcb->hashm,
3726 .pwr.state = mode == DRM_MODE_DPMS_ON,
3727 .pwr.type = nv_encoder->dcb->type,
3728 };
3729
3730 nvif_mthd(disp->disp, 0, &args, sizeof(args));
3731 }
3732
3733 static int
3734 nv50_pior_atomic_check(struct drm_encoder *encoder,
3735 struct drm_crtc_state *crtc_state,
3736 struct drm_connector_state *conn_state)
3737 {
3738 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3739 if (ret)
3740 return ret;
3741 crtc_state->adjusted_mode.clock *= 2;
3742 return 0;
3743 }
3744
3745 static void
3746 nv50_pior_disable(struct drm_encoder *encoder)
3747 {
3748 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3749 struct nv50_mast *mast = nv50_mast(encoder->dev);
3750 const int or = nv_encoder->or;
3751 u32 *push;
3752
3753 if (nv_encoder->crtc) {
3754 push = evo_wait(mast, 4);
3755 if (push) {
3756 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3757 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3758 evo_data(push, 0x00000000);
3759 }
3760 evo_kick(push, mast);
3761 }
3762 }
3763
3764 nv_encoder->crtc = NULL;
3765 }
3766
3767 static void
3768 nv50_pior_enable(struct drm_encoder *encoder)
3769 {
3770 struct nv50_mast *mast = nv50_mast(encoder->dev);
3771 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3772 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3773 struct nouveau_connector *nv_connector;
3774 struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3775 u8 owner = 1 << nv_crtc->index;
3776 u8 proto, depth;
3777 u32 *push;
3778
3779 nv_connector = nouveau_encoder_connector_get(nv_encoder);
3780 switch (nv_connector->base.display_info.bpc) {
3781 case 10: depth = 0x6; break;
3782 case 8: depth = 0x5; break;
3783 case 6: depth = 0x2; break;
3784 default: depth = 0x0; break;
3785 }
3786
3787 switch (nv_encoder->dcb->type) {
3788 case DCB_OUTPUT_TMDS:
3789 case DCB_OUTPUT_DP:
3790 proto = 0x0;
3791 break;
3792 default:
3793 BUG_ON(1);
3794 break;
3795 }
3796
3797 push = evo_wait(mast, 8);
3798 if (push) {
3799 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3800 u32 ctrl = (depth << 16) | (proto << 8) | owner;
3801 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3802 ctrl |= 0x00001000;
3803 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3804 ctrl |= 0x00002000;
3805 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3806 evo_data(push, ctrl);
3807 }
3808
3809 evo_kick(push, mast);
3810 }
3811
3812 nv_encoder->crtc = encoder->crtc;
3813 }
3814
3815 static const struct drm_encoder_helper_funcs
3816 nv50_pior_help = {
3817 .dpms = nv50_pior_dpms,
3818 .atomic_check = nv50_pior_atomic_check,
3819 .enable = nv50_pior_enable,
3820 .disable = nv50_pior_disable,
3821 };
3822
3823 static void
3824 nv50_pior_destroy(struct drm_encoder *encoder)
3825 {
3826 drm_encoder_cleanup(encoder);
3827 kfree(encoder);
3828 }
3829
3830 static const struct drm_encoder_funcs
3831 nv50_pior_func = {
3832 .destroy = nv50_pior_destroy,
3833 };
3834
3835 static int
3836 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3837 {
3838 struct nouveau_drm *drm = nouveau_drm(connector->dev);
3839 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
3840 struct nvkm_i2c_bus *bus = NULL;
3841 struct nvkm_i2c_aux *aux = NULL;
3842 struct i2c_adapter *ddc;
3843 struct nouveau_encoder *nv_encoder;
3844 struct drm_encoder *encoder;
3845 int type;
3846
3847 switch (dcbe->type) {
3848 case DCB_OUTPUT_TMDS:
3849 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3850 ddc = bus ? &bus->i2c : NULL;
3851 type = DRM_MODE_ENCODER_TMDS;
3852 break;
3853 case DCB_OUTPUT_DP:
3854 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3855 ddc = aux ? &aux->i2c : NULL;
3856 type = DRM_MODE_ENCODER_TMDS;
3857 break;
3858 default:
3859 return -ENODEV;
3860 }
3861
3862 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3863 if (!nv_encoder)
3864 return -ENOMEM;
3865 nv_encoder->dcb = dcbe;
3866 nv_encoder->or = ffs(dcbe->or) - 1;
3867 nv_encoder->i2c = ddc;
3868 nv_encoder->aux = aux;
3869
3870 encoder = to_drm_encoder(nv_encoder);
3871 encoder->possible_crtcs = dcbe->heads;
3872 encoder->possible_clones = 0;
3873 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3874 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3875 drm_encoder_helper_add(encoder, &nv50_pior_help);
3876
3877 drm_mode_connector_attach_encoder(connector, encoder);
3878 return 0;
3879 }
3880
3881 /******************************************************************************
3882 * Atomic
3883 *****************************************************************************/
3884
3885 static void
3886 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3887 {
3888 struct nv50_disp *disp = nv50_disp(drm->dev);
3889 struct nv50_dmac *core = &disp->mast.base;
3890 struct nv50_mstm *mstm;
3891 struct drm_encoder *encoder;
3892 u32 *push;
3893
3894 NV_ATOMIC(drm, "commit core %08x\n", interlock);
3895
3896 drm_for_each_encoder(encoder, drm->dev) {
3897 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3898 mstm = nouveau_encoder(encoder)->dp.mstm;
3899 if (mstm && mstm->modified)
3900 nv50_mstm_prepare(mstm);
3901 }
3902 }
3903
3904 if ((push = evo_wait(core, 5))) {
3905 evo_mthd(push, 0x0084, 1);
3906 evo_data(push, 0x80000000);
3907 evo_mthd(push, 0x0080, 2);
3908 evo_data(push, interlock);
3909 evo_data(push, 0x00000000);
3910 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3911 evo_kick(push, core);
3912 if (nvif_msec(&drm->device, 2000ULL,
3913 if (nouveau_bo_rd32(disp->sync, 0))
3914 break;
3915 usleep_range(1, 2);
3916 ) < 0)
3917 NV_ERROR(drm, "EVO timeout\n");
3918 }
3919
3920 drm_for_each_encoder(encoder, drm->dev) {
3921 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3922 mstm = nouveau_encoder(encoder)->dp.mstm;
3923 if (mstm && mstm->modified)
3924 nv50_mstm_cleanup(mstm);
3925 }
3926 }
3927 }
3928
3929 static void
3930 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3931 {
3932 struct drm_device *dev = state->dev;
3933 struct drm_crtc_state *crtc_state;
3934 struct drm_crtc *crtc;
3935 struct drm_plane_state *plane_state;
3936 struct drm_plane *plane;
3937 struct nouveau_drm *drm = nouveau_drm(dev);
3938 struct nv50_disp *disp = nv50_disp(dev);
3939 struct nv50_atom *atom = nv50_atom(state);
3940 struct nv50_outp_atom *outp, *outt;
3941 u32 interlock_core = 0;
3942 u32 interlock_chan = 0;
3943 int i;
3944
3945 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3946 drm_atomic_helper_wait_for_fences(dev, state, false);
3947 drm_atomic_helper_wait_for_dependencies(state);
3948 drm_atomic_helper_update_legacy_modeset_state(dev, state);
3949
3950 if (atom->lock_core)
3951 mutex_lock(&disp->mutex);
3952
3953 /* Disable head(s). */
3954 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3955 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3956 struct nv50_head *head = nv50_head(crtc);
3957
3958 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3959 asyh->clr.mask, asyh->set.mask);
3960
3961 if (asyh->clr.mask) {
3962 nv50_head_flush_clr(head, asyh, atom->flush_disable);
3963 interlock_core |= 1;
3964 }
3965 }
3966
3967 /* Disable plane(s). */
3968 for_each_plane_in_state(state, plane, plane_state, i) {
3969 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3970 struct nv50_wndw *wndw = nv50_wndw(plane);
3971
3972 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3973 asyw->clr.mask, asyw->set.mask);
3974 if (!asyw->clr.mask)
3975 continue;
3976
3977 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3978 atom->flush_disable,
3979 asyw);
3980 }
3981
3982 /* Disable output path(s). */
3983 list_for_each_entry(outp, &atom->outp, head) {
3984 const struct drm_encoder_helper_funcs *help;
3985 struct drm_encoder *encoder;
3986
3987 encoder = outp->encoder;
3988 help = encoder->helper_private;
3989
3990 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
3991 outp->clr.mask, outp->set.mask);
3992
3993 if (outp->clr.mask) {
3994 help->disable(encoder);
3995 interlock_core |= 1;
3996 if (outp->flush_disable) {
3997 nv50_disp_atomic_commit_core(drm, interlock_chan);
3998 interlock_core = 0;
3999 interlock_chan = 0;
4000 }
4001 }
4002 }
4003
4004 /* Flush disable. */
4005 if (interlock_core) {
4006 if (atom->flush_disable) {
4007 nv50_disp_atomic_commit_core(drm, interlock_chan);
4008 interlock_core = 0;
4009 interlock_chan = 0;
4010 }
4011 }
4012
4013 /* Update output path(s). */
4014 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4015 const struct drm_encoder_helper_funcs *help;
4016 struct drm_encoder *encoder;
4017
4018 encoder = outp->encoder;
4019 help = encoder->helper_private;
4020
4021 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
4022 outp->set.mask, outp->clr.mask);
4023
4024 if (outp->set.mask) {
4025 help->enable(encoder);
4026 interlock_core = 1;
4027 }
4028
4029 list_del(&outp->head);
4030 kfree(outp);
4031 }
4032
4033 /* Update head(s). */
4034 for_each_crtc_in_state(state, crtc, crtc_state, i) {
4035 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
4036 struct nv50_head *head = nv50_head(crtc);
4037
4038 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
4039 asyh->set.mask, asyh->clr.mask);
4040
4041 if (asyh->set.mask) {
4042 nv50_head_flush_set(head, asyh);
4043 interlock_core = 1;
4044 }
4045 }
4046
4047 /* Update plane(s). */
4048 for_each_plane_in_state(state, plane, plane_state, i) {
4049 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4050 struct nv50_wndw *wndw = nv50_wndw(plane);
4051
4052 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
4053 asyw->set.mask, asyw->clr.mask);
4054 if ( !asyw->set.mask &&
4055 (!asyw->clr.mask || atom->flush_disable))
4056 continue;
4057
4058 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4059 }
4060
4061 /* Flush update. */
4062 if (interlock_core) {
4063 if (!interlock_chan && atom->state.legacy_cursor_update) {
4064 u32 *push = evo_wait(&disp->mast, 2);
4065 if (push) {
4066 evo_mthd(push, 0x0080, 1);
4067 evo_data(push, 0x00000000);
4068 evo_kick(push, &disp->mast);
4069 }
4070 } else {
4071 nv50_disp_atomic_commit_core(drm, interlock_chan);
4072 }
4073 }
4074
4075 if (atom->lock_core)
4076 mutex_unlock(&disp->mutex);
4077
4078 /* Wait for HW to signal completion. */
4079 for_each_plane_in_state(state, plane, plane_state, i) {
4080 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4081 struct nv50_wndw *wndw = nv50_wndw(plane);
4082 int ret = nv50_wndw_wait_armed(wndw, asyw);
4083 if (ret)
4084 NV_ERROR(drm, "%s: timeout\n", plane->name);
4085 }
4086
4087 for_each_crtc_in_state(state, crtc, crtc_state, i) {
4088 if (crtc->state->event) {
4089 unsigned long flags;
4090 spin_lock_irqsave(&crtc->dev->event_lock, flags);
4091 drm_crtc_send_vblank_event(crtc, crtc->state->event);
4092 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4093 crtc->state->event = NULL;
4094 }
4095 }
4096
4097 drm_atomic_helper_commit_hw_done(state);
4098 drm_atomic_helper_cleanup_planes(dev, state);
4099 drm_atomic_helper_commit_cleanup_done(state);
4100 drm_atomic_state_put(state);
4101 }
4102
4103 static void
4104 nv50_disp_atomic_commit_work(struct work_struct *work)
4105 {
4106 struct drm_atomic_state *state =
4107 container_of(work, typeof(*state), commit_work);
4108 nv50_disp_atomic_commit_tail(state);
4109 }
4110
4111 static int
4112 nv50_disp_atomic_commit(struct drm_device *dev,
4113 struct drm_atomic_state *state, bool nonblock)
4114 {
4115 struct nouveau_drm *drm = nouveau_drm(dev);
4116 struct nv50_disp *disp = nv50_disp(dev);
4117 struct drm_plane_state *plane_state;
4118 struct drm_plane *plane;
4119 struct drm_crtc *crtc;
4120 bool active = false;
4121 int ret, i;
4122
4123 ret = pm_runtime_get_sync(dev->dev);
4124 if (ret < 0 && ret != -EACCES)
4125 return ret;
4126
4127 ret = drm_atomic_helper_setup_commit(state, nonblock);
4128 if (ret)
4129 goto done;
4130
4131 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4132
4133 ret = drm_atomic_helper_prepare_planes(dev, state);
4134 if (ret)
4135 goto done;
4136
4137 if (!nonblock) {
4138 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4139 if (ret)
4140 goto done;
4141 }
4142
4143 for_each_plane_in_state(state, plane, plane_state, i) {
4144 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state);
4145 struct nv50_wndw *wndw = nv50_wndw(plane);
4146 if (asyw->set.image) {
4147 asyw->ntfy.handle = wndw->dmac->sync.handle;
4148 asyw->ntfy.offset = wndw->ntfy;
4149 asyw->ntfy.awaken = false;
4150 asyw->set.ntfy = true;
4151 nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4152 wndw->ntfy ^= 0x10;
4153 }
4154 }
4155
4156 drm_atomic_helper_swap_state(state, true);
4157 drm_atomic_state_get(state);
4158
4159 if (nonblock)
4160 queue_work(system_unbound_wq, &state->commit_work);
4161 else
4162 nv50_disp_atomic_commit_tail(state);
4163
4164 drm_for_each_crtc(crtc, dev) {
4165 if (crtc->state->enable) {
4166 if (!drm->have_disp_power_ref) {
4167 drm->have_disp_power_ref = true;
4168 return ret;
4169 }
4170 active = true;
4171 break;
4172 }
4173 }
4174
4175 if (!active && drm->have_disp_power_ref) {
4176 pm_runtime_put_autosuspend(dev->dev);
4177 drm->have_disp_power_ref = false;
4178 }
4179
4180 done:
4181 pm_runtime_put_autosuspend(dev->dev);
4182 return ret;
4183 }
4184
4185 static struct nv50_outp_atom *
4186 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4187 {
4188 struct nv50_outp_atom *outp;
4189
4190 list_for_each_entry(outp, &atom->outp, head) {
4191 if (outp->encoder == encoder)
4192 return outp;
4193 }
4194
4195 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4196 if (!outp)
4197 return ERR_PTR(-ENOMEM);
4198
4199 list_add(&outp->head, &atom->outp);
4200 outp->encoder = encoder;
4201 return outp;
4202 }
4203
4204 static int
4205 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4206 struct drm_connector *connector)
4207 {
4208 struct drm_encoder *encoder = connector->state->best_encoder;
4209 struct drm_crtc_state *crtc_state;
4210 struct drm_crtc *crtc;
4211 struct nv50_outp_atom *outp;
4212
4213 if (!(crtc = connector->state->crtc))
4214 return 0;
4215
4216 crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4217 if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4218 outp = nv50_disp_outp_atomic_add(atom, encoder);
4219 if (IS_ERR(outp))
4220 return PTR_ERR(outp);
4221
4222 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4223 outp->flush_disable = true;
4224 atom->flush_disable = true;
4225 }
4226 outp->clr.ctrl = true;
4227 atom->lock_core = true;
4228 }
4229
4230 return 0;
4231 }
4232
4233 static int
4234 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4235 struct drm_connector_state *connector_state)
4236 {
4237 struct drm_encoder *encoder = connector_state->best_encoder;
4238 struct drm_crtc_state *crtc_state;
4239 struct drm_crtc *crtc;
4240 struct nv50_outp_atom *outp;
4241
4242 if (!(crtc = connector_state->crtc))
4243 return 0;
4244
4245 crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4246 if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4247 outp = nv50_disp_outp_atomic_add(atom, encoder);
4248 if (IS_ERR(outp))
4249 return PTR_ERR(outp);
4250
4251 outp->set.ctrl = true;
4252 atom->lock_core = true;
4253 }
4254
4255 return 0;
4256 }
4257
4258 static int
4259 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4260 {
4261 struct nv50_atom *atom = nv50_atom(state);
4262 struct drm_connector_state *connector_state;
4263 struct drm_connector *connector;
4264 int ret, i;
4265
4266 ret = drm_atomic_helper_check(dev, state);
4267 if (ret)
4268 return ret;
4269
4270 for_each_connector_in_state(state, connector, connector_state, i) {
4271 ret = nv50_disp_outp_atomic_check_clr(atom, connector);
4272 if (ret)
4273 return ret;
4274
4275 ret = nv50_disp_outp_atomic_check_set(atom, connector_state);
4276 if (ret)
4277 return ret;
4278 }
4279
4280 return 0;
4281 }
4282
4283 static void
4284 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4285 {
4286 struct nv50_atom *atom = nv50_atom(state);
4287 struct nv50_outp_atom *outp, *outt;
4288
4289 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4290 list_del(&outp->head);
4291 kfree(outp);
4292 }
4293
4294 drm_atomic_state_default_clear(state);
4295 }
4296
4297 static void
4298 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4299 {
4300 struct nv50_atom *atom = nv50_atom(state);
4301 drm_atomic_state_default_release(&atom->state);
4302 kfree(atom);
4303 }
4304
4305 static struct drm_atomic_state *
4306 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4307 {
4308 struct nv50_atom *atom;
4309 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4310 drm_atomic_state_init(dev, &atom->state) < 0) {
4311 kfree(atom);
4312 return NULL;
4313 }
4314 INIT_LIST_HEAD(&atom->outp);
4315 return &atom->state;
4316 }
4317
4318 static const struct drm_mode_config_funcs
4319 nv50_disp_func = {
4320 .fb_create = nouveau_user_framebuffer_create,
4321 .output_poll_changed = nouveau_fbcon_output_poll_changed,
4322 .atomic_check = nv50_disp_atomic_check,
4323 .atomic_commit = nv50_disp_atomic_commit,
4324 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4325 .atomic_state_clear = nv50_disp_atomic_state_clear,
4326 .atomic_state_free = nv50_disp_atomic_state_free,
4327 };
4328
4329 /******************************************************************************
4330 * Init
4331 *****************************************************************************/
4332
4333 void
4334 nv50_display_fini(struct drm_device *dev)
4335 {
4336 struct nouveau_encoder *nv_encoder;
4337 struct drm_encoder *encoder;
4338 struct drm_plane *plane;
4339
4340 drm_for_each_plane(plane, dev) {
4341 struct nv50_wndw *wndw = nv50_wndw(plane);
4342 if (plane->funcs != &nv50_wndw)
4343 continue;
4344 nv50_wndw_fini(wndw);
4345 }
4346
4347 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4348 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4349 nv_encoder = nouveau_encoder(encoder);
4350 nv50_mstm_fini(nv_encoder->dp.mstm);
4351 }
4352 }
4353 }
4354
4355 int
4356 nv50_display_init(struct drm_device *dev)
4357 {
4358 struct drm_encoder *encoder;
4359 struct drm_plane *plane;
4360 struct drm_crtc *crtc;
4361 u32 *push;
4362
4363 push = evo_wait(nv50_mast(dev), 32);
4364 if (!push)
4365 return -EBUSY;
4366
4367 evo_mthd(push, 0x0088, 1);
4368 evo_data(push, nv50_mast(dev)->base.sync.handle);
4369 evo_kick(push, nv50_mast(dev));
4370
4371 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4372 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4373 const struct drm_encoder_helper_funcs *help;
4374 struct nouveau_encoder *nv_encoder;
4375
4376 nv_encoder = nouveau_encoder(encoder);
4377 help = encoder->helper_private;
4378 if (help && help->dpms)
4379 help->dpms(encoder, DRM_MODE_DPMS_ON);
4380
4381 nv50_mstm_init(nv_encoder->dp.mstm);
4382 }
4383 }
4384
4385 drm_for_each_crtc(crtc, dev) {
4386 nv50_head_lut_load(crtc);
4387 }
4388
4389 drm_for_each_plane(plane, dev) {
4390 struct nv50_wndw *wndw = nv50_wndw(plane);
4391 if (plane->funcs != &nv50_wndw)
4392 continue;
4393 nv50_wndw_init(wndw);
4394 }
4395
4396 return 0;
4397 }
4398
4399 void
4400 nv50_display_destroy(struct drm_device *dev)
4401 {
4402 struct nv50_disp *disp = nv50_disp(dev);
4403
4404 nv50_dmac_destroy(&disp->mast.base, disp->disp);
4405
4406 nouveau_bo_unmap(disp->sync);
4407 if (disp->sync)
4408 nouveau_bo_unpin(disp->sync);
4409 nouveau_bo_ref(NULL, &disp->sync);
4410
4411 nouveau_display(dev)->priv = NULL;
4412 kfree(disp);
4413 }
4414
4415 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4416 static int nouveau_atomic = 0;
4417 module_param_named(atomic, nouveau_atomic, int, 0400);
4418
4419 int
4420 nv50_display_create(struct drm_device *dev)
4421 {
4422 struct nvif_device *device = &nouveau_drm(dev)->device;
4423 struct nouveau_drm *drm = nouveau_drm(dev);
4424 struct dcb_table *dcb = &drm->vbios.dcb;
4425 struct drm_connector *connector, *tmp;
4426 struct nv50_disp *disp;
4427 struct dcb_output *dcbe;
4428 int crtcs, ret, i;
4429
4430 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4431 if (!disp)
4432 return -ENOMEM;
4433
4434 mutex_init(&disp->mutex);
4435
4436 nouveau_display(dev)->priv = disp;
4437 nouveau_display(dev)->dtor = nv50_display_destroy;
4438 nouveau_display(dev)->init = nv50_display_init;
4439 nouveau_display(dev)->fini = nv50_display_fini;
4440 disp->disp = &nouveau_display(dev)->disp;
4441 dev->mode_config.funcs = &nv50_disp_func;
4442 if (nouveau_atomic)
4443 dev->driver->driver_features |= DRIVER_ATOMIC;
4444
4445 /* small shared memory area we use for notifiers and semaphores */
4446 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4447 0, 0x0000, NULL, NULL, &disp->sync);
4448 if (!ret) {
4449 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4450 if (!ret) {
4451 ret = nouveau_bo_map(disp->sync);
4452 if (ret)
4453 nouveau_bo_unpin(disp->sync);
4454 }
4455 if (ret)
4456 nouveau_bo_ref(NULL, &disp->sync);
4457 }
4458
4459 if (ret)
4460 goto out;
4461
4462 /* allocate master evo channel */
4463 ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4464 &disp->mast);
4465 if (ret)
4466 goto out;
4467
4468 /* create crtc objects to represent the hw heads */
4469 if (disp->disp->oclass >= GF110_DISP)
4470 crtcs = nvif_rd32(&device->object, 0x022448);
4471 else
4472 crtcs = 2;
4473
4474 for (i = 0; i < crtcs; i++) {
4475 ret = nv50_head_create(dev, i);
4476 if (ret)
4477 goto out;
4478 }
4479
4480 /* create encoder/connector objects based on VBIOS DCB table */
4481 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4482 connector = nouveau_connector_create(dev, dcbe->connector);
4483 if (IS_ERR(connector))
4484 continue;
4485
4486 if (dcbe->location == DCB_LOC_ON_CHIP) {
4487 switch (dcbe->type) {
4488 case DCB_OUTPUT_TMDS:
4489 case DCB_OUTPUT_LVDS:
4490 case DCB_OUTPUT_DP:
4491 ret = nv50_sor_create(connector, dcbe);
4492 break;
4493 case DCB_OUTPUT_ANALOG:
4494 ret = nv50_dac_create(connector, dcbe);
4495 break;
4496 default:
4497 ret = -ENODEV;
4498 break;
4499 }
4500 } else {
4501 ret = nv50_pior_create(connector, dcbe);
4502 }
4503
4504 if (ret) {
4505 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4506 dcbe->location, dcbe->type,
4507 ffs(dcbe->or) - 1, ret);
4508 ret = 0;
4509 }
4510 }
4511
4512 /* cull any connectors we created that don't have an encoder */
4513 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4514 if (connector->encoder_ids[0])
4515 continue;
4516
4517 NV_WARN(drm, "%s has no encoders, removing\n",
4518 connector->name);
4519 connector->funcs->destroy(connector);
4520 }
4521
4522 out:
4523 if (ret)
4524 nv50_display_destroy(dev);
4525 return ret;
4526 }
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