2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_dp_helper.h>
32 #include <drm/drm_fb_helper.h>
33 #include <drm/drm_plane_helper.h>
35 #include <nvif/class.h>
36 #include <nvif/cl0002.h>
37 #include <nvif/cl5070.h>
38 #include <nvif/cl507a.h>
39 #include <nvif/cl507b.h>
40 #include <nvif/cl507c.h>
41 #include <nvif/cl507d.h>
42 #include <nvif/cl507e.h>
43 #include <nvif/event.h>
45 #include "nouveau_drv.h"
46 #include "nouveau_dma.h"
47 #include "nouveau_gem.h"
48 #include "nouveau_connector.h"
49 #include "nouveau_encoder.h"
50 #include "nouveau_crtc.h"
51 #include "nouveau_fence.h"
52 #include "nouveau_fbcon.h"
53 #include "nv50_display.h"
57 #define EVO_MASTER (0x00)
58 #define EVO_FLIP(c) (0x01 + (c))
59 #define EVO_OVLY(c) (0x05 + (c))
60 #define EVO_OIMM(c) (0x09 + (c))
61 #define EVO_CURS(c) (0x0d + (c))
63 /* offsets in shared sync bo of various structures */
64 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
65 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
66 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
67 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
68 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
69 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
71 /******************************************************************************
73 *****************************************************************************/
74 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
77 struct drm_atomic_state state
;
79 struct list_head outp
;
84 struct nv50_outp_atom
{
85 struct list_head head
;
87 struct drm_encoder
*encoder
;
105 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
107 struct nv50_head_atom
{
108 struct drm_crtc_state state
;
117 struct nv50_head_mode
{
214 static inline struct nv50_head_atom
*
215 nv50_head_atom_get(struct drm_atomic_state
*state
, struct drm_crtc
*crtc
)
217 struct drm_crtc_state
*statec
= drm_atomic_get_crtc_state(state
, crtc
);
219 return (void *)statec
;
220 return nv50_head_atom(statec
);
223 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
225 struct nv50_wndw_atom
{
226 struct drm_plane_state state
;
229 struct drm_rect clip
;
290 /******************************************************************************
292 *****************************************************************************/
295 struct nvif_object user
;
296 struct nvif_device
*device
;
300 nv50_chan_create(struct nvif_device
*device
, struct nvif_object
*disp
,
301 const s32
*oclass
, u8 head
, void *data
, u32 size
,
302 struct nv50_chan
*chan
)
304 struct nvif_sclass
*sclass
;
307 chan
->device
= device
;
309 ret
= n
= nvif_object_sclass_get(disp
, &sclass
);
314 for (i
= 0; i
< n
; i
++) {
315 if (sclass
[i
].oclass
== oclass
[0]) {
316 ret
= nvif_object_init(disp
, 0, oclass
[0],
317 data
, size
, &chan
->user
);
319 nvif_object_map(&chan
->user
);
320 nvif_object_sclass_put(&sclass
);
327 nvif_object_sclass_put(&sclass
);
332 nv50_chan_destroy(struct nv50_chan
*chan
)
334 nvif_object_fini(&chan
->user
);
337 /******************************************************************************
339 *****************************************************************************/
342 struct nv50_chan base
;
346 nv50_pioc_destroy(struct nv50_pioc
*pioc
)
348 nv50_chan_destroy(&pioc
->base
);
352 nv50_pioc_create(struct nvif_device
*device
, struct nvif_object
*disp
,
353 const s32
*oclass
, u8 head
, void *data
, u32 size
,
354 struct nv50_pioc
*pioc
)
356 return nv50_chan_create(device
, disp
, oclass
, head
, data
, size
,
360 /******************************************************************************
362 *****************************************************************************/
365 struct nv50_pioc base
;
369 nv50_oimm_create(struct nvif_device
*device
, struct nvif_object
*disp
,
370 int head
, struct nv50_oimm
*oimm
)
372 struct nv50_disp_cursor_v0 args
= {
375 static const s32 oclass
[] = {
384 return nv50_pioc_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
388 /******************************************************************************
390 *****************************************************************************/
392 struct nv50_dmac_ctxdma
{
393 struct list_head head
;
394 struct nvif_object object
;
398 struct nv50_chan base
;
402 struct nvif_object sync
;
403 struct nvif_object vram
;
404 struct list_head ctxdma
;
406 /* Protects against concurrent pushbuf access to this channel, lock is
407 * grabbed by evo_wait (if the pushbuf reservation is successful) and
408 * dropped again by evo_kick. */
413 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma
*ctxdma
)
415 nvif_object_fini(&ctxdma
->object
);
416 list_del(&ctxdma
->head
);
420 static struct nv50_dmac_ctxdma
*
421 nv50_dmac_ctxdma_new(struct nv50_dmac
*dmac
, struct nouveau_framebuffer
*fb
)
423 struct nouveau_drm
*drm
= nouveau_drm(fb
->base
.dev
);
424 struct nv50_dmac_ctxdma
*ctxdma
;
425 const u8 kind
= (fb
->nvbo
->tile_flags
& 0x0000ff00) >> 8;
426 const u32 handle
= 0xfb000000 | kind
;
428 struct nv_dma_v0 base
;
430 struct nv50_dma_v0 nv50
;
431 struct gf100_dma_v0 gf100
;
432 struct gf119_dma_v0 gf119
;
435 u32 argc
= sizeof(args
.base
);
438 list_for_each_entry(ctxdma
, &dmac
->ctxdma
, head
) {
439 if (ctxdma
->object
.handle
== handle
)
443 if (!(ctxdma
= kzalloc(sizeof(*ctxdma
), GFP_KERNEL
)))
444 return ERR_PTR(-ENOMEM
);
445 list_add(&ctxdma
->head
, &dmac
->ctxdma
);
447 args
.base
.target
= NV_DMA_V0_TARGET_VRAM
;
448 args
.base
.access
= NV_DMA_V0_ACCESS_RDWR
;
450 args
.base
.limit
= drm
->device
.info
.ram_user
- 1;
452 if (drm
->device
.info
.chipset
< 0x80) {
453 args
.nv50
.part
= NV50_DMA_V0_PART_256
;
454 argc
+= sizeof(args
.nv50
);
456 if (drm
->device
.info
.chipset
< 0xc0) {
457 args
.nv50
.part
= NV50_DMA_V0_PART_256
;
458 args
.nv50
.kind
= kind
;
459 argc
+= sizeof(args
.nv50
);
461 if (drm
->device
.info
.chipset
< 0xd0) {
462 args
.gf100
.kind
= kind
;
463 argc
+= sizeof(args
.gf100
);
465 args
.gf119
.page
= GF119_DMA_V0_PAGE_LP
;
466 args
.gf119
.kind
= kind
;
467 argc
+= sizeof(args
.gf119
);
470 ret
= nvif_object_init(&dmac
->base
.user
, handle
, NV_DMA_IN_MEMORY
,
471 &args
, argc
, &ctxdma
->object
);
473 nv50_dmac_ctxdma_del(ctxdma
);
481 nv50_dmac_destroy(struct nv50_dmac
*dmac
, struct nvif_object
*disp
)
483 struct nvif_device
*device
= dmac
->base
.device
;
484 struct nv50_dmac_ctxdma
*ctxdma
, *ctxtmp
;
486 list_for_each_entry_safe(ctxdma
, ctxtmp
, &dmac
->ctxdma
, head
) {
487 nv50_dmac_ctxdma_del(ctxdma
);
490 nvif_object_fini(&dmac
->vram
);
491 nvif_object_fini(&dmac
->sync
);
493 nv50_chan_destroy(&dmac
->base
);
496 struct device
*dev
= nvxx_device(device
)->dev
;
497 dma_free_coherent(dev
, PAGE_SIZE
, dmac
->ptr
, dmac
->handle
);
502 nv50_dmac_create(struct nvif_device
*device
, struct nvif_object
*disp
,
503 const s32
*oclass
, u8 head
, void *data
, u32 size
, u64 syncbuf
,
504 struct nv50_dmac
*dmac
)
506 struct nv50_disp_core_channel_dma_v0
*args
= data
;
507 struct nvif_object pushbuf
;
510 mutex_init(&dmac
->lock
);
512 dmac
->ptr
= dma_alloc_coherent(nvxx_device(device
)->dev
, PAGE_SIZE
,
513 &dmac
->handle
, GFP_KERNEL
);
517 ret
= nvif_object_init(&device
->object
, 0, NV_DMA_FROM_MEMORY
,
518 &(struct nv_dma_v0
) {
519 .target
= NV_DMA_V0_TARGET_PCI_US
,
520 .access
= NV_DMA_V0_ACCESS_RD
,
521 .start
= dmac
->handle
+ 0x0000,
522 .limit
= dmac
->handle
+ 0x0fff,
523 }, sizeof(struct nv_dma_v0
), &pushbuf
);
527 args
->pushbuf
= nvif_handle(&pushbuf
);
529 ret
= nv50_chan_create(device
, disp
, oclass
, head
, data
, size
,
531 nvif_object_fini(&pushbuf
);
535 ret
= nvif_object_init(&dmac
->base
.user
, 0xf0000000, NV_DMA_IN_MEMORY
,
536 &(struct nv_dma_v0
) {
537 .target
= NV_DMA_V0_TARGET_VRAM
,
538 .access
= NV_DMA_V0_ACCESS_RDWR
,
539 .start
= syncbuf
+ 0x0000,
540 .limit
= syncbuf
+ 0x0fff,
541 }, sizeof(struct nv_dma_v0
),
546 ret
= nvif_object_init(&dmac
->base
.user
, 0xf0000001, NV_DMA_IN_MEMORY
,
547 &(struct nv_dma_v0
) {
548 .target
= NV_DMA_V0_TARGET_VRAM
,
549 .access
= NV_DMA_V0_ACCESS_RDWR
,
551 .limit
= device
->info
.ram_user
- 1,
552 }, sizeof(struct nv_dma_v0
),
557 INIT_LIST_HEAD(&dmac
->ctxdma
);
561 /******************************************************************************
563 *****************************************************************************/
566 struct nv50_dmac base
;
570 nv50_core_create(struct nvif_device
*device
, struct nvif_object
*disp
,
571 u64 syncbuf
, struct nv50_mast
*core
)
573 struct nv50_disp_core_channel_dma_v0 args
= {
574 .pushbuf
= 0xb0007d00,
576 static const s32 oclass
[] = {
577 GP102_DISP_CORE_CHANNEL_DMA
,
578 GP100_DISP_CORE_CHANNEL_DMA
,
579 GM200_DISP_CORE_CHANNEL_DMA
,
580 GM107_DISP_CORE_CHANNEL_DMA
,
581 GK110_DISP_CORE_CHANNEL_DMA
,
582 GK104_DISP_CORE_CHANNEL_DMA
,
583 GF110_DISP_CORE_CHANNEL_DMA
,
584 GT214_DISP_CORE_CHANNEL_DMA
,
585 GT206_DISP_CORE_CHANNEL_DMA
,
586 GT200_DISP_CORE_CHANNEL_DMA
,
587 G82_DISP_CORE_CHANNEL_DMA
,
588 NV50_DISP_CORE_CHANNEL_DMA
,
592 return nv50_dmac_create(device
, disp
, oclass
, 0, &args
, sizeof(args
),
593 syncbuf
, &core
->base
);
596 /******************************************************************************
598 *****************************************************************************/
601 struct nv50_dmac base
;
607 nv50_base_create(struct nvif_device
*device
, struct nvif_object
*disp
,
608 int head
, u64 syncbuf
, struct nv50_sync
*base
)
610 struct nv50_disp_base_channel_dma_v0 args
= {
611 .pushbuf
= 0xb0007c00 | head
,
614 static const s32 oclass
[] = {
615 GK110_DISP_BASE_CHANNEL_DMA
,
616 GK104_DISP_BASE_CHANNEL_DMA
,
617 GF110_DISP_BASE_CHANNEL_DMA
,
618 GT214_DISP_BASE_CHANNEL_DMA
,
619 GT200_DISP_BASE_CHANNEL_DMA
,
620 G82_DISP_BASE_CHANNEL_DMA
,
621 NV50_DISP_BASE_CHANNEL_DMA
,
625 return nv50_dmac_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
626 syncbuf
, &base
->base
);
629 /******************************************************************************
631 *****************************************************************************/
634 struct nv50_dmac base
;
638 nv50_ovly_create(struct nvif_device
*device
, struct nvif_object
*disp
,
639 int head
, u64 syncbuf
, struct nv50_ovly
*ovly
)
641 struct nv50_disp_overlay_channel_dma_v0 args
= {
642 .pushbuf
= 0xb0007e00 | head
,
645 static const s32 oclass
[] = {
646 GK104_DISP_OVERLAY_CONTROL_DMA
,
647 GF110_DISP_OVERLAY_CONTROL_DMA
,
648 GT214_DISP_OVERLAY_CHANNEL_DMA
,
649 GT200_DISP_OVERLAY_CHANNEL_DMA
,
650 G82_DISP_OVERLAY_CHANNEL_DMA
,
651 NV50_DISP_OVERLAY_CHANNEL_DMA
,
655 return nv50_dmac_create(device
, disp
, oclass
, head
, &args
, sizeof(args
),
656 syncbuf
, &ovly
->base
);
660 struct nouveau_crtc base
;
661 struct nv50_ovly ovly
;
662 struct nv50_oimm oimm
;
665 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
666 #define nv50_ovly(c) (&nv50_head(c)->ovly)
667 #define nv50_oimm(c) (&nv50_head(c)->oimm)
668 #define nv50_chan(c) (&(c)->base.base)
669 #define nv50_vers(c) nv50_chan(c)->user.oclass
672 struct nvif_object
*disp
;
673 struct nv50_mast mast
;
675 struct nouveau_bo
*sync
;
680 static struct nv50_disp
*
681 nv50_disp(struct drm_device
*dev
)
683 return nouveau_display(dev
)->priv
;
686 #define nv50_mast(d) (&nv50_disp(d)->mast)
688 /******************************************************************************
689 * EVO channel helpers
690 *****************************************************************************/
692 evo_wait(void *evoc
, int nr
)
694 struct nv50_dmac
*dmac
= evoc
;
695 struct nvif_device
*device
= dmac
->base
.device
;
696 u32 put
= nvif_rd32(&dmac
->base
.user
, 0x0000) / 4;
698 mutex_lock(&dmac
->lock
);
699 if (put
+ nr
>= (PAGE_SIZE
/ 4) - 8) {
700 dmac
->ptr
[put
] = 0x20000000;
702 nvif_wr32(&dmac
->base
.user
, 0x0000, 0x00000000);
703 if (nvif_msec(device
, 2000,
704 if (!nvif_rd32(&dmac
->base
.user
, 0x0004))
707 mutex_unlock(&dmac
->lock
);
708 printk(KERN_ERR
"nouveau: evo channel stalled\n");
715 return dmac
->ptr
+ put
;
719 evo_kick(u32
*push
, void *evoc
)
721 struct nv50_dmac
*dmac
= evoc
;
722 nvif_wr32(&dmac
->base
.user
, 0x0000, (push
- dmac
->ptr
) << 2);
723 mutex_unlock(&dmac
->lock
);
726 #define evo_mthd(p,m,s) do { \
727 const u32 _m = (m), _s = (s); \
728 if (drm_debug & DRM_UT_KMS) \
729 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \
730 *((p)++) = ((_s << 18) | _m); \
733 #define evo_data(p,d) do { \
734 const u32 _d = (d); \
735 if (drm_debug & DRM_UT_KMS) \
736 printk(KERN_ERR "\t%08x\n", _d); \
740 /******************************************************************************
742 *****************************************************************************/
743 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
746 const struct nv50_wndw_func
*func
;
747 struct nv50_dmac
*dmac
;
749 struct drm_plane plane
;
751 struct nvif_notify notify
;
757 struct nv50_wndw_func
{
758 void *(*dtor
)(struct nv50_wndw
*);
759 int (*acquire
)(struct nv50_wndw
*, struct nv50_wndw_atom
*asyw
,
760 struct nv50_head_atom
*asyh
);
761 void (*release
)(struct nv50_wndw
*, struct nv50_wndw_atom
*asyw
,
762 struct nv50_head_atom
*asyh
);
763 void (*prepare
)(struct nv50_wndw
*, struct nv50_head_atom
*asyh
,
764 struct nv50_wndw_atom
*asyw
);
766 void (*sema_set
)(struct nv50_wndw
*, struct nv50_wndw_atom
*);
767 void (*sema_clr
)(struct nv50_wndw
*);
768 void (*ntfy_set
)(struct nv50_wndw
*, struct nv50_wndw_atom
*);
769 void (*ntfy_clr
)(struct nv50_wndw
*);
770 int (*ntfy_wait_begun
)(struct nv50_wndw
*, struct nv50_wndw_atom
*);
771 void (*image_set
)(struct nv50_wndw
*, struct nv50_wndw_atom
*);
772 void (*image_clr
)(struct nv50_wndw
*);
773 void (*lut
)(struct nv50_wndw
*, struct nv50_wndw_atom
*);
774 void (*point
)(struct nv50_wndw
*, struct nv50_wndw_atom
*);
776 u32 (*update
)(struct nv50_wndw
*, u32 interlock
);
780 nv50_wndw_wait_armed(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
783 return wndw
->func
->ntfy_wait_begun(wndw
, asyw
);
788 nv50_wndw_flush_clr(struct nv50_wndw
*wndw
, u32 interlock
, bool flush
,
789 struct nv50_wndw_atom
*asyw
)
791 if (asyw
->clr
.sema
&& (!asyw
->set
.sema
|| flush
))
792 wndw
->func
->sema_clr(wndw
);
793 if (asyw
->clr
.ntfy
&& (!asyw
->set
.ntfy
|| flush
))
794 wndw
->func
->ntfy_clr(wndw
);
795 if (asyw
->clr
.image
&& (!asyw
->set
.image
|| flush
))
796 wndw
->func
->image_clr(wndw
);
798 return flush
? wndw
->func
->update(wndw
, interlock
) : 0;
802 nv50_wndw_flush_set(struct nv50_wndw
*wndw
, u32 interlock
,
803 struct nv50_wndw_atom
*asyw
)
806 asyw
->image
.mode
= 0;
807 asyw
->image
.interval
= 1;
810 if (asyw
->set
.sema
) wndw
->func
->sema_set (wndw
, asyw
);
811 if (asyw
->set
.ntfy
) wndw
->func
->ntfy_set (wndw
, asyw
);
812 if (asyw
->set
.image
) wndw
->func
->image_set(wndw
, asyw
);
813 if (asyw
->set
.lut
) wndw
->func
->lut (wndw
, asyw
);
814 if (asyw
->set
.point
) wndw
->func
->point (wndw
, asyw
);
816 return wndw
->func
->update(wndw
, interlock
);
820 nv50_wndw_atomic_check_release(struct nv50_wndw
*wndw
,
821 struct nv50_wndw_atom
*asyw
,
822 struct nv50_head_atom
*asyh
)
824 struct nouveau_drm
*drm
= nouveau_drm(wndw
->plane
.dev
);
825 NV_ATOMIC(drm
, "%s release\n", wndw
->plane
.name
);
826 wndw
->func
->release(wndw
, asyw
, asyh
);
827 asyw
->ntfy
.handle
= 0;
828 asyw
->sema
.handle
= 0;
832 nv50_wndw_atomic_check_acquire(struct nv50_wndw
*wndw
,
833 struct nv50_wndw_atom
*asyw
,
834 struct nv50_head_atom
*asyh
)
836 struct nouveau_framebuffer
*fb
= nouveau_framebuffer(asyw
->state
.fb
);
837 struct nouveau_drm
*drm
= nouveau_drm(wndw
->plane
.dev
);
840 NV_ATOMIC(drm
, "%s acquire\n", wndw
->plane
.name
);
843 asyw
->clip
.x2
= asyh
->state
.mode
.hdisplay
;
844 asyw
->clip
.y2
= asyh
->state
.mode
.vdisplay
;
846 asyw
->image
.w
= fb
->base
.width
;
847 asyw
->image
.h
= fb
->base
.height
;
848 asyw
->image
.kind
= (fb
->nvbo
->tile_flags
& 0x0000ff00) >> 8;
849 if (asyw
->image
.kind
) {
850 asyw
->image
.layout
= 0;
851 if (drm
->device
.info
.chipset
>= 0xc0)
852 asyw
->image
.block
= fb
->nvbo
->tile_mode
>> 4;
854 asyw
->image
.block
= fb
->nvbo
->tile_mode
;
855 asyw
->image
.pitch
= (fb
->base
.pitches
[0] / 4) << 4;
857 asyw
->image
.layout
= 1;
858 asyw
->image
.block
= 0;
859 asyw
->image
.pitch
= fb
->base
.pitches
[0];
862 ret
= wndw
->func
->acquire(wndw
, asyw
, asyh
);
866 if (asyw
->set
.image
) {
867 if (!(asyw
->image
.mode
= asyw
->interval
? 0 : 1))
868 asyw
->image
.interval
= asyw
->interval
;
870 asyw
->image
.interval
= 0;
877 nv50_wndw_atomic_check(struct drm_plane
*plane
, struct drm_plane_state
*state
)
879 struct nouveau_drm
*drm
= nouveau_drm(plane
->dev
);
880 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
881 struct nv50_wndw_atom
*armw
= nv50_wndw_atom(wndw
->plane
.state
);
882 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(state
);
883 struct nv50_head_atom
*harm
= NULL
, *asyh
= NULL
;
884 bool varm
= false, asyv
= false, asym
= false;
887 NV_ATOMIC(drm
, "%s atomic_check\n", plane
->name
);
888 if (asyw
->state
.crtc
) {
889 asyh
= nv50_head_atom_get(asyw
->state
.state
, asyw
->state
.crtc
);
891 return PTR_ERR(asyh
);
892 asym
= drm_atomic_crtc_needs_modeset(&asyh
->state
);
893 asyv
= asyh
->state
.active
;
896 if (armw
->state
.crtc
) {
897 harm
= nv50_head_atom_get(asyw
->state
.state
, armw
->state
.crtc
);
899 return PTR_ERR(harm
);
900 varm
= harm
->state
.crtc
->state
->active
;
904 asyw
->point
.x
= asyw
->state
.crtc_x
;
905 asyw
->point
.y
= asyw
->state
.crtc_y
;
906 if (memcmp(&armw
->point
, &asyw
->point
, sizeof(asyw
->point
)))
907 asyw
->set
.point
= true;
909 if (!varm
|| asym
|| armw
->state
.fb
!= asyw
->state
.fb
) {
910 ret
= nv50_wndw_atomic_check_acquire(wndw
, asyw
, asyh
);
916 nv50_wndw_atomic_check_release(wndw
, asyw
, harm
);
922 asyw
->clr
.ntfy
= armw
->ntfy
.handle
!= 0;
923 asyw
->clr
.sema
= armw
->sema
.handle
!= 0;
924 if (wndw
->func
->image_clr
)
925 asyw
->clr
.image
= armw
->image
.handle
!= 0;
926 asyw
->set
.lut
= wndw
->func
->lut
&& asyv
;
933 nv50_wndw_cleanup_fb(struct drm_plane
*plane
, struct drm_plane_state
*old_state
)
935 struct nouveau_framebuffer
*fb
= nouveau_framebuffer(old_state
->fb
);
936 struct nouveau_drm
*drm
= nouveau_drm(plane
->dev
);
938 NV_ATOMIC(drm
, "%s cleanup: %p\n", plane
->name
, old_state
->fb
);
942 nouveau_bo_unpin(fb
->nvbo
);
946 nv50_wndw_prepare_fb(struct drm_plane
*plane
, struct drm_plane_state
*state
)
948 struct nouveau_framebuffer
*fb
= nouveau_framebuffer(state
->fb
);
949 struct nouveau_drm
*drm
= nouveau_drm(plane
->dev
);
950 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
951 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(state
);
952 struct nv50_head_atom
*asyh
;
953 struct nv50_dmac_ctxdma
*ctxdma
;
956 NV_ATOMIC(drm
, "%s prepare: %p\n", plane
->name
, state
->fb
);
960 ret
= nouveau_bo_pin(fb
->nvbo
, TTM_PL_FLAG_VRAM
, true);
964 ctxdma
= nv50_dmac_ctxdma_new(wndw
->dmac
, fb
);
965 if (IS_ERR(ctxdma
)) {
966 nouveau_bo_unpin(fb
->nvbo
);
967 return PTR_ERR(ctxdma
);
970 asyw
->state
.fence
= reservation_object_get_excl_rcu(fb
->nvbo
->bo
.resv
);
971 asyw
->image
.handle
= ctxdma
->object
.handle
;
972 asyw
->image
.offset
= fb
->nvbo
->bo
.offset
;
974 if (wndw
->func
->prepare
) {
975 asyh
= nv50_head_atom_get(asyw
->state
.state
, asyw
->state
.crtc
);
977 return PTR_ERR(asyh
);
979 wndw
->func
->prepare(wndw
, asyh
, asyw
);
985 static const struct drm_plane_helper_funcs
987 .prepare_fb
= nv50_wndw_prepare_fb
,
988 .cleanup_fb
= nv50_wndw_cleanup_fb
,
989 .atomic_check
= nv50_wndw_atomic_check
,
993 nv50_wndw_atomic_destroy_state(struct drm_plane
*plane
,
994 struct drm_plane_state
*state
)
996 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(state
);
997 __drm_atomic_helper_plane_destroy_state(&asyw
->state
);
998 dma_fence_put(asyw
->state
.fence
);
1002 static struct drm_plane_state
*
1003 nv50_wndw_atomic_duplicate_state(struct drm_plane
*plane
)
1005 struct nv50_wndw_atom
*armw
= nv50_wndw_atom(plane
->state
);
1006 struct nv50_wndw_atom
*asyw
;
1007 if (!(asyw
= kmalloc(sizeof(*asyw
), GFP_KERNEL
)))
1009 __drm_atomic_helper_plane_duplicate_state(plane
, &asyw
->state
);
1010 asyw
->state
.fence
= NULL
;
1012 asyw
->sema
= armw
->sema
;
1013 asyw
->ntfy
= armw
->ntfy
;
1014 asyw
->image
= armw
->image
;
1015 asyw
->point
= armw
->point
;
1016 asyw
->lut
= armw
->lut
;
1019 return &asyw
->state
;
1023 nv50_wndw_reset(struct drm_plane
*plane
)
1025 struct nv50_wndw_atom
*asyw
;
1027 if (WARN_ON(!(asyw
= kzalloc(sizeof(*asyw
), GFP_KERNEL
))))
1031 plane
->funcs
->atomic_destroy_state(plane
, plane
->state
);
1032 plane
->state
= &asyw
->state
;
1033 plane
->state
->plane
= plane
;
1034 plane
->state
->rotation
= DRM_ROTATE_0
;
1038 nv50_wndw_destroy(struct drm_plane
*plane
)
1040 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
1042 nvif_notify_fini(&wndw
->notify
);
1043 data
= wndw
->func
->dtor(wndw
);
1044 drm_plane_cleanup(&wndw
->plane
);
1048 static const struct drm_plane_funcs
1050 .update_plane
= drm_atomic_helper_update_plane
,
1051 .disable_plane
= drm_atomic_helper_disable_plane
,
1052 .destroy
= nv50_wndw_destroy
,
1053 .reset
= nv50_wndw_reset
,
1054 .set_property
= drm_atomic_helper_plane_set_property
,
1055 .atomic_duplicate_state
= nv50_wndw_atomic_duplicate_state
,
1056 .atomic_destroy_state
= nv50_wndw_atomic_destroy_state
,
1060 nv50_wndw_fini(struct nv50_wndw
*wndw
)
1062 nvif_notify_put(&wndw
->notify
);
1066 nv50_wndw_init(struct nv50_wndw
*wndw
)
1068 nvif_notify_get(&wndw
->notify
);
1072 nv50_wndw_ctor(const struct nv50_wndw_func
*func
, struct drm_device
*dev
,
1073 enum drm_plane_type type
, const char *name
, int index
,
1074 struct nv50_dmac
*dmac
, const u32
*format
, int nformat
,
1075 struct nv50_wndw
*wndw
)
1082 ret
= drm_universal_plane_init(dev
, &wndw
->plane
, 0, &nv50_wndw
, format
,
1083 nformat
, type
, "%s-%d", name
, index
);
1087 drm_plane_helper_add(&wndw
->plane
, &nv50_wndw_helper
);
1091 /******************************************************************************
1093 *****************************************************************************/
1094 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1097 struct nv50_wndw wndw
;
1098 struct nvif_object chan
;
1102 nv50_curs_update(struct nv50_wndw
*wndw
, u32 interlock
)
1104 struct nv50_curs
*curs
= nv50_curs(wndw
);
1105 nvif_wr32(&curs
->chan
, 0x0080, 0x00000000);
1110 nv50_curs_point(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
1112 struct nv50_curs
*curs
= nv50_curs(wndw
);
1113 nvif_wr32(&curs
->chan
, 0x0084, (asyw
->point
.y
<< 16) | asyw
->point
.x
);
1117 nv50_curs_prepare(struct nv50_wndw
*wndw
, struct nv50_head_atom
*asyh
,
1118 struct nv50_wndw_atom
*asyw
)
1120 asyh
->curs
.handle
= nv50_disp(wndw
->plane
.dev
)->mast
.base
.vram
.handle
;
1121 asyh
->curs
.offset
= asyw
->image
.offset
;
1122 asyh
->set
.curs
= asyh
->curs
.visible
;
1126 nv50_curs_release(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
,
1127 struct nv50_head_atom
*asyh
)
1129 asyh
->curs
.visible
= false;
1133 nv50_curs_acquire(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
,
1134 struct nv50_head_atom
*asyh
)
1138 ret
= drm_plane_helper_check_state(&asyw
->state
, &asyw
->clip
,
1139 DRM_PLANE_HELPER_NO_SCALING
,
1140 DRM_PLANE_HELPER_NO_SCALING
,
1142 asyh
->curs
.visible
= asyw
->state
.visible
;
1143 if (ret
|| !asyh
->curs
.visible
)
1146 switch (asyw
->state
.fb
->width
) {
1147 case 32: asyh
->curs
.layout
= 0; break;
1148 case 64: asyh
->curs
.layout
= 1; break;
1153 if (asyw
->state
.fb
->width
!= asyw
->state
.fb
->height
)
1156 switch (asyw
->state
.fb
->pixel_format
) {
1157 case DRM_FORMAT_ARGB8888
: asyh
->curs
.format
= 1; break;
1167 nv50_curs_dtor(struct nv50_wndw
*wndw
)
1169 struct nv50_curs
*curs
= nv50_curs(wndw
);
1170 nvif_object_fini(&curs
->chan
);
1175 nv50_curs_format
[] = {
1176 DRM_FORMAT_ARGB8888
,
1179 static const struct nv50_wndw_func
1181 .dtor
= nv50_curs_dtor
,
1182 .acquire
= nv50_curs_acquire
,
1183 .release
= nv50_curs_release
,
1184 .prepare
= nv50_curs_prepare
,
1185 .point
= nv50_curs_point
,
1186 .update
= nv50_curs_update
,
1190 nv50_curs_new(struct nouveau_drm
*drm
, struct nv50_head
*head
,
1191 struct nv50_curs
**pcurs
)
1193 static const struct nvif_mclass curses
[] = {
1194 { GK104_DISP_CURSOR
, 0 },
1195 { GF110_DISP_CURSOR
, 0 },
1196 { GT214_DISP_CURSOR
, 0 },
1197 { G82_DISP_CURSOR
, 0 },
1198 { NV50_DISP_CURSOR
, 0 },
1201 struct nv50_disp_cursor_v0 args
= {
1202 .head
= head
->base
.index
,
1204 struct nv50_disp
*disp
= nv50_disp(drm
->dev
);
1205 struct nv50_curs
*curs
;
1208 cid
= nvif_mclass(disp
->disp
, curses
);
1210 NV_ERROR(drm
, "No supported cursor immediate class\n");
1214 if (!(curs
= *pcurs
= kzalloc(sizeof(*curs
), GFP_KERNEL
)))
1217 ret
= nv50_wndw_ctor(&nv50_curs
, drm
->dev
, DRM_PLANE_TYPE_CURSOR
,
1218 "curs", head
->base
.index
, &disp
->mast
.base
,
1219 nv50_curs_format
, ARRAY_SIZE(nv50_curs_format
),
1226 ret
= nvif_object_init(disp
->disp
, 0, curses
[cid
].oclass
, &args
,
1227 sizeof(args
), &curs
->chan
);
1229 NV_ERROR(drm
, "curs%04x allocation failed: %d\n",
1230 curses
[cid
].oclass
, ret
);
1237 /******************************************************************************
1239 *****************************************************************************/
1240 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1243 struct nv50_wndw wndw
;
1244 struct nv50_sync chan
;
1249 nv50_base_notify(struct nvif_notify
*notify
)
1251 return NVIF_NOTIFY_KEEP
;
1255 nv50_base_lut(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
1257 struct nv50_base
*base
= nv50_base(wndw
);
1259 if ((push
= evo_wait(&base
->chan
, 2))) {
1260 evo_mthd(push
, 0x00e0, 1);
1261 evo_data(push
, asyw
->lut
.enable
<< 30);
1262 evo_kick(push
, &base
->chan
);
1267 nv50_base_image_clr(struct nv50_wndw
*wndw
)
1269 struct nv50_base
*base
= nv50_base(wndw
);
1271 if ((push
= evo_wait(&base
->chan
, 4))) {
1272 evo_mthd(push
, 0x0084, 1);
1273 evo_data(push
, 0x00000000);
1274 evo_mthd(push
, 0x00c0, 1);
1275 evo_data(push
, 0x00000000);
1276 evo_kick(push
, &base
->chan
);
1281 nv50_base_image_set(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
1283 struct nv50_base
*base
= nv50_base(wndw
);
1284 const s32 oclass
= base
->chan
.base
.base
.user
.oclass
;
1286 if ((push
= evo_wait(&base
->chan
, 10))) {
1287 evo_mthd(push
, 0x0084, 1);
1288 evo_data(push
, (asyw
->image
.mode
<< 8) |
1289 (asyw
->image
.interval
<< 4));
1290 evo_mthd(push
, 0x00c0, 1);
1291 evo_data(push
, asyw
->image
.handle
);
1292 if (oclass
< G82_DISP_BASE_CHANNEL_DMA
) {
1293 evo_mthd(push
, 0x0800, 5);
1294 evo_data(push
, asyw
->image
.offset
>> 8);
1295 evo_data(push
, 0x00000000);
1296 evo_data(push
, (asyw
->image
.h
<< 16) | asyw
->image
.w
);
1297 evo_data(push
, (asyw
->image
.layout
<< 20) |
1300 evo_data(push
, (asyw
->image
.kind
<< 16) |
1301 (asyw
->image
.format
<< 8));
1303 if (oclass
< GF110_DISP_BASE_CHANNEL_DMA
) {
1304 evo_mthd(push
, 0x0800, 5);
1305 evo_data(push
, asyw
->image
.offset
>> 8);
1306 evo_data(push
, 0x00000000);
1307 evo_data(push
, (asyw
->image
.h
<< 16) | asyw
->image
.w
);
1308 evo_data(push
, (asyw
->image
.layout
<< 20) |
1311 evo_data(push
, asyw
->image
.format
<< 8);
1313 evo_mthd(push
, 0x0400, 5);
1314 evo_data(push
, asyw
->image
.offset
>> 8);
1315 evo_data(push
, 0x00000000);
1316 evo_data(push
, (asyw
->image
.h
<< 16) | asyw
->image
.w
);
1317 evo_data(push
, (asyw
->image
.layout
<< 24) |
1320 evo_data(push
, asyw
->image
.format
<< 8);
1322 evo_kick(push
, &base
->chan
);
1327 nv50_base_ntfy_clr(struct nv50_wndw
*wndw
)
1329 struct nv50_base
*base
= nv50_base(wndw
);
1331 if ((push
= evo_wait(&base
->chan
, 2))) {
1332 evo_mthd(push
, 0x00a4, 1);
1333 evo_data(push
, 0x00000000);
1334 evo_kick(push
, &base
->chan
);
1339 nv50_base_ntfy_set(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
1341 struct nv50_base
*base
= nv50_base(wndw
);
1343 if ((push
= evo_wait(&base
->chan
, 3))) {
1344 evo_mthd(push
, 0x00a0, 2);
1345 evo_data(push
, (asyw
->ntfy
.awaken
<< 30) | asyw
->ntfy
.offset
);
1346 evo_data(push
, asyw
->ntfy
.handle
);
1347 evo_kick(push
, &base
->chan
);
1352 nv50_base_sema_clr(struct nv50_wndw
*wndw
)
1354 struct nv50_base
*base
= nv50_base(wndw
);
1356 if ((push
= evo_wait(&base
->chan
, 2))) {
1357 evo_mthd(push
, 0x0094, 1);
1358 evo_data(push
, 0x00000000);
1359 evo_kick(push
, &base
->chan
);
1364 nv50_base_sema_set(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
1366 struct nv50_base
*base
= nv50_base(wndw
);
1368 if ((push
= evo_wait(&base
->chan
, 5))) {
1369 evo_mthd(push
, 0x0088, 4);
1370 evo_data(push
, asyw
->sema
.offset
);
1371 evo_data(push
, asyw
->sema
.acquire
);
1372 evo_data(push
, asyw
->sema
.release
);
1373 evo_data(push
, asyw
->sema
.handle
);
1374 evo_kick(push
, &base
->chan
);
1379 nv50_base_update(struct nv50_wndw
*wndw
, u32 interlock
)
1381 struct nv50_base
*base
= nv50_base(wndw
);
1384 if (!(push
= evo_wait(&base
->chan
, 2)))
1386 evo_mthd(push
, 0x0080, 1);
1387 evo_data(push
, interlock
);
1388 evo_kick(push
, &base
->chan
);
1390 if (base
->chan
.base
.base
.user
.oclass
< GF110_DISP_BASE_CHANNEL_DMA
)
1391 return interlock
? 2 << (base
->id
* 8) : 0;
1392 return interlock
? 2 << (base
->id
* 4) : 0;
1396 nv50_base_ntfy_wait_begun(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
)
1398 struct nouveau_drm
*drm
= nouveau_drm(wndw
->plane
.dev
);
1399 struct nv50_disp
*disp
= nv50_disp(wndw
->plane
.dev
);
1400 if (nvif_msec(&drm
->device
, 2000ULL,
1401 u32 data
= nouveau_bo_rd32(disp
->sync
, asyw
->ntfy
.offset
/ 4);
1402 if ((data
& 0xc0000000) == 0x40000000)
1411 nv50_base_release(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
,
1412 struct nv50_head_atom
*asyh
)
1418 nv50_base_acquire(struct nv50_wndw
*wndw
, struct nv50_wndw_atom
*asyw
,
1419 struct nv50_head_atom
*asyh
)
1421 const u32 format
= asyw
->state
.fb
->pixel_format
;
1422 const struct drm_format_info
*info
;
1425 info
= drm_format_info(format
);
1426 if (!info
|| !info
->depth
)
1429 ret
= drm_plane_helper_check_state(&asyw
->state
, &asyw
->clip
,
1430 DRM_PLANE_HELPER_NO_SCALING
,
1431 DRM_PLANE_HELPER_NO_SCALING
,
1436 asyh
->base
.depth
= info
->depth
;
1437 asyh
->base
.cpp
= info
->cpp
[0];
1438 asyh
->base
.x
= asyw
->state
.src
.x1
>> 16;
1439 asyh
->base
.y
= asyw
->state
.src
.y1
>> 16;
1440 asyh
->base
.w
= asyw
->state
.fb
->width
;
1441 asyh
->base
.h
= asyw
->state
.fb
->height
;
1444 case DRM_FORMAT_C8
: asyw
->image
.format
= 0x1e; break;
1445 case DRM_FORMAT_RGB565
: asyw
->image
.format
= 0xe8; break;
1446 case DRM_FORMAT_XRGB1555
:
1447 case DRM_FORMAT_ARGB1555
: asyw
->image
.format
= 0xe9; break;
1448 case DRM_FORMAT_XRGB8888
:
1449 case DRM_FORMAT_ARGB8888
: asyw
->image
.format
= 0xcf; break;
1450 case DRM_FORMAT_XBGR2101010
:
1451 case DRM_FORMAT_ABGR2101010
: asyw
->image
.format
= 0xd1; break;
1452 case DRM_FORMAT_XBGR8888
:
1453 case DRM_FORMAT_ABGR8888
: asyw
->image
.format
= 0xd5; break;
1459 asyw
->lut
.enable
= 1;
1460 asyw
->set
.image
= true;
1465 nv50_base_dtor(struct nv50_wndw
*wndw
)
1467 struct nv50_disp
*disp
= nv50_disp(wndw
->plane
.dev
);
1468 struct nv50_base
*base
= nv50_base(wndw
);
1469 nv50_dmac_destroy(&base
->chan
.base
, disp
->disp
);
1474 nv50_base_format
[] = {
1477 DRM_FORMAT_XRGB1555
,
1478 DRM_FORMAT_ARGB1555
,
1479 DRM_FORMAT_XRGB8888
,
1480 DRM_FORMAT_ARGB8888
,
1481 DRM_FORMAT_XBGR2101010
,
1482 DRM_FORMAT_ABGR2101010
,
1483 DRM_FORMAT_XBGR8888
,
1484 DRM_FORMAT_ABGR8888
,
1487 static const struct nv50_wndw_func
1489 .dtor
= nv50_base_dtor
,
1490 .acquire
= nv50_base_acquire
,
1491 .release
= nv50_base_release
,
1492 .sema_set
= nv50_base_sema_set
,
1493 .sema_clr
= nv50_base_sema_clr
,
1494 .ntfy_set
= nv50_base_ntfy_set
,
1495 .ntfy_clr
= nv50_base_ntfy_clr
,
1496 .ntfy_wait_begun
= nv50_base_ntfy_wait_begun
,
1497 .image_set
= nv50_base_image_set
,
1498 .image_clr
= nv50_base_image_clr
,
1499 .lut
= nv50_base_lut
,
1500 .update
= nv50_base_update
,
1504 nv50_base_new(struct nouveau_drm
*drm
, struct nv50_head
*head
,
1505 struct nv50_base
**pbase
)
1507 struct nv50_disp
*disp
= nv50_disp(drm
->dev
);
1508 struct nv50_base
*base
;
1511 if (!(base
= *pbase
= kzalloc(sizeof(*base
), GFP_KERNEL
)))
1513 base
->id
= head
->base
.index
;
1514 base
->wndw
.ntfy
= EVO_FLIP_NTFY0(base
->id
);
1515 base
->wndw
.sema
= EVO_FLIP_SEM0(base
->id
);
1516 base
->wndw
.data
= 0x00000000;
1518 ret
= nv50_wndw_ctor(&nv50_base
, drm
->dev
, DRM_PLANE_TYPE_PRIMARY
,
1519 "base", base
->id
, &base
->chan
.base
,
1520 nv50_base_format
, ARRAY_SIZE(nv50_base_format
),
1527 ret
= nv50_base_create(&drm
->device
, disp
->disp
, base
->id
,
1528 disp
->sync
->bo
.offset
, &base
->chan
);
1532 return nvif_notify_init(&base
->chan
.base
.base
.user
, nv50_base_notify
,
1534 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT
,
1535 &(struct nvif_notify_uevent_req
) {},
1536 sizeof(struct nvif_notify_uevent_req
),
1537 sizeof(struct nvif_notify_uevent_rep
),
1538 &base
->wndw
.notify
);
1541 /******************************************************************************
1543 *****************************************************************************/
1545 nv50_head_procamp(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1547 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1549 if ((push
= evo_wait(core
, 2))) {
1550 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
)
1551 evo_mthd(push
, 0x08a8 + (head
->base
.index
* 0x400), 1);
1553 evo_mthd(push
, 0x0498 + (head
->base
.index
* 0x300), 1);
1554 evo_data(push
, (asyh
->procamp
.sat
.sin
<< 20) |
1555 (asyh
->procamp
.sat
.cos
<< 8));
1556 evo_kick(push
, core
);
1561 nv50_head_dither(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1563 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1565 if ((push
= evo_wait(core
, 2))) {
1566 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
)
1567 evo_mthd(push
, 0x08a0 + (head
->base
.index
* 0x0400), 1);
1569 if (core
->base
.user
.oclass
< GK104_DISP_CORE_CHANNEL_DMA
)
1570 evo_mthd(push
, 0x0490 + (head
->base
.index
* 0x0300), 1);
1572 evo_mthd(push
, 0x04a0 + (head
->base
.index
* 0x0300), 1);
1573 evo_data(push
, (asyh
->dither
.mode
<< 3) |
1574 (asyh
->dither
.bits
<< 1) |
1575 asyh
->dither
.enable
);
1576 evo_kick(push
, core
);
1581 nv50_head_ovly(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1583 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1587 if (asyh
->base
.cpp
) {
1588 switch (asyh
->base
.cpp
) {
1589 case 8: bounds
|= 0x00000500; break;
1590 case 4: bounds
|= 0x00000300; break;
1591 case 2: bounds
|= 0x00000100; break;
1596 bounds
|= 0x00000001;
1599 if ((push
= evo_wait(core
, 2))) {
1600 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
)
1601 evo_mthd(push
, 0x0904 + head
->base
.index
* 0x400, 1);
1603 evo_mthd(push
, 0x04d4 + head
->base
.index
* 0x300, 1);
1604 evo_data(push
, bounds
);
1605 evo_kick(push
, core
);
1610 nv50_head_base(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1612 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1616 if (asyh
->base
.cpp
) {
1617 switch (asyh
->base
.cpp
) {
1618 case 8: bounds
|= 0x00000500; break;
1619 case 4: bounds
|= 0x00000300; break;
1620 case 2: bounds
|= 0x00000100; break;
1621 case 1: bounds
|= 0x00000000; break;
1626 bounds
|= 0x00000001;
1629 if ((push
= evo_wait(core
, 2))) {
1630 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
)
1631 evo_mthd(push
, 0x0900 + head
->base
.index
* 0x400, 1);
1633 evo_mthd(push
, 0x04d0 + head
->base
.index
* 0x300, 1);
1634 evo_data(push
, bounds
);
1635 evo_kick(push
, core
);
1640 nv50_head_curs_clr(struct nv50_head
*head
)
1642 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1644 if ((push
= evo_wait(core
, 4))) {
1645 if (core
->base
.user
.oclass
< G82_DISP_CORE_CHANNEL_DMA
) {
1646 evo_mthd(push
, 0x0880 + head
->base
.index
* 0x400, 1);
1647 evo_data(push
, 0x05000000);
1649 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
1650 evo_mthd(push
, 0x0880 + head
->base
.index
* 0x400, 1);
1651 evo_data(push
, 0x05000000);
1652 evo_mthd(push
, 0x089c + head
->base
.index
* 0x400, 1);
1653 evo_data(push
, 0x00000000);
1655 evo_mthd(push
, 0x0480 + head
->base
.index
* 0x300, 1);
1656 evo_data(push
, 0x05000000);
1657 evo_mthd(push
, 0x048c + head
->base
.index
* 0x300, 1);
1658 evo_data(push
, 0x00000000);
1660 evo_kick(push
, core
);
1665 nv50_head_curs_set(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1667 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1669 if ((push
= evo_wait(core
, 5))) {
1670 if (core
->base
.user
.oclass
< G82_DISP_BASE_CHANNEL_DMA
) {
1671 evo_mthd(push
, 0x0880 + head
->base
.index
* 0x400, 2);
1672 evo_data(push
, 0x80000000 | (asyh
->curs
.layout
<< 26) |
1673 (asyh
->curs
.format
<< 24));
1674 evo_data(push
, asyh
->curs
.offset
>> 8);
1676 if (core
->base
.user
.oclass
< GF110_DISP_BASE_CHANNEL_DMA
) {
1677 evo_mthd(push
, 0x0880 + head
->base
.index
* 0x400, 2);
1678 evo_data(push
, 0x80000000 | (asyh
->curs
.layout
<< 26) |
1679 (asyh
->curs
.format
<< 24));
1680 evo_data(push
, asyh
->curs
.offset
>> 8);
1681 evo_mthd(push
, 0x089c + head
->base
.index
* 0x400, 1);
1682 evo_data(push
, asyh
->curs
.handle
);
1684 evo_mthd(push
, 0x0480 + head
->base
.index
* 0x300, 2);
1685 evo_data(push
, 0x80000000 | (asyh
->curs
.layout
<< 26) |
1686 (asyh
->curs
.format
<< 24));
1687 evo_data(push
, asyh
->curs
.offset
>> 8);
1688 evo_mthd(push
, 0x048c + head
->base
.index
* 0x300, 1);
1689 evo_data(push
, asyh
->curs
.handle
);
1691 evo_kick(push
, core
);
1696 nv50_head_core_clr(struct nv50_head
*head
)
1698 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1700 if ((push
= evo_wait(core
, 2))) {
1701 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
)
1702 evo_mthd(push
, 0x0874 + head
->base
.index
* 0x400, 1);
1704 evo_mthd(push
, 0x0474 + head
->base
.index
* 0x300, 1);
1705 evo_data(push
, 0x00000000);
1706 evo_kick(push
, core
);
1711 nv50_head_core_set(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1713 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1715 if ((push
= evo_wait(core
, 9))) {
1716 if (core
->base
.user
.oclass
< G82_DISP_CORE_CHANNEL_DMA
) {
1717 evo_mthd(push
, 0x0860 + head
->base
.index
* 0x400, 1);
1718 evo_data(push
, asyh
->core
.offset
>> 8);
1719 evo_mthd(push
, 0x0868 + head
->base
.index
* 0x400, 4);
1720 evo_data(push
, (asyh
->core
.h
<< 16) | asyh
->core
.w
);
1721 evo_data(push
, asyh
->core
.layout
<< 20 |
1722 (asyh
->core
.pitch
>> 8) << 8 |
1724 evo_data(push
, asyh
->core
.kind
<< 16 |
1725 asyh
->core
.format
<< 8);
1726 evo_data(push
, asyh
->core
.handle
);
1727 evo_mthd(push
, 0x08c0 + head
->base
.index
* 0x400, 1);
1728 evo_data(push
, (asyh
->core
.y
<< 16) | asyh
->core
.x
);
1730 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
1731 evo_mthd(push
, 0x0860 + head
->base
.index
* 0x400, 1);
1732 evo_data(push
, asyh
->core
.offset
>> 8);
1733 evo_mthd(push
, 0x0868 + head
->base
.index
* 0x400, 4);
1734 evo_data(push
, (asyh
->core
.h
<< 16) | asyh
->core
.w
);
1735 evo_data(push
, asyh
->core
.layout
<< 20 |
1736 (asyh
->core
.pitch
>> 8) << 8 |
1738 evo_data(push
, asyh
->core
.format
<< 8);
1739 evo_data(push
, asyh
->core
.handle
);
1740 evo_mthd(push
, 0x08c0 + head
->base
.index
* 0x400, 1);
1741 evo_data(push
, (asyh
->core
.y
<< 16) | asyh
->core
.x
);
1743 evo_mthd(push
, 0x0460 + head
->base
.index
* 0x300, 1);
1744 evo_data(push
, asyh
->core
.offset
>> 8);
1745 evo_mthd(push
, 0x0468 + head
->base
.index
* 0x300, 4);
1746 evo_data(push
, (asyh
->core
.h
<< 16) | asyh
->core
.w
);
1747 evo_data(push
, asyh
->core
.layout
<< 24 |
1748 (asyh
->core
.pitch
>> 8) << 8 |
1750 evo_data(push
, asyh
->core
.format
<< 8);
1751 evo_data(push
, asyh
->core
.handle
);
1752 evo_mthd(push
, 0x04b0 + head
->base
.index
* 0x300, 1);
1753 evo_data(push
, (asyh
->core
.y
<< 16) | asyh
->core
.x
);
1755 evo_kick(push
, core
);
1760 nv50_head_lut_clr(struct nv50_head
*head
)
1762 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1764 if ((push
= evo_wait(core
, 4))) {
1765 if (core
->base
.user
.oclass
< G82_DISP_CORE_CHANNEL_DMA
) {
1766 evo_mthd(push
, 0x0840 + (head
->base
.index
* 0x400), 1);
1767 evo_data(push
, 0x40000000);
1769 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
1770 evo_mthd(push
, 0x0840 + (head
->base
.index
* 0x400), 1);
1771 evo_data(push
, 0x40000000);
1772 evo_mthd(push
, 0x085c + (head
->base
.index
* 0x400), 1);
1773 evo_data(push
, 0x00000000);
1775 evo_mthd(push
, 0x0440 + (head
->base
.index
* 0x300), 1);
1776 evo_data(push
, 0x03000000);
1777 evo_mthd(push
, 0x045c + (head
->base
.index
* 0x300), 1);
1778 evo_data(push
, 0x00000000);
1780 evo_kick(push
, core
);
1785 nv50_head_lut_set(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1787 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1789 if ((push
= evo_wait(core
, 7))) {
1790 if (core
->base
.user
.oclass
< G82_DISP_CORE_CHANNEL_DMA
) {
1791 evo_mthd(push
, 0x0840 + (head
->base
.index
* 0x400), 2);
1792 evo_data(push
, 0xc0000000);
1793 evo_data(push
, asyh
->lut
.offset
>> 8);
1795 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
1796 evo_mthd(push
, 0x0840 + (head
->base
.index
* 0x400), 2);
1797 evo_data(push
, 0xc0000000);
1798 evo_data(push
, asyh
->lut
.offset
>> 8);
1799 evo_mthd(push
, 0x085c + (head
->base
.index
* 0x400), 1);
1800 evo_data(push
, asyh
->lut
.handle
);
1802 evo_mthd(push
, 0x0440 + (head
->base
.index
* 0x300), 4);
1803 evo_data(push
, 0x83000000);
1804 evo_data(push
, asyh
->lut
.offset
>> 8);
1805 evo_data(push
, 0x00000000);
1806 evo_data(push
, 0x00000000);
1807 evo_mthd(push
, 0x045c + (head
->base
.index
* 0x300), 1);
1808 evo_data(push
, asyh
->lut
.handle
);
1810 evo_kick(push
, core
);
1815 nv50_head_mode(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1817 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1818 struct nv50_head_mode
*m
= &asyh
->mode
;
1820 if ((push
= evo_wait(core
, 14))) {
1821 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
1822 evo_mthd(push
, 0x0804 + (head
->base
.index
* 0x400), 2);
1823 evo_data(push
, 0x00800000 | m
->clock
);
1824 evo_data(push
, m
->interlace
? 0x00000002 : 0x00000000);
1825 evo_mthd(push
, 0x0810 + (head
->base
.index
* 0x400), 7);
1826 evo_data(push
, 0x00000000);
1827 evo_data(push
, (m
->v
.active
<< 16) | m
->h
.active
);
1828 evo_data(push
, (m
->v
.synce
<< 16) | m
->h
.synce
);
1829 evo_data(push
, (m
->v
.blanke
<< 16) | m
->h
.blanke
);
1830 evo_data(push
, (m
->v
.blanks
<< 16) | m
->h
.blanks
);
1831 evo_data(push
, (m
->v
.blank2e
<< 16) | m
->v
.blank2s
);
1832 evo_data(push
, asyh
->mode
.v
.blankus
);
1833 evo_mthd(push
, 0x082c + (head
->base
.index
* 0x400), 1);
1834 evo_data(push
, 0x00000000);
1836 evo_mthd(push
, 0x0410 + (head
->base
.index
* 0x300), 6);
1837 evo_data(push
, 0x00000000);
1838 evo_data(push
, (m
->v
.active
<< 16) | m
->h
.active
);
1839 evo_data(push
, (m
->v
.synce
<< 16) | m
->h
.synce
);
1840 evo_data(push
, (m
->v
.blanke
<< 16) | m
->h
.blanke
);
1841 evo_data(push
, (m
->v
.blanks
<< 16) | m
->h
.blanks
);
1842 evo_data(push
, (m
->v
.blank2e
<< 16) | m
->v
.blank2s
);
1843 evo_mthd(push
, 0x042c + (head
->base
.index
* 0x300), 2);
1844 evo_data(push
, 0x00000000); /* ??? */
1845 evo_data(push
, 0xffffff00);
1846 evo_mthd(push
, 0x0450 + (head
->base
.index
* 0x300), 3);
1847 evo_data(push
, m
->clock
* 1000);
1848 evo_data(push
, 0x00200000); /* ??? */
1849 evo_data(push
, m
->clock
* 1000);
1851 evo_kick(push
, core
);
1856 nv50_head_view(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1858 struct nv50_dmac
*core
= &nv50_disp(head
->base
.base
.dev
)->mast
.base
;
1860 if ((push
= evo_wait(core
, 10))) {
1861 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
1862 evo_mthd(push
, 0x08a4 + (head
->base
.index
* 0x400), 1);
1863 evo_data(push
, 0x00000000);
1864 evo_mthd(push
, 0x08c8 + (head
->base
.index
* 0x400), 1);
1865 evo_data(push
, (asyh
->view
.iH
<< 16) | asyh
->view
.iW
);
1866 evo_mthd(push
, 0x08d8 + (head
->base
.index
* 0x400), 2);
1867 evo_data(push
, (asyh
->view
.oH
<< 16) | asyh
->view
.oW
);
1868 evo_data(push
, (asyh
->view
.oH
<< 16) | asyh
->view
.oW
);
1870 evo_mthd(push
, 0x0494 + (head
->base
.index
* 0x300), 1);
1871 evo_data(push
, 0x00000000);
1872 evo_mthd(push
, 0x04b8 + (head
->base
.index
* 0x300), 1);
1873 evo_data(push
, (asyh
->view
.iH
<< 16) | asyh
->view
.iW
);
1874 evo_mthd(push
, 0x04c0 + (head
->base
.index
* 0x300), 3);
1875 evo_data(push
, (asyh
->view
.oH
<< 16) | asyh
->view
.oW
);
1876 evo_data(push
, (asyh
->view
.oH
<< 16) | asyh
->view
.oW
);
1877 evo_data(push
, (asyh
->view
.oH
<< 16) | asyh
->view
.oW
);
1879 evo_kick(push
, core
);
1884 nv50_head_flush_clr(struct nv50_head
*head
, struct nv50_head_atom
*asyh
, bool y
)
1886 if (asyh
->clr
.core
&& (!asyh
->set
.core
|| y
))
1887 nv50_head_lut_clr(head
);
1888 if (asyh
->clr
.core
&& (!asyh
->set
.core
|| y
))
1889 nv50_head_core_clr(head
);
1890 if (asyh
->clr
.curs
&& (!asyh
->set
.curs
|| y
))
1891 nv50_head_curs_clr(head
);
1895 nv50_head_flush_set(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
1897 if (asyh
->set
.view
) nv50_head_view (head
, asyh
);
1898 if (asyh
->set
.mode
) nv50_head_mode (head
, asyh
);
1899 if (asyh
->set
.core
) nv50_head_lut_set (head
, asyh
);
1900 if (asyh
->set
.core
) nv50_head_core_set(head
, asyh
);
1901 if (asyh
->set
.curs
) nv50_head_curs_set(head
, asyh
);
1902 if (asyh
->set
.base
) nv50_head_base (head
, asyh
);
1903 if (asyh
->set
.ovly
) nv50_head_ovly (head
, asyh
);
1904 if (asyh
->set
.dither
) nv50_head_dither (head
, asyh
);
1905 if (asyh
->set
.procamp
) nv50_head_procamp (head
, asyh
);
1909 nv50_head_atomic_check_procamp(struct nv50_head_atom
*armh
,
1910 struct nv50_head_atom
*asyh
,
1911 struct nouveau_conn_atom
*asyc
)
1913 const int vib
= asyc
->procamp
.color_vibrance
- 100;
1914 const int hue
= asyc
->procamp
.vibrant_hue
- 90;
1915 const int adj
= (vib
> 0) ? 50 : 0;
1916 asyh
->procamp
.sat
.cos
= ((vib
* 2047 + adj
) / 100) & 0xfff;
1917 asyh
->procamp
.sat
.sin
= ((hue
* 2047) / 100) & 0xfff;
1918 asyh
->set
.procamp
= true;
1922 nv50_head_atomic_check_dither(struct nv50_head_atom
*armh
,
1923 struct nv50_head_atom
*asyh
,
1924 struct nouveau_conn_atom
*asyc
)
1926 struct drm_connector
*connector
= asyc
->state
.connector
;
1929 if (asyc
->dither
.mode
== DITHERING_MODE_AUTO
) {
1930 if (asyh
->base
.depth
> connector
->display_info
.bpc
* 3)
1931 mode
= DITHERING_MODE_DYNAMIC2X2
;
1933 mode
= asyc
->dither
.mode
;
1936 if (asyc
->dither
.depth
== DITHERING_DEPTH_AUTO
) {
1937 if (connector
->display_info
.bpc
>= 8)
1938 mode
|= DITHERING_DEPTH_8BPC
;
1940 mode
|= asyc
->dither
.depth
;
1943 asyh
->dither
.enable
= mode
;
1944 asyh
->dither
.bits
= mode
>> 1;
1945 asyh
->dither
.mode
= mode
>> 3;
1946 asyh
->set
.dither
= true;
1950 nv50_head_atomic_check_view(struct nv50_head_atom
*armh
,
1951 struct nv50_head_atom
*asyh
,
1952 struct nouveau_conn_atom
*asyc
)
1954 struct drm_connector
*connector
= asyc
->state
.connector
;
1955 struct drm_display_mode
*omode
= &asyh
->state
.adjusted_mode
;
1956 struct drm_display_mode
*umode
= &asyh
->state
.mode
;
1957 int mode
= asyc
->scaler
.mode
;
1960 if (connector
->edid_blob_ptr
)
1961 edid
= (struct edid
*)connector
->edid_blob_ptr
->data
;
1965 if (!asyc
->scaler
.full
) {
1966 if (mode
== DRM_MODE_SCALE_NONE
)
1969 /* Non-EDID LVDS/eDP mode. */
1970 mode
= DRM_MODE_SCALE_FULLSCREEN
;
1973 asyh
->view
.iW
= umode
->hdisplay
;
1974 asyh
->view
.iH
= umode
->vdisplay
;
1975 asyh
->view
.oW
= omode
->hdisplay
;
1976 asyh
->view
.oH
= omode
->vdisplay
;
1977 if (omode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
1980 /* Add overscan compensation if necessary, will keep the aspect
1981 * ratio the same as the backend mode unless overridden by the
1982 * user setting both hborder and vborder properties.
1984 if ((asyc
->scaler
.underscan
.mode
== UNDERSCAN_ON
||
1985 (asyc
->scaler
.underscan
.mode
== UNDERSCAN_AUTO
&&
1986 drm_detect_hdmi_monitor(edid
)))) {
1987 u32 bX
= asyc
->scaler
.underscan
.hborder
;
1988 u32 bY
= asyc
->scaler
.underscan
.vborder
;
1989 u32 r
= (asyh
->view
.oH
<< 19) / asyh
->view
.oW
;
1992 asyh
->view
.oW
-= (bX
* 2);
1993 if (bY
) asyh
->view
.oH
-= (bY
* 2);
1994 else asyh
->view
.oH
= ((asyh
->view
.oW
* r
) + (r
/ 2)) >> 19;
1996 asyh
->view
.oW
-= (asyh
->view
.oW
>> 4) + 32;
1997 if (bY
) asyh
->view
.oH
-= (bY
* 2);
1998 else asyh
->view
.oH
= ((asyh
->view
.oW
* r
) + (r
/ 2)) >> 19;
2002 /* Handle CENTER/ASPECT scaling, taking into account the areas
2003 * removed already for overscan compensation.
2006 case DRM_MODE_SCALE_CENTER
:
2007 asyh
->view
.oW
= min((u16
)umode
->hdisplay
, asyh
->view
.oW
);
2008 asyh
->view
.oH
= min((u16
)umode
->vdisplay
, asyh
->view
.oH
);
2010 case DRM_MODE_SCALE_ASPECT
:
2011 if (asyh
->view
.oH
< asyh
->view
.oW
) {
2012 u32 r
= (asyh
->view
.iW
<< 19) / asyh
->view
.iH
;
2013 asyh
->view
.oW
= ((asyh
->view
.oH
* r
) + (r
/ 2)) >> 19;
2015 u32 r
= (asyh
->view
.iH
<< 19) / asyh
->view
.iW
;
2016 asyh
->view
.oH
= ((asyh
->view
.oW
* r
) + (r
/ 2)) >> 19;
2023 asyh
->set
.view
= true;
2027 nv50_head_atomic_check_mode(struct nv50_head
*head
, struct nv50_head_atom
*asyh
)
2029 struct drm_display_mode
*mode
= &asyh
->state
.adjusted_mode
;
2030 u32 ilace
= (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ? 2 : 1;
2031 u32 vscan
= (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) ? 2 : 1;
2032 u32 hbackp
= mode
->htotal
- mode
->hsync_end
;
2033 u32 vbackp
= (mode
->vtotal
- mode
->vsync_end
) * vscan
/ ilace
;
2034 u32 hfrontp
= mode
->hsync_start
- mode
->hdisplay
;
2035 u32 vfrontp
= (mode
->vsync_start
- mode
->vdisplay
) * vscan
/ ilace
;
2036 struct nv50_head_mode
*m
= &asyh
->mode
;
2038 m
->h
.active
= mode
->htotal
;
2039 m
->h
.synce
= mode
->hsync_end
- mode
->hsync_start
- 1;
2040 m
->h
.blanke
= m
->h
.synce
+ hbackp
;
2041 m
->h
.blanks
= mode
->htotal
- hfrontp
- 1;
2043 m
->v
.active
= mode
->vtotal
* vscan
/ ilace
;
2044 m
->v
.synce
= ((mode
->vsync_end
- mode
->vsync_start
) * vscan
/ ilace
) - 1;
2045 m
->v
.blanke
= m
->v
.synce
+ vbackp
;
2046 m
->v
.blanks
= m
->v
.active
- vfrontp
- 1;
2048 /*XXX: Safe underestimate, even "0" works */
2049 m
->v
.blankus
= (m
->v
.active
- mode
->vdisplay
- 2) * m
->h
.active
;
2050 m
->v
.blankus
*= 1000;
2051 m
->v
.blankus
/= mode
->clock
;
2053 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
2054 m
->v
.blank2e
= m
->v
.active
+ m
->v
.synce
+ vbackp
;
2055 m
->v
.blank2s
= m
->v
.blank2e
+ (mode
->vdisplay
* vscan
/ ilace
);
2056 m
->v
.active
= (m
->v
.active
* 2) + 1;
2057 m
->interlace
= true;
2061 m
->interlace
= false;
2063 m
->clock
= mode
->clock
;
2065 drm_mode_set_crtcinfo(mode
, CRTC_INTERLACE_HALVE_V
);
2066 asyh
->set
.mode
= true;
2070 nv50_head_atomic_check(struct drm_crtc
*crtc
, struct drm_crtc_state
*state
)
2072 struct nouveau_drm
*drm
= nouveau_drm(crtc
->dev
);
2073 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
2074 struct nv50_head
*head
= nv50_head(crtc
);
2075 struct nv50_head_atom
*armh
= nv50_head_atom(crtc
->state
);
2076 struct nv50_head_atom
*asyh
= nv50_head_atom(state
);
2077 struct nouveau_conn_atom
*asyc
= NULL
;
2078 struct drm_connector_state
*conns
;
2079 struct drm_connector
*conn
;
2082 NV_ATOMIC(drm
, "%s atomic_check %d\n", crtc
->name
, asyh
->state
.active
);
2083 if (asyh
->state
.active
) {
2084 for_each_connector_in_state(asyh
->state
.state
, conn
, conns
, i
) {
2085 if (conns
->crtc
== crtc
) {
2086 asyc
= nouveau_conn_atom(conns
);
2091 if (armh
->state
.active
) {
2093 if (asyh
->state
.mode_changed
)
2094 asyc
->set
.scaler
= true;
2095 if (armh
->base
.depth
!= asyh
->base
.depth
)
2096 asyc
->set
.dither
= true;
2099 asyc
->set
.mask
= ~0;
2100 asyh
->set
.mask
= ~0;
2103 if (asyh
->state
.mode_changed
)
2104 nv50_head_atomic_check_mode(head
, asyh
);
2107 if (asyc
->set
.scaler
)
2108 nv50_head_atomic_check_view(armh
, asyh
, asyc
);
2109 if (asyc
->set
.dither
)
2110 nv50_head_atomic_check_dither(armh
, asyh
, asyc
);
2111 if (asyc
->set
.procamp
)
2112 nv50_head_atomic_check_procamp(armh
, asyh
, asyc
);
2115 if ((asyh
->core
.visible
= (asyh
->base
.cpp
!= 0))) {
2116 asyh
->core
.x
= asyh
->base
.x
;
2117 asyh
->core
.y
= asyh
->base
.y
;
2118 asyh
->core
.w
= asyh
->base
.w
;
2119 asyh
->core
.h
= asyh
->base
.h
;
2121 if ((asyh
->core
.visible
= asyh
->curs
.visible
)) {
2122 /*XXX: We need to either find some way of having the
2123 * primary base layer appear black, while still
2124 * being able to display the other layers, or we
2125 * need to allocate a dummy black surface here.
2129 asyh
->core
.w
= asyh
->state
.mode
.hdisplay
;
2130 asyh
->core
.h
= asyh
->state
.mode
.vdisplay
;
2132 asyh
->core
.handle
= disp
->mast
.base
.vram
.handle
;
2133 asyh
->core
.offset
= 0;
2134 asyh
->core
.format
= 0xcf;
2135 asyh
->core
.kind
= 0;
2136 asyh
->core
.layout
= 1;
2137 asyh
->core
.block
= 0;
2138 asyh
->core
.pitch
= ALIGN(asyh
->core
.w
, 64) * 4;
2139 asyh
->lut
.handle
= disp
->mast
.base
.vram
.handle
;
2140 asyh
->lut
.offset
= head
->base
.lut
.nvbo
->bo
.offset
;
2141 asyh
->set
.base
= armh
->base
.cpp
!= asyh
->base
.cpp
;
2142 asyh
->set
.ovly
= armh
->ovly
.cpp
!= asyh
->ovly
.cpp
;
2144 asyh
->core
.visible
= false;
2145 asyh
->curs
.visible
= false;
2150 if (!drm_atomic_crtc_needs_modeset(&asyh
->state
)) {
2151 if (asyh
->core
.visible
) {
2152 if (memcmp(&armh
->core
, &asyh
->core
, sizeof(asyh
->core
)))
2153 asyh
->set
.core
= true;
2155 if (armh
->core
.visible
) {
2156 asyh
->clr
.core
= true;
2159 if (asyh
->curs
.visible
) {
2160 if (memcmp(&armh
->curs
, &asyh
->curs
, sizeof(asyh
->curs
)))
2161 asyh
->set
.curs
= true;
2163 if (armh
->curs
.visible
) {
2164 asyh
->clr
.curs
= true;
2167 asyh
->clr
.core
= armh
->core
.visible
;
2168 asyh
->clr
.curs
= armh
->curs
.visible
;
2169 asyh
->set
.core
= asyh
->core
.visible
;
2170 asyh
->set
.curs
= asyh
->curs
.visible
;
2173 if (asyh
->clr
.mask
|| asyh
->set
.mask
)
2174 nv50_atom(asyh
->state
.state
)->lock_core
= true;
2179 nv50_head_lut_load(struct drm_crtc
*crtc
)
2181 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
2182 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
2183 void __iomem
*lut
= nvbo_kmap_obj_iovirtual(nv_crtc
->lut
.nvbo
);
2186 for (i
= 0; i
< 256; i
++) {
2187 u16 r
= nv_crtc
->lut
.r
[i
] >> 2;
2188 u16 g
= nv_crtc
->lut
.g
[i
] >> 2;
2189 u16 b
= nv_crtc
->lut
.b
[i
] >> 2;
2191 if (disp
->disp
->oclass
< GF110_DISP
) {
2192 writew(r
+ 0x0000, lut
+ (i
* 0x08) + 0);
2193 writew(g
+ 0x0000, lut
+ (i
* 0x08) + 2);
2194 writew(b
+ 0x0000, lut
+ (i
* 0x08) + 4);
2196 writew(r
+ 0x6000, lut
+ (i
* 0x20) + 0);
2197 writew(g
+ 0x6000, lut
+ (i
* 0x20) + 2);
2198 writew(b
+ 0x6000, lut
+ (i
* 0x20) + 4);
2204 nv50_head_mode_set_base_atomic(struct drm_crtc
*crtc
,
2205 struct drm_framebuffer
*fb
, int x
, int y
,
2206 enum mode_set_atomic state
)
2212 static const struct drm_crtc_helper_funcs
2214 .mode_set_base_atomic
= nv50_head_mode_set_base_atomic
,
2215 .load_lut
= nv50_head_lut_load
,
2216 .atomic_check
= nv50_head_atomic_check
,
2219 /* This is identical to the version in the atomic helpers, except that
2220 * it supports non-vblanked ("async") page flips.
2223 nv50_head_page_flip(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2224 struct drm_pending_vblank_event
*event
, u32 flags
)
2226 struct drm_plane
*plane
= crtc
->primary
;
2227 struct drm_atomic_state
*state
;
2228 struct drm_plane_state
*plane_state
;
2229 struct drm_crtc_state
*crtc_state
;
2232 state
= drm_atomic_state_alloc(plane
->dev
);
2236 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
2238 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
2239 if (IS_ERR(crtc_state
)) {
2240 ret
= PTR_ERR(crtc_state
);
2243 crtc_state
->event
= event
;
2245 plane_state
= drm_atomic_get_plane_state(state
, plane
);
2246 if (IS_ERR(plane_state
)) {
2247 ret
= PTR_ERR(plane_state
);
2251 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
2254 drm_atomic_set_fb_for_plane(plane_state
, fb
);
2256 /* Make sure we don't accidentally do a full modeset. */
2257 state
->allow_modeset
= false;
2258 if (!crtc_state
->active
) {
2259 DRM_DEBUG_ATOMIC("[CRTC:%d] disabled, rejecting legacy flip\n",
2265 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
2266 nv50_wndw_atom(plane_state
)->interval
= 0;
2268 ret
= drm_atomic_nonblocking_commit(state
);
2270 if (ret
== -EDEADLK
)
2273 drm_atomic_state_put(state
);
2277 drm_atomic_state_clear(state
);
2278 drm_atomic_legacy_backoff(state
);
2281 * Someone might have exchanged the framebuffer while we dropped locks
2282 * in the backoff code. We need to fix up the fb refcount tracking the
2285 plane
->old_fb
= plane
->fb
;
2291 nv50_head_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
2294 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
2297 for (i
= 0; i
< size
; i
++) {
2298 nv_crtc
->lut
.r
[i
] = r
[i
];
2299 nv_crtc
->lut
.g
[i
] = g
[i
];
2300 nv_crtc
->lut
.b
[i
] = b
[i
];
2303 nv50_head_lut_load(crtc
);
2308 nv50_head_atomic_destroy_state(struct drm_crtc
*crtc
,
2309 struct drm_crtc_state
*state
)
2311 struct nv50_head_atom
*asyh
= nv50_head_atom(state
);
2312 __drm_atomic_helper_crtc_destroy_state(&asyh
->state
);
2316 static struct drm_crtc_state
*
2317 nv50_head_atomic_duplicate_state(struct drm_crtc
*crtc
)
2319 struct nv50_head_atom
*armh
= nv50_head_atom(crtc
->state
);
2320 struct nv50_head_atom
*asyh
;
2321 if (!(asyh
= kmalloc(sizeof(*asyh
), GFP_KERNEL
)))
2323 __drm_atomic_helper_crtc_duplicate_state(crtc
, &asyh
->state
);
2324 asyh
->view
= armh
->view
;
2325 asyh
->mode
= armh
->mode
;
2326 asyh
->lut
= armh
->lut
;
2327 asyh
->core
= armh
->core
;
2328 asyh
->curs
= armh
->curs
;
2329 asyh
->base
= armh
->base
;
2330 asyh
->ovly
= armh
->ovly
;
2331 asyh
->dither
= armh
->dither
;
2332 asyh
->procamp
= armh
->procamp
;
2335 return &asyh
->state
;
2339 __drm_atomic_helper_crtc_reset(struct drm_crtc
*crtc
,
2340 struct drm_crtc_state
*state
)
2343 crtc
->funcs
->atomic_destroy_state(crtc
, crtc
->state
);
2344 crtc
->state
= state
;
2345 crtc
->state
->crtc
= crtc
;
2349 nv50_head_reset(struct drm_crtc
*crtc
)
2351 struct nv50_head_atom
*asyh
;
2353 if (WARN_ON(!(asyh
= kzalloc(sizeof(*asyh
), GFP_KERNEL
))))
2356 __drm_atomic_helper_crtc_reset(crtc
, &asyh
->state
);
2360 nv50_head_destroy(struct drm_crtc
*crtc
)
2362 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
2363 struct nv50_disp
*disp
= nv50_disp(crtc
->dev
);
2364 struct nv50_head
*head
= nv50_head(crtc
);
2366 nv50_dmac_destroy(&head
->ovly
.base
, disp
->disp
);
2367 nv50_pioc_destroy(&head
->oimm
.base
);
2369 nouveau_bo_unmap(nv_crtc
->lut
.nvbo
);
2370 if (nv_crtc
->lut
.nvbo
)
2371 nouveau_bo_unpin(nv_crtc
->lut
.nvbo
);
2372 nouveau_bo_ref(NULL
, &nv_crtc
->lut
.nvbo
);
2374 drm_crtc_cleanup(crtc
);
2378 static const struct drm_crtc_funcs
2380 .reset
= nv50_head_reset
,
2381 .gamma_set
= nv50_head_gamma_set
,
2382 .destroy
= nv50_head_destroy
,
2383 .set_config
= drm_atomic_helper_set_config
,
2384 .page_flip
= nv50_head_page_flip
,
2385 .set_property
= drm_atomic_helper_crtc_set_property
,
2386 .atomic_duplicate_state
= nv50_head_atomic_duplicate_state
,
2387 .atomic_destroy_state
= nv50_head_atomic_destroy_state
,
2391 nv50_head_create(struct drm_device
*dev
, int index
)
2393 struct nouveau_drm
*drm
= nouveau_drm(dev
);
2394 struct nvif_device
*device
= &drm
->device
;
2395 struct nv50_disp
*disp
= nv50_disp(dev
);
2396 struct nv50_head
*head
;
2397 struct nv50_base
*base
;
2398 struct nv50_curs
*curs
;
2399 struct drm_crtc
*crtc
;
2402 head
= kzalloc(sizeof(*head
), GFP_KERNEL
);
2406 head
->base
.index
= index
;
2407 for (i
= 0; i
< 256; i
++) {
2408 head
->base
.lut
.r
[i
] = i
<< 8;
2409 head
->base
.lut
.g
[i
] = i
<< 8;
2410 head
->base
.lut
.b
[i
] = i
<< 8;
2413 ret
= nv50_base_new(drm
, head
, &base
);
2415 ret
= nv50_curs_new(drm
, head
, &curs
);
2421 crtc
= &head
->base
.base
;
2422 drm_crtc_init_with_planes(dev
, crtc
, &base
->wndw
.plane
,
2423 &curs
->wndw
.plane
, &nv50_head_func
,
2424 "head-%d", head
->base
.index
);
2425 drm_crtc_helper_add(crtc
, &nv50_head_help
);
2426 drm_mode_crtc_set_gamma_size(crtc
, 256);
2428 ret
= nouveau_bo_new(dev
, 8192, 0x100, TTM_PL_FLAG_VRAM
,
2429 0, 0x0000, NULL
, NULL
, &head
->base
.lut
.nvbo
);
2431 ret
= nouveau_bo_pin(head
->base
.lut
.nvbo
, TTM_PL_FLAG_VRAM
, true);
2433 ret
= nouveau_bo_map(head
->base
.lut
.nvbo
);
2435 nouveau_bo_unpin(head
->base
.lut
.nvbo
);
2438 nouveau_bo_ref(NULL
, &head
->base
.lut
.nvbo
);
2444 /* allocate overlay resources */
2445 ret
= nv50_oimm_create(device
, disp
->disp
, index
, &head
->oimm
);
2449 ret
= nv50_ovly_create(device
, disp
->disp
, index
, disp
->sync
->bo
.offset
,
2456 nv50_head_destroy(crtc
);
2460 /******************************************************************************
2461 * Output path helpers
2462 *****************************************************************************/
2464 nv50_outp_atomic_check_view(struct drm_encoder
*encoder
,
2465 struct drm_crtc_state
*crtc_state
,
2466 struct drm_connector_state
*conn_state
,
2467 struct drm_display_mode
*native_mode
)
2469 struct drm_display_mode
*adjusted_mode
= &crtc_state
->adjusted_mode
;
2470 struct drm_display_mode
*mode
= &crtc_state
->mode
;
2471 struct drm_connector
*connector
= conn_state
->connector
;
2472 struct nouveau_conn_atom
*asyc
= nouveau_conn_atom(conn_state
);
2473 struct nouveau_drm
*drm
= nouveau_drm(encoder
->dev
);
2475 NV_ATOMIC(drm
, "%s atomic_check\n", encoder
->name
);
2476 asyc
->scaler
.full
= false;
2480 if (asyc
->scaler
.mode
== DRM_MODE_SCALE_NONE
) {
2481 switch (connector
->connector_type
) {
2482 case DRM_MODE_CONNECTOR_LVDS
:
2483 case DRM_MODE_CONNECTOR_eDP
:
2484 /* Force use of scaler for non-EDID modes. */
2485 if (adjusted_mode
->type
& DRM_MODE_TYPE_DRIVER
)
2488 asyc
->scaler
.full
= true;
2497 if (!drm_mode_equal(adjusted_mode
, mode
)) {
2498 drm_mode_copy(adjusted_mode
, mode
);
2499 crtc_state
->mode_changed
= true;
2506 nv50_outp_atomic_check(struct drm_encoder
*encoder
,
2507 struct drm_crtc_state
*crtc_state
,
2508 struct drm_connector_state
*conn_state
)
2510 struct nouveau_connector
*nv_connector
=
2511 nouveau_connector(conn_state
->connector
);
2512 return nv50_outp_atomic_check_view(encoder
, crtc_state
, conn_state
,
2513 nv_connector
->native_mode
);
2516 /******************************************************************************
2518 *****************************************************************************/
2520 nv50_dac_dpms(struct drm_encoder
*encoder
, int mode
)
2522 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2523 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2525 struct nv50_disp_mthd_v1 base
;
2526 struct nv50_disp_dac_pwr_v0 pwr
;
2529 .base
.method
= NV50_DISP_MTHD_V1_DAC_PWR
,
2530 .base
.hasht
= nv_encoder
->dcb
->hasht
,
2531 .base
.hashm
= nv_encoder
->dcb
->hashm
,
2534 .pwr
.vsync
= (mode
!= DRM_MODE_DPMS_SUSPEND
&&
2535 mode
!= DRM_MODE_DPMS_OFF
),
2536 .pwr
.hsync
= (mode
!= DRM_MODE_DPMS_STANDBY
&&
2537 mode
!= DRM_MODE_DPMS_OFF
),
2540 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
2544 nv50_dac_disable(struct drm_encoder
*encoder
)
2546 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2547 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
2548 const int or = nv_encoder
->or;
2551 if (nv_encoder
->crtc
) {
2552 push
= evo_wait(mast
, 4);
2554 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
2555 evo_mthd(push
, 0x0400 + (or * 0x080), 1);
2556 evo_data(push
, 0x00000000);
2558 evo_mthd(push
, 0x0180 + (or * 0x020), 1);
2559 evo_data(push
, 0x00000000);
2561 evo_kick(push
, mast
);
2565 nv_encoder
->crtc
= NULL
;
2569 nv50_dac_enable(struct drm_encoder
*encoder
)
2571 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
2572 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2573 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
2574 struct drm_display_mode
*mode
= &nv_crtc
->base
.state
->adjusted_mode
;
2577 push
= evo_wait(mast
, 8);
2579 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
2580 u32 syncs
= 0x00000000;
2582 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
2583 syncs
|= 0x00000001;
2584 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
2585 syncs
|= 0x00000002;
2587 evo_mthd(push
, 0x0400 + (nv_encoder
->or * 0x080), 2);
2588 evo_data(push
, 1 << nv_crtc
->index
);
2589 evo_data(push
, syncs
);
2591 u32 magic
= 0x31ec6000 | (nv_crtc
->index
<< 25);
2592 u32 syncs
= 0x00000001;
2594 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
2595 syncs
|= 0x00000008;
2596 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
2597 syncs
|= 0x00000010;
2599 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2600 magic
|= 0x00000001;
2602 evo_mthd(push
, 0x0404 + (nv_crtc
->index
* 0x300), 2);
2603 evo_data(push
, syncs
);
2604 evo_data(push
, magic
);
2605 evo_mthd(push
, 0x0180 + (nv_encoder
->or * 0x020), 1);
2606 evo_data(push
, 1 << nv_crtc
->index
);
2609 evo_kick(push
, mast
);
2612 nv_encoder
->crtc
= encoder
->crtc
;
2615 static enum drm_connector_status
2616 nv50_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
2618 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2619 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2621 struct nv50_disp_mthd_v1 base
;
2622 struct nv50_disp_dac_load_v0 load
;
2625 .base
.method
= NV50_DISP_MTHD_V1_DAC_LOAD
,
2626 .base
.hasht
= nv_encoder
->dcb
->hasht
,
2627 .base
.hashm
= nv_encoder
->dcb
->hashm
,
2631 args
.load
.data
= nouveau_drm(encoder
->dev
)->vbios
.dactestval
;
2632 if (args
.load
.data
== 0)
2633 args
.load
.data
= 340;
2635 ret
= nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
2636 if (ret
|| !args
.load
.load
)
2637 return connector_status_disconnected
;
2639 return connector_status_connected
;
2642 static const struct drm_encoder_helper_funcs
2644 .dpms
= nv50_dac_dpms
,
2645 .atomic_check
= nv50_outp_atomic_check
,
2646 .enable
= nv50_dac_enable
,
2647 .disable
= nv50_dac_disable
,
2648 .detect
= nv50_dac_detect
2652 nv50_dac_destroy(struct drm_encoder
*encoder
)
2654 drm_encoder_cleanup(encoder
);
2658 static const struct drm_encoder_funcs
2660 .destroy
= nv50_dac_destroy
,
2664 nv50_dac_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
2666 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
2667 struct nvkm_i2c
*i2c
= nvxx_i2c(&drm
->device
);
2668 struct nvkm_i2c_bus
*bus
;
2669 struct nouveau_encoder
*nv_encoder
;
2670 struct drm_encoder
*encoder
;
2671 int type
= DRM_MODE_ENCODER_DAC
;
2673 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
2676 nv_encoder
->dcb
= dcbe
;
2677 nv_encoder
->or = ffs(dcbe
->or) - 1;
2679 bus
= nvkm_i2c_bus_find(i2c
, dcbe
->i2c_index
);
2681 nv_encoder
->i2c
= &bus
->i2c
;
2683 encoder
= to_drm_encoder(nv_encoder
);
2684 encoder
->possible_crtcs
= dcbe
->heads
;
2685 encoder
->possible_clones
= 0;
2686 drm_encoder_init(connector
->dev
, encoder
, &nv50_dac_func
, type
,
2687 "dac-%04x-%04x", dcbe
->hasht
, dcbe
->hashm
);
2688 drm_encoder_helper_add(encoder
, &nv50_dac_help
);
2690 drm_mode_connector_attach_encoder(connector
, encoder
);
2694 /******************************************************************************
2696 *****************************************************************************/
2698 nv50_audio_disable(struct drm_encoder
*encoder
, struct nouveau_crtc
*nv_crtc
)
2700 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2701 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2703 struct nv50_disp_mthd_v1 base
;
2704 struct nv50_disp_sor_hda_eld_v0 eld
;
2707 .base
.method
= NV50_DISP_MTHD_V1_SOR_HDA_ELD
,
2708 .base
.hasht
= nv_encoder
->dcb
->hasht
,
2709 .base
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
2710 (0x0100 << nv_crtc
->index
),
2713 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
2717 nv50_audio_enable(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
2719 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2720 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
2721 struct nouveau_connector
*nv_connector
;
2722 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2725 struct nv50_disp_mthd_v1 mthd
;
2726 struct nv50_disp_sor_hda_eld_v0 eld
;
2728 u8 data
[sizeof(nv_connector
->base
.eld
)];
2730 .base
.mthd
.version
= 1,
2731 .base
.mthd
.method
= NV50_DISP_MTHD_V1_SOR_HDA_ELD
,
2732 .base
.mthd
.hasht
= nv_encoder
->dcb
->hasht
,
2733 .base
.mthd
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
2734 (0x0100 << nv_crtc
->index
),
2737 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
2738 if (!drm_detect_monitor_audio(nv_connector
->edid
))
2741 drm_edid_to_eld(&nv_connector
->base
, nv_connector
->edid
);
2742 memcpy(args
.data
, nv_connector
->base
.eld
, sizeof(args
.data
));
2744 nvif_mthd(disp
->disp
, 0, &args
,
2745 sizeof(args
.base
) + drm_eld_size(args
.data
));
2748 /******************************************************************************
2750 *****************************************************************************/
2752 nv50_hdmi_disable(struct drm_encoder
*encoder
, struct nouveau_crtc
*nv_crtc
)
2754 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2755 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2757 struct nv50_disp_mthd_v1 base
;
2758 struct nv50_disp_sor_hdmi_pwr_v0 pwr
;
2761 .base
.method
= NV50_DISP_MTHD_V1_SOR_HDMI_PWR
,
2762 .base
.hasht
= nv_encoder
->dcb
->hasht
,
2763 .base
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
2764 (0x0100 << nv_crtc
->index
),
2767 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
2771 nv50_hdmi_enable(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
)
2773 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
2774 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
2775 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
2777 struct nv50_disp_mthd_v1 base
;
2778 struct nv50_disp_sor_hdmi_pwr_v0 pwr
;
2781 .base
.method
= NV50_DISP_MTHD_V1_SOR_HDMI_PWR
,
2782 .base
.hasht
= nv_encoder
->dcb
->hasht
,
2783 .base
.hashm
= (0xf0ff & nv_encoder
->dcb
->hashm
) |
2784 (0x0100 << nv_crtc
->index
),
2786 .pwr
.rekey
= 56, /* binary driver, and tegra, constant */
2788 struct nouveau_connector
*nv_connector
;
2791 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
2792 if (!drm_detect_hdmi_monitor(nv_connector
->edid
))
2795 max_ac_packet
= mode
->htotal
- mode
->hdisplay
;
2796 max_ac_packet
-= args
.pwr
.rekey
;
2797 max_ac_packet
-= 18; /* constant from tegra */
2798 args
.pwr
.max_ac_packet
= max_ac_packet
/ 32;
2800 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
2801 nv50_audio_enable(encoder
, mode
);
2804 /******************************************************************************
2806 *****************************************************************************/
2807 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2808 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2809 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2812 struct nouveau_encoder
*outp
;
2814 struct drm_dp_mst_topology_mgr mgr
;
2815 struct nv50_msto
*msto
[4];
2821 struct nv50_mstm
*mstm
;
2822 struct drm_dp_mst_port
*port
;
2823 struct drm_connector connector
;
2825 struct drm_display_mode
*native
;
2832 struct drm_encoder encoder
;
2834 struct nv50_head
*head
;
2835 struct nv50_mstc
*mstc
;
2839 static struct drm_dp_payload
*
2840 nv50_msto_payload(struct nv50_msto
*msto
)
2842 struct nouveau_drm
*drm
= nouveau_drm(msto
->encoder
.dev
);
2843 struct nv50_mstc
*mstc
= msto
->mstc
;
2844 struct nv50_mstm
*mstm
= mstc
->mstm
;
2845 int vcpi
= mstc
->port
->vcpi
.vcpi
, i
;
2847 NV_ATOMIC(drm
, "%s: vcpi %d\n", msto
->encoder
.name
, vcpi
);
2848 for (i
= 0; i
< mstm
->mgr
.max_payloads
; i
++) {
2849 struct drm_dp_payload
*payload
= &mstm
->mgr
.payloads
[i
];
2850 NV_ATOMIC(drm
, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2851 mstm
->outp
->base
.base
.name
, i
, payload
->vcpi
,
2852 payload
->start_slot
, payload
->num_slots
);
2855 for (i
= 0; i
< mstm
->mgr
.max_payloads
; i
++) {
2856 struct drm_dp_payload
*payload
= &mstm
->mgr
.payloads
[i
];
2857 if (payload
->vcpi
== vcpi
)
2865 nv50_msto_cleanup(struct nv50_msto
*msto
)
2867 struct nouveau_drm
*drm
= nouveau_drm(msto
->encoder
.dev
);
2868 struct nv50_mstc
*mstc
= msto
->mstc
;
2869 struct nv50_mstm
*mstm
= mstc
->mstm
;
2871 NV_ATOMIC(drm
, "%s: msto cleanup\n", msto
->encoder
.name
);
2872 if (mstc
->port
&& mstc
->port
->vcpi
.vcpi
> 0 && !nv50_msto_payload(msto
))
2873 drm_dp_mst_deallocate_vcpi(&mstm
->mgr
, mstc
->port
);
2874 if (msto
->disabled
) {
2877 msto
->disabled
= false;
2882 nv50_msto_prepare(struct nv50_msto
*msto
)
2884 struct nouveau_drm
*drm
= nouveau_drm(msto
->encoder
.dev
);
2885 struct nv50_mstc
*mstc
= msto
->mstc
;
2886 struct nv50_mstm
*mstm
= mstc
->mstm
;
2888 struct nv50_disp_mthd_v1 base
;
2889 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi
;
2892 .base
.method
= NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI
,
2893 .base
.hasht
= mstm
->outp
->dcb
->hasht
,
2894 .base
.hashm
= (0xf0ff & mstm
->outp
->dcb
->hashm
) |
2895 (0x0100 << msto
->head
->base
.index
),
2898 NV_ATOMIC(drm
, "%s: msto prepare\n", msto
->encoder
.name
);
2899 if (mstc
->port
&& mstc
->port
->vcpi
.vcpi
> 0) {
2900 struct drm_dp_payload
*payload
= nv50_msto_payload(msto
);
2902 args
.vcpi
.start_slot
= payload
->start_slot
;
2903 args
.vcpi
.num_slots
= payload
->num_slots
;
2904 args
.vcpi
.pbn
= mstc
->port
->vcpi
.pbn
;
2905 args
.vcpi
.aligned_pbn
= mstc
->port
->vcpi
.aligned_pbn
;
2909 NV_ATOMIC(drm
, "%s: %s: %02x %02x %04x %04x\n",
2910 msto
->encoder
.name
, msto
->head
->base
.base
.name
,
2911 args
.vcpi
.start_slot
, args
.vcpi
.num_slots
,
2912 args
.vcpi
.pbn
, args
.vcpi
.aligned_pbn
);
2913 nvif_mthd(&drm
->display
->disp
, 0, &args
, sizeof(args
));
2917 nv50_msto_atomic_check(struct drm_encoder
*encoder
,
2918 struct drm_crtc_state
*crtc_state
,
2919 struct drm_connector_state
*conn_state
)
2921 struct nv50_mstc
*mstc
= nv50_mstc(conn_state
->connector
);
2922 struct nv50_mstm
*mstm
= mstc
->mstm
;
2923 int bpp
= conn_state
->connector
->display_info
.bpc
* 3;
2926 mstc
->pbn
= drm_dp_calc_pbn_mode(crtc_state
->adjusted_mode
.clock
, bpp
);
2928 slots
= drm_dp_find_vcpi_slots(&mstm
->mgr
, mstc
->pbn
);
2932 return nv50_outp_atomic_check_view(encoder
, crtc_state
, conn_state
,
2937 nv50_msto_enable(struct drm_encoder
*encoder
)
2939 struct nv50_head
*head
= nv50_head(encoder
->crtc
);
2940 struct nv50_msto
*msto
= nv50_msto(encoder
);
2941 struct nv50_mstc
*mstc
= NULL
;
2942 struct nv50_mstm
*mstm
= NULL
;
2943 struct drm_connector
*connector
;
2948 drm_for_each_connector(connector
, encoder
->dev
) {
2949 if (connector
->state
->best_encoder
== &msto
->encoder
) {
2950 mstc
= nv50_mstc(connector
);
2959 r
= drm_dp_mst_allocate_vcpi(&mstm
->mgr
, mstc
->port
, mstc
->pbn
, &slots
);
2962 if (mstm
->outp
->dcb
->sorconf
.link
& 1)
2967 switch (mstc
->connector
.display_info
.bpc
) {
2968 case 6: depth
= 0x2; break;
2969 case 8: depth
= 0x5; break;
2971 default: depth
= 0x6; break;
2974 mstm
->outp
->update(mstm
->outp
, head
->base
.index
,
2975 &head
->base
.base
.state
->adjusted_mode
, proto
, depth
);
2979 mstm
->modified
= true;
2983 nv50_msto_disable(struct drm_encoder
*encoder
)
2985 struct nv50_msto
*msto
= nv50_msto(encoder
);
2986 struct nv50_mstc
*mstc
= msto
->mstc
;
2987 struct nv50_mstm
*mstm
= mstc
->mstm
;
2990 drm_dp_mst_reset_vcpi_slots(&mstm
->mgr
, mstc
->port
);
2992 mstm
->outp
->update(mstm
->outp
, msto
->head
->base
.index
, NULL
, 0, 0);
2993 mstm
->modified
= true;
2994 msto
->disabled
= true;
2997 static const struct drm_encoder_helper_funcs
2999 .disable
= nv50_msto_disable
,
3000 .enable
= nv50_msto_enable
,
3001 .atomic_check
= nv50_msto_atomic_check
,
3005 nv50_msto_destroy(struct drm_encoder
*encoder
)
3007 struct nv50_msto
*msto
= nv50_msto(encoder
);
3008 drm_encoder_cleanup(&msto
->encoder
);
3012 static const struct drm_encoder_funcs
3014 .destroy
= nv50_msto_destroy
,
3018 nv50_msto_new(struct drm_device
*dev
, u32 heads
, const char *name
, int id
,
3019 struct nv50_msto
**pmsto
)
3021 struct nv50_msto
*msto
;
3024 if (!(msto
= *pmsto
= kzalloc(sizeof(*msto
), GFP_KERNEL
)))
3027 ret
= drm_encoder_init(dev
, &msto
->encoder
, &nv50_msto
,
3028 DRM_MODE_ENCODER_DPMST
, "%s-mst-%d", name
, id
);
3035 drm_encoder_helper_add(&msto
->encoder
, &nv50_msto_help
);
3036 msto
->encoder
.possible_crtcs
= heads
;
3040 static struct drm_encoder
*
3041 nv50_mstc_atomic_best_encoder(struct drm_connector
*connector
,
3042 struct drm_connector_state
*connector_state
)
3044 struct nv50_head
*head
= nv50_head(connector_state
->crtc
);
3045 struct nv50_mstc
*mstc
= nv50_mstc(connector
);
3047 struct nv50_mstm
*mstm
= mstc
->mstm
;
3048 return &mstm
->msto
[head
->base
.index
]->encoder
;
3053 static struct drm_encoder
*
3054 nv50_mstc_best_encoder(struct drm_connector
*connector
)
3056 struct nv50_mstc
*mstc
= nv50_mstc(connector
);
3058 struct nv50_mstm
*mstm
= mstc
->mstm
;
3059 return &mstm
->msto
[0]->encoder
;
3064 static enum drm_mode_status
3065 nv50_mstc_mode_valid(struct drm_connector
*connector
,
3066 struct drm_display_mode
*mode
)
3072 nv50_mstc_get_modes(struct drm_connector
*connector
)
3074 struct nv50_mstc
*mstc
= nv50_mstc(connector
);
3077 mstc
->edid
= drm_dp_mst_get_edid(&mstc
->connector
, mstc
->port
->mgr
, mstc
->port
);
3078 drm_mode_connector_update_edid_property(&mstc
->connector
, mstc
->edid
);
3080 ret
= drm_add_edid_modes(&mstc
->connector
, mstc
->edid
);
3081 drm_edid_to_eld(&mstc
->connector
, mstc
->edid
);
3084 if (!mstc
->connector
.display_info
.bpc
)
3085 mstc
->connector
.display_info
.bpc
= 8;
3088 drm_mode_destroy(mstc
->connector
.dev
, mstc
->native
);
3089 mstc
->native
= nouveau_conn_native_mode(&mstc
->connector
);
3093 static const struct drm_connector_helper_funcs
3095 .get_modes
= nv50_mstc_get_modes
,
3096 .mode_valid
= nv50_mstc_mode_valid
,
3097 .best_encoder
= nv50_mstc_best_encoder
,
3098 .atomic_best_encoder
= nv50_mstc_atomic_best_encoder
,
3101 static enum drm_connector_status
3102 nv50_mstc_detect(struct drm_connector
*connector
, bool force
)
3104 struct nv50_mstc
*mstc
= nv50_mstc(connector
);
3106 return connector_status_disconnected
;
3107 return drm_dp_mst_detect_port(connector
, mstc
->port
->mgr
, mstc
->port
);
3111 nv50_mstc_destroy(struct drm_connector
*connector
)
3113 struct nv50_mstc
*mstc
= nv50_mstc(connector
);
3114 drm_connector_cleanup(&mstc
->connector
);
3118 static const struct drm_connector_funcs
3120 .dpms
= drm_atomic_helper_connector_dpms
,
3121 .reset
= nouveau_conn_reset
,
3122 .detect
= nv50_mstc_detect
,
3123 .fill_modes
= drm_helper_probe_single_connector_modes
,
3124 .set_property
= drm_atomic_helper_connector_set_property
,
3125 .destroy
= nv50_mstc_destroy
,
3126 .atomic_duplicate_state
= nouveau_conn_atomic_duplicate_state
,
3127 .atomic_destroy_state
= nouveau_conn_atomic_destroy_state
,
3128 .atomic_set_property
= nouveau_conn_atomic_set_property
,
3129 .atomic_get_property
= nouveau_conn_atomic_get_property
,
3133 nv50_mstc_new(struct nv50_mstm
*mstm
, struct drm_dp_mst_port
*port
,
3134 const char *path
, struct nv50_mstc
**pmstc
)
3136 struct drm_device
*dev
= mstm
->outp
->base
.base
.dev
;
3137 struct nv50_mstc
*mstc
;
3140 if (!(mstc
= *pmstc
= kzalloc(sizeof(*mstc
), GFP_KERNEL
)))
3145 ret
= drm_connector_init(dev
, &mstc
->connector
, &nv50_mstc
,
3146 DRM_MODE_CONNECTOR_DisplayPort
);
3153 drm_connector_helper_add(&mstc
->connector
, &nv50_mstc_help
);
3155 mstc
->connector
.funcs
->reset(&mstc
->connector
);
3156 nouveau_conn_attach_properties(&mstc
->connector
);
3158 for (i
= 0; i
< ARRAY_SIZE(mstm
->msto
) && mstm
->msto
; i
++)
3159 drm_mode_connector_attach_encoder(&mstc
->connector
, &mstm
->msto
[i
]->encoder
);
3161 drm_object_attach_property(&mstc
->connector
.base
, dev
->mode_config
.path_property
, 0);
3162 drm_object_attach_property(&mstc
->connector
.base
, dev
->mode_config
.tile_property
, 0);
3163 drm_mode_connector_set_path_property(&mstc
->connector
, path
);
3168 nv50_mstm_cleanup(struct nv50_mstm
*mstm
)
3170 struct nouveau_drm
*drm
= nouveau_drm(mstm
->outp
->base
.base
.dev
);
3171 struct drm_encoder
*encoder
;
3174 NV_ATOMIC(drm
, "%s: mstm cleanup\n", mstm
->outp
->base
.base
.name
);
3175 ret
= drm_dp_check_act_status(&mstm
->mgr
);
3177 ret
= drm_dp_update_payload_part2(&mstm
->mgr
);
3179 drm_for_each_encoder(encoder
, mstm
->outp
->base
.base
.dev
) {
3180 if (encoder
->encoder_type
== DRM_MODE_ENCODER_DPMST
) {
3181 struct nv50_msto
*msto
= nv50_msto(encoder
);
3182 struct nv50_mstc
*mstc
= msto
->mstc
;
3183 if (mstc
&& mstc
->mstm
== mstm
)
3184 nv50_msto_cleanup(msto
);
3188 mstm
->modified
= false;
3192 nv50_mstm_prepare(struct nv50_mstm
*mstm
)
3194 struct nouveau_drm
*drm
= nouveau_drm(mstm
->outp
->base
.base
.dev
);
3195 struct drm_encoder
*encoder
;
3198 NV_ATOMIC(drm
, "%s: mstm prepare\n", mstm
->outp
->base
.base
.name
);
3199 ret
= drm_dp_update_payload_part1(&mstm
->mgr
);
3201 drm_for_each_encoder(encoder
, mstm
->outp
->base
.base
.dev
) {
3202 if (encoder
->encoder_type
== DRM_MODE_ENCODER_DPMST
) {
3203 struct nv50_msto
*msto
= nv50_msto(encoder
);
3204 struct nv50_mstc
*mstc
= msto
->mstc
;
3205 if (mstc
&& mstc
->mstm
== mstm
)
3206 nv50_msto_prepare(msto
);
3212 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr
*mgr
)
3214 struct nv50_mstm
*mstm
= nv50_mstm(mgr
);
3215 drm_kms_helper_hotplug_event(mstm
->outp
->base
.base
.dev
);
3219 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr
*mgr
,
3220 struct drm_connector
*connector
)
3222 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
3223 struct nv50_mstc
*mstc
= nv50_mstc(connector
);
3225 drm_connector_unregister(&mstc
->connector
);
3227 drm_modeset_lock_all(drm
->dev
);
3228 drm_fb_helper_remove_one_connector(&drm
->fbcon
->helper
, &mstc
->connector
);
3230 drm_modeset_unlock_all(drm
->dev
);
3232 drm_connector_unreference(&mstc
->connector
);
3236 nv50_mstm_register_connector(struct drm_connector
*connector
)
3238 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
3240 drm_modeset_lock_all(drm
->dev
);
3241 drm_fb_helper_add_one_connector(&drm
->fbcon
->helper
, connector
);
3242 drm_modeset_unlock_all(drm
->dev
);
3244 drm_connector_register(connector
);
3247 static struct drm_connector
*
3248 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr
*mgr
,
3249 struct drm_dp_mst_port
*port
, const char *path
)
3251 struct nv50_mstm
*mstm
= nv50_mstm(mgr
);
3252 struct nv50_mstc
*mstc
;
3255 ret
= nv50_mstc_new(mstm
, port
, path
, &mstc
);
3258 mstc
->connector
.funcs
->destroy(&mstc
->connector
);
3262 return &mstc
->connector
;
3265 static const struct drm_dp_mst_topology_cbs
3267 .add_connector
= nv50_mstm_add_connector
,
3268 .register_connector
= nv50_mstm_register_connector
,
3269 .destroy_connector
= nv50_mstm_destroy_connector
,
3270 .hotplug
= nv50_mstm_hotplug
,
3274 nv50_mstm_service(struct nv50_mstm
*mstm
)
3276 struct drm_dp_aux
*aux
= mstm
->mgr
.aux
;
3277 bool handled
= true;
3282 ret
= drm_dp_dpcd_read(aux
, DP_SINK_COUNT_ESI
, esi
, 8);
3284 drm_dp_mst_topology_mgr_set_mst(&mstm
->mgr
, false);
3288 drm_dp_mst_hpd_irq(&mstm
->mgr
, esi
, &handled
);
3292 drm_dp_dpcd_write(aux
, DP_SINK_COUNT_ESI
+ 1, &esi
[1], 3);
3297 nv50_mstm_remove(struct nv50_mstm
*mstm
)
3300 drm_dp_mst_topology_mgr_set_mst(&mstm
->mgr
, false);
3304 nv50_mstm_enable(struct nv50_mstm
*mstm
, u8 dpcd
, int state
)
3306 struct nouveau_encoder
*outp
= mstm
->outp
;
3308 struct nv50_disp_mthd_v1 base
;
3309 struct nv50_disp_sor_dp_mst_link_v0 mst
;
3312 .base
.method
= NV50_DISP_MTHD_V1_SOR_DP_MST_LINK
,
3313 .base
.hasht
= outp
->dcb
->hasht
,
3314 .base
.hashm
= outp
->dcb
->hashm
,
3317 struct nouveau_drm
*drm
= nouveau_drm(outp
->base
.base
.dev
);
3318 struct nvif_object
*disp
= &drm
->display
->disp
;
3322 ret
= drm_dp_dpcd_readb(mstm
->mgr
.aux
, DP_MSTM_CTRL
, &dpcd
);
3330 ret
= drm_dp_dpcd_writeb(mstm
->mgr
.aux
, DP_MSTM_CTRL
, dpcd
);
3335 return nvif_mthd(disp
, 0, &args
, sizeof(args
));
3339 nv50_mstm_detect(struct nv50_mstm
*mstm
, u8 dpcd
[8], int allow
)
3346 if (dpcd
[0] >= 0x12) {
3347 ret
= drm_dp_dpcd_readb(mstm
->mgr
.aux
, DP_MSTM_CAP
, &dpcd
[1]);
3351 if (!(dpcd
[1] & DP_MST_CAP
))
3357 ret
= nv50_mstm_enable(mstm
, dpcd
[0], state
);
3361 ret
= drm_dp_mst_topology_mgr_set_mst(&mstm
->mgr
, state
);
3363 return nv50_mstm_enable(mstm
, dpcd
[0], 0);
3365 return mstm
->mgr
.mst_state
;
3369 nv50_mstm_fini(struct nv50_mstm
*mstm
)
3371 if (mstm
&& mstm
->mgr
.mst_state
)
3372 drm_dp_mst_topology_mgr_suspend(&mstm
->mgr
);
3376 nv50_mstm_init(struct nv50_mstm
*mstm
)
3378 if (mstm
&& mstm
->mgr
.mst_state
)
3379 drm_dp_mst_topology_mgr_resume(&mstm
->mgr
);
3383 nv50_mstm_del(struct nv50_mstm
**pmstm
)
3385 struct nv50_mstm
*mstm
= *pmstm
;
3393 nv50_mstm_new(struct nouveau_encoder
*outp
, struct drm_dp_aux
*aux
, int aux_max
,
3394 int conn_base_id
, struct nv50_mstm
**pmstm
)
3396 const int max_payloads
= hweight8(outp
->dcb
->heads
);
3397 struct drm_device
*dev
= outp
->base
.base
.dev
;
3398 struct nv50_mstm
*mstm
;
3402 /* This is a workaround for some monitors not functioning
3403 * correctly in MST mode on initial module load. I think
3404 * some bad interaction with the VBIOS may be responsible.
3406 * A good ol' off and on again seems to work here ;)
3408 ret
= drm_dp_dpcd_readb(aux
, DP_DPCD_REV
, &dpcd
);
3409 if (ret
>= 0 && dpcd
>= 0x12)
3410 drm_dp_dpcd_writeb(aux
, DP_MSTM_CTRL
, 0);
3412 if (!(mstm
= *pmstm
= kzalloc(sizeof(*mstm
), GFP_KERNEL
)))
3415 mstm
->mgr
.cbs
= &nv50_mstm
;
3417 ret
= drm_dp_mst_topology_mgr_init(&mstm
->mgr
, dev
->dev
, aux
, aux_max
,
3418 max_payloads
, conn_base_id
);
3422 for (i
= 0; i
< max_payloads
; i
++) {
3423 ret
= nv50_msto_new(dev
, outp
->dcb
->heads
, outp
->base
.base
.name
,
3432 /******************************************************************************
3434 *****************************************************************************/
3436 nv50_sor_dpms(struct drm_encoder
*encoder
, int mode
)
3438 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3439 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
3441 struct nv50_disp_mthd_v1 base
;
3442 struct nv50_disp_sor_pwr_v0 pwr
;
3445 .base
.method
= NV50_DISP_MTHD_V1_SOR_PWR
,
3446 .base
.hasht
= nv_encoder
->dcb
->hasht
,
3447 .base
.hashm
= nv_encoder
->dcb
->hashm
,
3448 .pwr
.state
= mode
== DRM_MODE_DPMS_ON
,
3451 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
3455 nv50_sor_update(struct nouveau_encoder
*nv_encoder
, u8 head
,
3456 struct drm_display_mode
*mode
, u8 proto
, u8 depth
)
3458 struct nv50_dmac
*core
= &nv50_mast(nv_encoder
->base
.base
.dev
)->base
;
3462 nv_encoder
->ctrl
&= ~BIT(head
);
3463 if (!(nv_encoder
->ctrl
& 0x0000000f))
3464 nv_encoder
->ctrl
= 0;
3466 nv_encoder
->ctrl
|= proto
<< 8;
3467 nv_encoder
->ctrl
|= BIT(head
);
3470 if ((push
= evo_wait(core
, 6))) {
3471 if (core
->base
.user
.oclass
< GF110_DISP_CORE_CHANNEL_DMA
) {
3473 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3474 nv_encoder
->ctrl
|= 0x00001000;
3475 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3476 nv_encoder
->ctrl
|= 0x00002000;
3477 nv_encoder
->ctrl
|= depth
<< 16;
3479 evo_mthd(push
, 0x0600 + (nv_encoder
->or * 0x40), 1);
3482 u32 magic
= 0x31ec6000 | (head
<< 25);
3483 u32 syncs
= 0x00000001;
3484 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3485 syncs
|= 0x00000008;
3486 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3487 syncs
|= 0x00000010;
3488 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
3489 magic
|= 0x00000001;
3491 evo_mthd(push
, 0x0404 + (head
* 0x300), 2);
3492 evo_data(push
, syncs
| (depth
<< 6));
3493 evo_data(push
, magic
);
3495 evo_mthd(push
, 0x0200 + (nv_encoder
->or * 0x20), 1);
3497 evo_data(push
, nv_encoder
->ctrl
);
3498 evo_kick(push
, core
);
3503 nv50_sor_disable(struct drm_encoder
*encoder
)
3505 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3506 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(nv_encoder
->crtc
);
3508 nv_encoder
->crtc
= NULL
;
3511 struct nvkm_i2c_aux
*aux
= nv_encoder
->aux
;
3515 int ret
= nvkm_rdaux(aux
, DP_SET_POWER
, &pwr
, 1);
3517 pwr
&= ~DP_SET_POWER_MASK
;
3518 pwr
|= DP_SET_POWER_D3
;
3519 nvkm_wraux(aux
, DP_SET_POWER
, &pwr
, 1);
3523 nv_encoder
->update(nv_encoder
, nv_crtc
->index
, NULL
, 0, 0);
3524 nv50_audio_disable(encoder
, nv_crtc
);
3525 nv50_hdmi_disable(&nv_encoder
->base
.base
, nv_crtc
);
3530 nv50_sor_enable(struct drm_encoder
*encoder
)
3532 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3533 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
3534 struct drm_display_mode
*mode
= &nv_crtc
->base
.state
->adjusted_mode
;
3536 struct nv50_disp_mthd_v1 base
;
3537 struct nv50_disp_sor_lvds_script_v0 lvds
;
3540 .base
.method
= NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT
,
3541 .base
.hasht
= nv_encoder
->dcb
->hasht
,
3542 .base
.hashm
= nv_encoder
->dcb
->hashm
,
3544 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
3545 struct drm_device
*dev
= encoder
->dev
;
3546 struct nouveau_drm
*drm
= nouveau_drm(dev
);
3547 struct nouveau_connector
*nv_connector
;
3548 struct nvbios
*bios
= &drm
->vbios
;
3552 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
3553 nv_encoder
->crtc
= encoder
->crtc
;
3555 switch (nv_encoder
->dcb
->type
) {
3556 case DCB_OUTPUT_TMDS
:
3557 if (nv_encoder
->dcb
->sorconf
.link
& 1) {
3559 /* Only enable dual-link if:
3560 * - Need to (i.e. rate > 165MHz)
3562 * - Not an HDMI monitor, since there's no dual-link
3565 if (mode
->clock
>= 165000 &&
3566 nv_encoder
->dcb
->duallink_possible
&&
3567 !drm_detect_hdmi_monitor(nv_connector
->edid
))
3573 nv50_hdmi_enable(&nv_encoder
->base
.base
, mode
);
3575 case DCB_OUTPUT_LVDS
:
3578 if (bios
->fp_no_ddc
) {
3579 if (bios
->fp
.dual_link
)
3580 lvds
.lvds
.script
|= 0x0100;
3581 if (bios
->fp
.if_is_24bit
)
3582 lvds
.lvds
.script
|= 0x0200;
3584 if (nv_connector
->type
== DCB_CONNECTOR_LVDS_SPWG
) {
3585 if (((u8
*)nv_connector
->edid
)[121] == 2)
3586 lvds
.lvds
.script
|= 0x0100;
3588 if (mode
->clock
>= bios
->fp
.duallink_transition_clk
) {
3589 lvds
.lvds
.script
|= 0x0100;
3592 if (lvds
.lvds
.script
& 0x0100) {
3593 if (bios
->fp
.strapless_is_24bit
& 2)
3594 lvds
.lvds
.script
|= 0x0200;
3596 if (bios
->fp
.strapless_is_24bit
& 1)
3597 lvds
.lvds
.script
|= 0x0200;
3600 if (nv_connector
->base
.display_info
.bpc
== 8)
3601 lvds
.lvds
.script
|= 0x0200;
3604 nvif_mthd(disp
->disp
, 0, &lvds
, sizeof(lvds
));
3607 if (nv_connector
->base
.display_info
.bpc
== 6)
3610 if (nv_connector
->base
.display_info
.bpc
== 8)
3615 if (nv_encoder
->dcb
->sorconf
.link
& 1)
3620 nv50_audio_enable(encoder
, mode
);
3627 nv_encoder
->update(nv_encoder
, nv_crtc
->index
, mode
, proto
, depth
);
3630 static const struct drm_encoder_helper_funcs
3632 .dpms
= nv50_sor_dpms
,
3633 .atomic_check
= nv50_outp_atomic_check
,
3634 .enable
= nv50_sor_enable
,
3635 .disable
= nv50_sor_disable
,
3639 nv50_sor_destroy(struct drm_encoder
*encoder
)
3641 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3642 nv50_mstm_del(&nv_encoder
->dp
.mstm
);
3643 drm_encoder_cleanup(encoder
);
3647 static const struct drm_encoder_funcs
3649 .destroy
= nv50_sor_destroy
,
3653 nv50_sor_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
3655 struct nouveau_connector
*nv_connector
= nouveau_connector(connector
);
3656 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
3657 struct nvkm_i2c
*i2c
= nvxx_i2c(&drm
->device
);
3658 struct nouveau_encoder
*nv_encoder
;
3659 struct drm_encoder
*encoder
;
3662 switch (dcbe
->type
) {
3663 case DCB_OUTPUT_LVDS
: type
= DRM_MODE_ENCODER_LVDS
; break;
3664 case DCB_OUTPUT_TMDS
:
3667 type
= DRM_MODE_ENCODER_TMDS
;
3671 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
3674 nv_encoder
->dcb
= dcbe
;
3675 nv_encoder
->or = ffs(dcbe
->or) - 1;
3676 nv_encoder
->update
= nv50_sor_update
;
3678 encoder
= to_drm_encoder(nv_encoder
);
3679 encoder
->possible_crtcs
= dcbe
->heads
;
3680 encoder
->possible_clones
= 0;
3681 drm_encoder_init(connector
->dev
, encoder
, &nv50_sor_func
, type
,
3682 "sor-%04x-%04x", dcbe
->hasht
, dcbe
->hashm
);
3683 drm_encoder_helper_add(encoder
, &nv50_sor_help
);
3685 drm_mode_connector_attach_encoder(connector
, encoder
);
3687 if (dcbe
->type
== DCB_OUTPUT_DP
) {
3688 struct nvkm_i2c_aux
*aux
=
3689 nvkm_i2c_aux_find(i2c
, dcbe
->i2c_index
);
3691 nv_encoder
->i2c
= &aux
->i2c
;
3692 nv_encoder
->aux
= aux
;
3695 /*TODO: Use DP Info Table to check for support. */
3696 if (nv50_disp(encoder
->dev
)->disp
->oclass
>= GF110_DISP
) {
3697 ret
= nv50_mstm_new(nv_encoder
, &nv_connector
->aux
, 16,
3698 nv_connector
->base
.base
.id
,
3699 &nv_encoder
->dp
.mstm
);
3704 struct nvkm_i2c_bus
*bus
=
3705 nvkm_i2c_bus_find(i2c
, dcbe
->i2c_index
);
3707 nv_encoder
->i2c
= &bus
->i2c
;
3713 /******************************************************************************
3715 *****************************************************************************/
3717 nv50_pior_dpms(struct drm_encoder
*encoder
, int mode
)
3719 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3720 struct nv50_disp
*disp
= nv50_disp(encoder
->dev
);
3722 struct nv50_disp_mthd_v1 base
;
3723 struct nv50_disp_pior_pwr_v0 pwr
;
3726 .base
.method
= NV50_DISP_MTHD_V1_PIOR_PWR
,
3727 .base
.hasht
= nv_encoder
->dcb
->hasht
,
3728 .base
.hashm
= nv_encoder
->dcb
->hashm
,
3729 .pwr
.state
= mode
== DRM_MODE_DPMS_ON
,
3730 .pwr
.type
= nv_encoder
->dcb
->type
,
3733 nvif_mthd(disp
->disp
, 0, &args
, sizeof(args
));
3737 nv50_pior_atomic_check(struct drm_encoder
*encoder
,
3738 struct drm_crtc_state
*crtc_state
,
3739 struct drm_connector_state
*conn_state
)
3741 int ret
= nv50_outp_atomic_check(encoder
, crtc_state
, conn_state
);
3744 crtc_state
->adjusted_mode
.clock
*= 2;
3749 nv50_pior_disable(struct drm_encoder
*encoder
)
3751 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3752 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
3753 const int or = nv_encoder
->or;
3756 if (nv_encoder
->crtc
) {
3757 push
= evo_wait(mast
, 4);
3759 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
3760 evo_mthd(push
, 0x0700 + (or * 0x040), 1);
3761 evo_data(push
, 0x00000000);
3763 evo_kick(push
, mast
);
3767 nv_encoder
->crtc
= NULL
;
3771 nv50_pior_enable(struct drm_encoder
*encoder
)
3773 struct nv50_mast
*mast
= nv50_mast(encoder
->dev
);
3774 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
3775 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(encoder
->crtc
);
3776 struct nouveau_connector
*nv_connector
;
3777 struct drm_display_mode
*mode
= &nv_crtc
->base
.state
->adjusted_mode
;
3778 u8 owner
= 1 << nv_crtc
->index
;
3782 nv_connector
= nouveau_encoder_connector_get(nv_encoder
);
3783 switch (nv_connector
->base
.display_info
.bpc
) {
3784 case 10: depth
= 0x6; break;
3785 case 8: depth
= 0x5; break;
3786 case 6: depth
= 0x2; break;
3787 default: depth
= 0x0; break;
3790 switch (nv_encoder
->dcb
->type
) {
3791 case DCB_OUTPUT_TMDS
:
3800 push
= evo_wait(mast
, 8);
3802 if (nv50_vers(mast
) < GF110_DISP_CORE_CHANNEL_DMA
) {
3803 u32 ctrl
= (depth
<< 16) | (proto
<< 8) | owner
;
3804 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3806 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3808 evo_mthd(push
, 0x0700 + (nv_encoder
->or * 0x040), 1);
3809 evo_data(push
, ctrl
);
3812 evo_kick(push
, mast
);
3815 nv_encoder
->crtc
= encoder
->crtc
;
3818 static const struct drm_encoder_helper_funcs
3820 .dpms
= nv50_pior_dpms
,
3821 .atomic_check
= nv50_pior_atomic_check
,
3822 .enable
= nv50_pior_enable
,
3823 .disable
= nv50_pior_disable
,
3827 nv50_pior_destroy(struct drm_encoder
*encoder
)
3829 drm_encoder_cleanup(encoder
);
3833 static const struct drm_encoder_funcs
3835 .destroy
= nv50_pior_destroy
,
3839 nv50_pior_create(struct drm_connector
*connector
, struct dcb_output
*dcbe
)
3841 struct nouveau_drm
*drm
= nouveau_drm(connector
->dev
);
3842 struct nvkm_i2c
*i2c
= nvxx_i2c(&drm
->device
);
3843 struct nvkm_i2c_bus
*bus
= NULL
;
3844 struct nvkm_i2c_aux
*aux
= NULL
;
3845 struct i2c_adapter
*ddc
;
3846 struct nouveau_encoder
*nv_encoder
;
3847 struct drm_encoder
*encoder
;
3850 switch (dcbe
->type
) {
3851 case DCB_OUTPUT_TMDS
:
3852 bus
= nvkm_i2c_bus_find(i2c
, NVKM_I2C_BUS_EXT(dcbe
->extdev
));
3853 ddc
= bus
? &bus
->i2c
: NULL
;
3854 type
= DRM_MODE_ENCODER_TMDS
;
3857 aux
= nvkm_i2c_aux_find(i2c
, NVKM_I2C_AUX_EXT(dcbe
->extdev
));
3858 ddc
= aux
? &aux
->i2c
: NULL
;
3859 type
= DRM_MODE_ENCODER_TMDS
;
3865 nv_encoder
= kzalloc(sizeof(*nv_encoder
), GFP_KERNEL
);
3868 nv_encoder
->dcb
= dcbe
;
3869 nv_encoder
->or = ffs(dcbe
->or) - 1;
3870 nv_encoder
->i2c
= ddc
;
3871 nv_encoder
->aux
= aux
;
3873 encoder
= to_drm_encoder(nv_encoder
);
3874 encoder
->possible_crtcs
= dcbe
->heads
;
3875 encoder
->possible_clones
= 0;
3876 drm_encoder_init(connector
->dev
, encoder
, &nv50_pior_func
, type
,
3877 "pior-%04x-%04x", dcbe
->hasht
, dcbe
->hashm
);
3878 drm_encoder_helper_add(encoder
, &nv50_pior_help
);
3880 drm_mode_connector_attach_encoder(connector
, encoder
);
3884 /******************************************************************************
3886 *****************************************************************************/
3889 nv50_disp_atomic_commit_core(struct nouveau_drm
*drm
, u32 interlock
)
3891 struct nv50_disp
*disp
= nv50_disp(drm
->dev
);
3892 struct nv50_dmac
*core
= &disp
->mast
.base
;
3893 struct nv50_mstm
*mstm
;
3894 struct drm_encoder
*encoder
;
3897 NV_ATOMIC(drm
, "commit core %08x\n", interlock
);
3899 drm_for_each_encoder(encoder
, drm
->dev
) {
3900 if (encoder
->encoder_type
!= DRM_MODE_ENCODER_DPMST
) {
3901 mstm
= nouveau_encoder(encoder
)->dp
.mstm
;
3902 if (mstm
&& mstm
->modified
)
3903 nv50_mstm_prepare(mstm
);
3907 if ((push
= evo_wait(core
, 5))) {
3908 evo_mthd(push
, 0x0084, 1);
3909 evo_data(push
, 0x80000000);
3910 evo_mthd(push
, 0x0080, 2);
3911 evo_data(push
, interlock
);
3912 evo_data(push
, 0x00000000);
3913 nouveau_bo_wr32(disp
->sync
, 0, 0x00000000);
3914 evo_kick(push
, core
);
3915 if (nvif_msec(&drm
->device
, 2000ULL,
3916 if (nouveau_bo_rd32(disp
->sync
, 0))
3920 NV_ERROR(drm
, "EVO timeout\n");
3923 drm_for_each_encoder(encoder
, drm
->dev
) {
3924 if (encoder
->encoder_type
!= DRM_MODE_ENCODER_DPMST
) {
3925 mstm
= nouveau_encoder(encoder
)->dp
.mstm
;
3926 if (mstm
&& mstm
->modified
)
3927 nv50_mstm_cleanup(mstm
);
3933 nv50_disp_atomic_commit_tail(struct drm_atomic_state
*state
)
3935 struct drm_device
*dev
= state
->dev
;
3936 struct drm_crtc_state
*crtc_state
;
3937 struct drm_crtc
*crtc
;
3938 struct drm_plane_state
*plane_state
;
3939 struct drm_plane
*plane
;
3940 struct nouveau_drm
*drm
= nouveau_drm(dev
);
3941 struct nv50_disp
*disp
= nv50_disp(dev
);
3942 struct nv50_atom
*atom
= nv50_atom(state
);
3943 struct nv50_outp_atom
*outp
, *outt
;
3944 u32 interlock_core
= 0;
3945 u32 interlock_chan
= 0;
3948 NV_ATOMIC(drm
, "commit %d %d\n", atom
->lock_core
, atom
->flush_disable
);
3949 drm_atomic_helper_wait_for_fences(dev
, state
, false);
3950 drm_atomic_helper_wait_for_dependencies(state
);
3951 drm_atomic_helper_update_legacy_modeset_state(dev
, state
);
3953 if (atom
->lock_core
)
3954 mutex_lock(&disp
->mutex
);
3956 /* Disable head(s). */
3957 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
3958 struct nv50_head_atom
*asyh
= nv50_head_atom(crtc
->state
);
3959 struct nv50_head
*head
= nv50_head(crtc
);
3961 NV_ATOMIC(drm
, "%s: clr %04x (set %04x)\n", crtc
->name
,
3962 asyh
->clr
.mask
, asyh
->set
.mask
);
3964 if (asyh
->clr
.mask
) {
3965 nv50_head_flush_clr(head
, asyh
, atom
->flush_disable
);
3966 interlock_core
|= 1;
3970 /* Disable plane(s). */
3971 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
3972 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(plane
->state
);
3973 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
3975 NV_ATOMIC(drm
, "%s: clr %02x (set %02x)\n", plane
->name
,
3976 asyw
->clr
.mask
, asyw
->set
.mask
);
3977 if (!asyw
->clr
.mask
)
3980 interlock_chan
|= nv50_wndw_flush_clr(wndw
, interlock_core
,
3981 atom
->flush_disable
,
3985 /* Disable output path(s). */
3986 list_for_each_entry(outp
, &atom
->outp
, head
) {
3987 const struct drm_encoder_helper_funcs
*help
;
3988 struct drm_encoder
*encoder
;
3990 encoder
= outp
->encoder
;
3991 help
= encoder
->helper_private
;
3993 NV_ATOMIC(drm
, "%s: clr %02x (set %02x)\n", encoder
->name
,
3994 outp
->clr
.mask
, outp
->set
.mask
);
3996 if (outp
->clr
.mask
) {
3997 help
->disable(encoder
);
3998 interlock_core
|= 1;
3999 if (outp
->flush_disable
) {
4000 nv50_disp_atomic_commit_core(drm
, interlock_chan
);
4007 /* Flush disable. */
4008 if (interlock_core
) {
4009 if (atom
->flush_disable
) {
4010 nv50_disp_atomic_commit_core(drm
, interlock_chan
);
4016 /* Update output path(s). */
4017 list_for_each_entry_safe(outp
, outt
, &atom
->outp
, head
) {
4018 const struct drm_encoder_helper_funcs
*help
;
4019 struct drm_encoder
*encoder
;
4021 encoder
= outp
->encoder
;
4022 help
= encoder
->helper_private
;
4024 NV_ATOMIC(drm
, "%s: set %02x (clr %02x)\n", encoder
->name
,
4025 outp
->set
.mask
, outp
->clr
.mask
);
4027 if (outp
->set
.mask
) {
4028 help
->enable(encoder
);
4032 list_del(&outp
->head
);
4036 /* Update head(s). */
4037 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
4038 struct nv50_head_atom
*asyh
= nv50_head_atom(crtc
->state
);
4039 struct nv50_head
*head
= nv50_head(crtc
);
4041 NV_ATOMIC(drm
, "%s: set %04x (clr %04x)\n", crtc
->name
,
4042 asyh
->set
.mask
, asyh
->clr
.mask
);
4044 if (asyh
->set
.mask
) {
4045 nv50_head_flush_set(head
, asyh
);
4050 /* Update plane(s). */
4051 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
4052 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(plane
->state
);
4053 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
4055 NV_ATOMIC(drm
, "%s: set %02x (clr %02x)\n", plane
->name
,
4056 asyw
->set
.mask
, asyw
->clr
.mask
);
4057 if ( !asyw
->set
.mask
&&
4058 (!asyw
->clr
.mask
|| atom
->flush_disable
))
4061 interlock_chan
|= nv50_wndw_flush_set(wndw
, interlock_core
, asyw
);
4065 if (interlock_core
) {
4066 if (!interlock_chan
&& atom
->state
.legacy_cursor_update
) {
4067 u32
*push
= evo_wait(&disp
->mast
, 2);
4069 evo_mthd(push
, 0x0080, 1);
4070 evo_data(push
, 0x00000000);
4071 evo_kick(push
, &disp
->mast
);
4074 nv50_disp_atomic_commit_core(drm
, interlock_chan
);
4078 if (atom
->lock_core
)
4079 mutex_unlock(&disp
->mutex
);
4081 /* Wait for HW to signal completion. */
4082 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
4083 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(plane
->state
);
4084 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
4085 int ret
= nv50_wndw_wait_armed(wndw
, asyw
);
4087 NV_ERROR(drm
, "%s: timeout\n", plane
->name
);
4090 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
4091 if (crtc
->state
->event
) {
4092 unsigned long flags
;
4093 /* Get correct count/ts if racing with vblank irq */
4094 drm_accurate_vblank_count(crtc
);
4095 spin_lock_irqsave(&crtc
->dev
->event_lock
, flags
);
4096 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
4097 spin_unlock_irqrestore(&crtc
->dev
->event_lock
, flags
);
4098 crtc
->state
->event
= NULL
;
4102 drm_atomic_helper_commit_hw_done(state
);
4103 drm_atomic_helper_cleanup_planes(dev
, state
);
4104 drm_atomic_helper_commit_cleanup_done(state
);
4105 drm_atomic_state_put(state
);
4109 nv50_disp_atomic_commit_work(struct work_struct
*work
)
4111 struct drm_atomic_state
*state
=
4112 container_of(work
, typeof(*state
), commit_work
);
4113 nv50_disp_atomic_commit_tail(state
);
4117 nv50_disp_atomic_commit(struct drm_device
*dev
,
4118 struct drm_atomic_state
*state
, bool nonblock
)
4120 struct nouveau_drm
*drm
= nouveau_drm(dev
);
4121 struct nv50_disp
*disp
= nv50_disp(dev
);
4122 struct drm_plane_state
*plane_state
;
4123 struct drm_plane
*plane
;
4124 struct drm_crtc
*crtc
;
4125 bool active
= false;
4128 ret
= pm_runtime_get_sync(dev
->dev
);
4129 if (ret
< 0 && ret
!= -EACCES
)
4132 ret
= drm_atomic_helper_setup_commit(state
, nonblock
);
4136 INIT_WORK(&state
->commit_work
, nv50_disp_atomic_commit_work
);
4138 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
4143 ret
= drm_atomic_helper_wait_for_fences(dev
, state
, true);
4148 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
4149 struct nv50_wndw_atom
*asyw
= nv50_wndw_atom(plane_state
);
4150 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
4151 if (asyw
->set
.image
) {
4152 asyw
->ntfy
.handle
= wndw
->dmac
->sync
.handle
;
4153 asyw
->ntfy
.offset
= wndw
->ntfy
;
4154 asyw
->ntfy
.awaken
= false;
4155 asyw
->set
.ntfy
= true;
4156 nouveau_bo_wr32(disp
->sync
, wndw
->ntfy
/ 4, 0x00000000);
4161 drm_atomic_helper_swap_state(state
, true);
4162 drm_atomic_state_get(state
);
4165 queue_work(system_unbound_wq
, &state
->commit_work
);
4167 nv50_disp_atomic_commit_tail(state
);
4169 drm_for_each_crtc(crtc
, dev
) {
4170 if (crtc
->state
->enable
) {
4171 if (!drm
->have_disp_power_ref
) {
4172 drm
->have_disp_power_ref
= true;
4180 if (!active
&& drm
->have_disp_power_ref
) {
4181 pm_runtime_put_autosuspend(dev
->dev
);
4182 drm
->have_disp_power_ref
= false;
4186 pm_runtime_put_autosuspend(dev
->dev
);
4190 static struct nv50_outp_atom
*
4191 nv50_disp_outp_atomic_add(struct nv50_atom
*atom
, struct drm_encoder
*encoder
)
4193 struct nv50_outp_atom
*outp
;
4195 list_for_each_entry(outp
, &atom
->outp
, head
) {
4196 if (outp
->encoder
== encoder
)
4200 outp
= kzalloc(sizeof(*outp
), GFP_KERNEL
);
4202 return ERR_PTR(-ENOMEM
);
4204 list_add(&outp
->head
, &atom
->outp
);
4205 outp
->encoder
= encoder
;
4210 nv50_disp_outp_atomic_check_clr(struct nv50_atom
*atom
,
4211 struct drm_connector
*connector
)
4213 struct drm_encoder
*encoder
= connector
->state
->best_encoder
;
4214 struct drm_crtc_state
*crtc_state
;
4215 struct drm_crtc
*crtc
;
4216 struct nv50_outp_atom
*outp
;
4218 if (!(crtc
= connector
->state
->crtc
))
4221 crtc_state
= drm_atomic_get_existing_crtc_state(&atom
->state
, crtc
);
4222 if (crtc
->state
->active
&& drm_atomic_crtc_needs_modeset(crtc_state
)) {
4223 outp
= nv50_disp_outp_atomic_add(atom
, encoder
);
4225 return PTR_ERR(outp
);
4227 if (outp
->encoder
->encoder_type
== DRM_MODE_ENCODER_DPMST
) {
4228 outp
->flush_disable
= true;
4229 atom
->flush_disable
= true;
4231 outp
->clr
.ctrl
= true;
4232 atom
->lock_core
= true;
4239 nv50_disp_outp_atomic_check_set(struct nv50_atom
*atom
,
4240 struct drm_connector_state
*connector_state
)
4242 struct drm_encoder
*encoder
= connector_state
->best_encoder
;
4243 struct drm_crtc_state
*crtc_state
;
4244 struct drm_crtc
*crtc
;
4245 struct nv50_outp_atom
*outp
;
4247 if (!(crtc
= connector_state
->crtc
))
4250 crtc_state
= drm_atomic_get_existing_crtc_state(&atom
->state
, crtc
);
4251 if (crtc_state
->active
&& drm_atomic_crtc_needs_modeset(crtc_state
)) {
4252 outp
= nv50_disp_outp_atomic_add(atom
, encoder
);
4254 return PTR_ERR(outp
);
4256 outp
->set
.ctrl
= true;
4257 atom
->lock_core
= true;
4264 nv50_disp_atomic_check(struct drm_device
*dev
, struct drm_atomic_state
*state
)
4266 struct nv50_atom
*atom
= nv50_atom(state
);
4267 struct drm_connector_state
*connector_state
;
4268 struct drm_connector
*connector
;
4271 ret
= drm_atomic_helper_check(dev
, state
);
4275 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
4276 ret
= nv50_disp_outp_atomic_check_clr(atom
, connector
);
4280 ret
= nv50_disp_outp_atomic_check_set(atom
, connector_state
);
4289 nv50_disp_atomic_state_clear(struct drm_atomic_state
*state
)
4291 struct nv50_atom
*atom
= nv50_atom(state
);
4292 struct nv50_outp_atom
*outp
, *outt
;
4294 list_for_each_entry_safe(outp
, outt
, &atom
->outp
, head
) {
4295 list_del(&outp
->head
);
4299 drm_atomic_state_default_clear(state
);
4303 nv50_disp_atomic_state_free(struct drm_atomic_state
*state
)
4305 struct nv50_atom
*atom
= nv50_atom(state
);
4306 drm_atomic_state_default_release(&atom
->state
);
4310 static struct drm_atomic_state
*
4311 nv50_disp_atomic_state_alloc(struct drm_device
*dev
)
4313 struct nv50_atom
*atom
;
4314 if (!(atom
= kzalloc(sizeof(*atom
), GFP_KERNEL
)) ||
4315 drm_atomic_state_init(dev
, &atom
->state
) < 0) {
4319 INIT_LIST_HEAD(&atom
->outp
);
4320 return &atom
->state
;
4323 static const struct drm_mode_config_funcs
4325 .fb_create
= nouveau_user_framebuffer_create
,
4326 .output_poll_changed
= nouveau_fbcon_output_poll_changed
,
4327 .atomic_check
= nv50_disp_atomic_check
,
4328 .atomic_commit
= nv50_disp_atomic_commit
,
4329 .atomic_state_alloc
= nv50_disp_atomic_state_alloc
,
4330 .atomic_state_clear
= nv50_disp_atomic_state_clear
,
4331 .atomic_state_free
= nv50_disp_atomic_state_free
,
4334 /******************************************************************************
4336 *****************************************************************************/
4339 nv50_display_fini(struct drm_device
*dev
)
4341 struct nouveau_encoder
*nv_encoder
;
4342 struct drm_encoder
*encoder
;
4343 struct drm_plane
*plane
;
4345 drm_for_each_plane(plane
, dev
) {
4346 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
4347 if (plane
->funcs
!= &nv50_wndw
)
4349 nv50_wndw_fini(wndw
);
4352 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4353 if (encoder
->encoder_type
!= DRM_MODE_ENCODER_DPMST
) {
4354 nv_encoder
= nouveau_encoder(encoder
);
4355 nv50_mstm_fini(nv_encoder
->dp
.mstm
);
4361 nv50_display_init(struct drm_device
*dev
)
4363 struct drm_encoder
*encoder
;
4364 struct drm_plane
*plane
;
4365 struct drm_crtc
*crtc
;
4368 push
= evo_wait(nv50_mast(dev
), 32);
4372 evo_mthd(push
, 0x0088, 1);
4373 evo_data(push
, nv50_mast(dev
)->base
.sync
.handle
);
4374 evo_kick(push
, nv50_mast(dev
));
4376 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4377 if (encoder
->encoder_type
!= DRM_MODE_ENCODER_DPMST
) {
4378 const struct drm_encoder_helper_funcs
*help
;
4379 struct nouveau_encoder
*nv_encoder
;
4381 nv_encoder
= nouveau_encoder(encoder
);
4382 help
= encoder
->helper_private
;
4383 if (help
&& help
->dpms
)
4384 help
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4386 nv50_mstm_init(nv_encoder
->dp
.mstm
);
4390 drm_for_each_crtc(crtc
, dev
) {
4391 nv50_head_lut_load(crtc
);
4394 drm_for_each_plane(plane
, dev
) {
4395 struct nv50_wndw
*wndw
= nv50_wndw(plane
);
4396 if (plane
->funcs
!= &nv50_wndw
)
4398 nv50_wndw_init(wndw
);
4405 nv50_display_destroy(struct drm_device
*dev
)
4407 struct nv50_disp
*disp
= nv50_disp(dev
);
4409 nv50_dmac_destroy(&disp
->mast
.base
, disp
->disp
);
4411 nouveau_bo_unmap(disp
->sync
);
4413 nouveau_bo_unpin(disp
->sync
);
4414 nouveau_bo_ref(NULL
, &disp
->sync
);
4416 nouveau_display(dev
)->priv
= NULL
;
4420 MODULE_PARM_DESC(atomic
, "Expose atomic ioctl (default: disabled)");
4421 static int nouveau_atomic
= 0;
4422 module_param_named(atomic
, nouveau_atomic
, int, 0400);
4425 nv50_display_create(struct drm_device
*dev
)
4427 struct nvif_device
*device
= &nouveau_drm(dev
)->device
;
4428 struct nouveau_drm
*drm
= nouveau_drm(dev
);
4429 struct dcb_table
*dcb
= &drm
->vbios
.dcb
;
4430 struct drm_connector
*connector
, *tmp
;
4431 struct nv50_disp
*disp
;
4432 struct dcb_output
*dcbe
;
4435 disp
= kzalloc(sizeof(*disp
), GFP_KERNEL
);
4439 mutex_init(&disp
->mutex
);
4441 nouveau_display(dev
)->priv
= disp
;
4442 nouveau_display(dev
)->dtor
= nv50_display_destroy
;
4443 nouveau_display(dev
)->init
= nv50_display_init
;
4444 nouveau_display(dev
)->fini
= nv50_display_fini
;
4445 disp
->disp
= &nouveau_display(dev
)->disp
;
4446 dev
->mode_config
.funcs
= &nv50_disp_func
;
4448 dev
->driver
->driver_features
|= DRIVER_ATOMIC
;
4450 /* small shared memory area we use for notifiers and semaphores */
4451 ret
= nouveau_bo_new(dev
, 4096, 0x1000, TTM_PL_FLAG_VRAM
,
4452 0, 0x0000, NULL
, NULL
, &disp
->sync
);
4454 ret
= nouveau_bo_pin(disp
->sync
, TTM_PL_FLAG_VRAM
, true);
4456 ret
= nouveau_bo_map(disp
->sync
);
4458 nouveau_bo_unpin(disp
->sync
);
4461 nouveau_bo_ref(NULL
, &disp
->sync
);
4467 /* allocate master evo channel */
4468 ret
= nv50_core_create(device
, disp
->disp
, disp
->sync
->bo
.offset
,
4473 /* create crtc objects to represent the hw heads */
4474 if (disp
->disp
->oclass
>= GF110_DISP
)
4475 crtcs
= nvif_rd32(&device
->object
, 0x022448);
4479 for (i
= 0; i
< crtcs
; i
++) {
4480 ret
= nv50_head_create(dev
, i
);
4485 /* create encoder/connector objects based on VBIOS DCB table */
4486 for (i
= 0, dcbe
= &dcb
->entry
[0]; i
< dcb
->entries
; i
++, dcbe
++) {
4487 connector
= nouveau_connector_create(dev
, dcbe
->connector
);
4488 if (IS_ERR(connector
))
4491 if (dcbe
->location
== DCB_LOC_ON_CHIP
) {
4492 switch (dcbe
->type
) {
4493 case DCB_OUTPUT_TMDS
:
4494 case DCB_OUTPUT_LVDS
:
4496 ret
= nv50_sor_create(connector
, dcbe
);
4498 case DCB_OUTPUT_ANALOG
:
4499 ret
= nv50_dac_create(connector
, dcbe
);
4506 ret
= nv50_pior_create(connector
, dcbe
);
4510 NV_WARN(drm
, "failed to create encoder %d/%d/%d: %d\n",
4511 dcbe
->location
, dcbe
->type
,
4512 ffs(dcbe
->or) - 1, ret
);
4517 /* cull any connectors we created that don't have an encoder */
4518 list_for_each_entry_safe(connector
, tmp
, &dev
->mode_config
.connector_list
, head
) {
4519 if (connector
->encoder_ids
[0])
4522 NV_WARN(drm
, "%s has no encoders, removing\n",
4524 connector
->funcs
->destroy(connector
);
4529 nv50_display_destroy(dev
);