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drm/nouveau/kms/nv50: separate out viewport commit
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / nouveau / nv50_display.c
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <linux/dma-mapping.h>
26
27 #include <drm/drmP.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_dp_helper.h>
31 #include <drm/drm_fb_helper.h>
32 #include <drm/drm_plane_helper.h>
33
34 #include <nvif/class.h>
35 #include <nvif/cl0002.h>
36 #include <nvif/cl5070.h>
37 #include <nvif/cl507a.h>
38 #include <nvif/cl507b.h>
39 #include <nvif/cl507c.h>
40 #include <nvif/cl507d.h>
41 #include <nvif/cl507e.h>
42
43 #include "nouveau_drv.h"
44 #include "nouveau_dma.h"
45 #include "nouveau_gem.h"
46 #include "nouveau_connector.h"
47 #include "nouveau_encoder.h"
48 #include "nouveau_crtc.h"
49 #include "nouveau_fence.h"
50 #include "nv50_display.h"
51
52 #define EVO_DMA_NR 9
53
54 #define EVO_MASTER (0x00)
55 #define EVO_FLIP(c) (0x01 + (c))
56 #define EVO_OVLY(c) (0x05 + (c))
57 #define EVO_OIMM(c) (0x09 + (c))
58 #define EVO_CURS(c) (0x0d + (c))
59
60 /* offsets in shared sync bo of various structures */
61 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
62 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
63 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
64 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
65
66 /******************************************************************************
67 * Atomic state
68 *****************************************************************************/
69 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
70
71 struct nv50_head_atom {
72 struct drm_crtc_state state;
73
74 struct {
75 u16 iW;
76 u16 iH;
77 u16 oW;
78 u16 oH;
79 } view;
80
81 struct nv50_head_mode {
82 bool interlace;
83 u32 clock;
84 struct {
85 u16 active;
86 u16 synce;
87 u16 blanke;
88 u16 blanks;
89 } h;
90 struct {
91 u32 active;
92 u16 synce;
93 u16 blanke;
94 u16 blanks;
95 u16 blank2s;
96 u16 blank2e;
97 u16 blankus;
98 } v;
99 } mode;
100
101 struct {
102 u32 handle;
103 u64 offset:40;
104 } lut;
105
106 struct {
107 bool visible;
108 u32 handle;
109 u64 offset:40;
110 u8 format;
111 u8 kind:7;
112 u8 layout:1;
113 u8 block:4;
114 u32 pitch:20;
115 u16 x;
116 u16 y;
117 u16 w;
118 u16 h;
119 } core;
120
121 struct {
122 bool visible;
123 u32 handle;
124 u64 offset:40;
125 u8 layout:1;
126 u8 format:1;
127 } curs;
128
129 struct {
130 u8 depth;
131 u8 cpp;
132 u16 x;
133 u16 y;
134 u16 w;
135 u16 h;
136 } base;
137
138 struct {
139 u8 cpp;
140 } ovly;
141
142 union {
143 struct {
144 bool core:1;
145 bool curs:1;
146 };
147 u8 mask;
148 } clr;
149
150 union {
151 struct {
152 bool core:1;
153 bool curs:1;
154 bool view:1;
155 bool mode:1;
156 bool base:1;
157 bool ovly:1;
158 };
159 u16 mask;
160 } set;
161 };
162
163 /******************************************************************************
164 * EVO channel
165 *****************************************************************************/
166
167 struct nv50_chan {
168 struct nvif_object user;
169 struct nvif_device *device;
170 };
171
172 static int
173 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
174 const s32 *oclass, u8 head, void *data, u32 size,
175 struct nv50_chan *chan)
176 {
177 struct nvif_sclass *sclass;
178 int ret, i, n;
179
180 chan->device = device;
181
182 ret = n = nvif_object_sclass_get(disp, &sclass);
183 if (ret < 0)
184 return ret;
185
186 while (oclass[0]) {
187 for (i = 0; i < n; i++) {
188 if (sclass[i].oclass == oclass[0]) {
189 ret = nvif_object_init(disp, 0, oclass[0],
190 data, size, &chan->user);
191 if (ret == 0)
192 nvif_object_map(&chan->user);
193 nvif_object_sclass_put(&sclass);
194 return ret;
195 }
196 }
197 oclass++;
198 }
199
200 nvif_object_sclass_put(&sclass);
201 return -ENOSYS;
202 }
203
204 static void
205 nv50_chan_destroy(struct nv50_chan *chan)
206 {
207 nvif_object_fini(&chan->user);
208 }
209
210 /******************************************************************************
211 * PIO EVO channel
212 *****************************************************************************/
213
214 struct nv50_pioc {
215 struct nv50_chan base;
216 };
217
218 static void
219 nv50_pioc_destroy(struct nv50_pioc *pioc)
220 {
221 nv50_chan_destroy(&pioc->base);
222 }
223
224 static int
225 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
226 const s32 *oclass, u8 head, void *data, u32 size,
227 struct nv50_pioc *pioc)
228 {
229 return nv50_chan_create(device, disp, oclass, head, data, size,
230 &pioc->base);
231 }
232
233 /******************************************************************************
234 * Cursor Immediate
235 *****************************************************************************/
236
237 struct nv50_curs {
238 struct nv50_pioc base;
239 };
240
241 static int
242 nv50_curs_create(struct nvif_device *device, struct nvif_object *disp,
243 int head, struct nv50_curs *curs)
244 {
245 struct nv50_disp_cursor_v0 args = {
246 .head = head,
247 };
248 static const s32 oclass[] = {
249 GK104_DISP_CURSOR,
250 GF110_DISP_CURSOR,
251 GT214_DISP_CURSOR,
252 G82_DISP_CURSOR,
253 NV50_DISP_CURSOR,
254 0
255 };
256
257 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
258 &curs->base);
259 }
260
261 /******************************************************************************
262 * Overlay Immediate
263 *****************************************************************************/
264
265 struct nv50_oimm {
266 struct nv50_pioc base;
267 };
268
269 static int
270 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
271 int head, struct nv50_oimm *oimm)
272 {
273 struct nv50_disp_cursor_v0 args = {
274 .head = head,
275 };
276 static const s32 oclass[] = {
277 GK104_DISP_OVERLAY,
278 GF110_DISP_OVERLAY,
279 GT214_DISP_OVERLAY,
280 G82_DISP_OVERLAY,
281 NV50_DISP_OVERLAY,
282 0
283 };
284
285 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
286 &oimm->base);
287 }
288
289 /******************************************************************************
290 * DMA EVO channel
291 *****************************************************************************/
292
293 struct nv50_dmac {
294 struct nv50_chan base;
295 dma_addr_t handle;
296 u32 *ptr;
297
298 struct nvif_object sync;
299 struct nvif_object vram;
300
301 /* Protects against concurrent pushbuf access to this channel, lock is
302 * grabbed by evo_wait (if the pushbuf reservation is successful) and
303 * dropped again by evo_kick. */
304 struct mutex lock;
305 };
306
307 static void
308 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
309 {
310 struct nvif_device *device = dmac->base.device;
311
312 nvif_object_fini(&dmac->vram);
313 nvif_object_fini(&dmac->sync);
314
315 nv50_chan_destroy(&dmac->base);
316
317 if (dmac->ptr) {
318 struct device *dev = nvxx_device(device)->dev;
319 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
320 }
321 }
322
323 static int
324 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
325 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
326 struct nv50_dmac *dmac)
327 {
328 struct nv50_disp_core_channel_dma_v0 *args = data;
329 struct nvif_object pushbuf;
330 int ret;
331
332 mutex_init(&dmac->lock);
333
334 dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
335 &dmac->handle, GFP_KERNEL);
336 if (!dmac->ptr)
337 return -ENOMEM;
338
339 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
340 &(struct nv_dma_v0) {
341 .target = NV_DMA_V0_TARGET_PCI_US,
342 .access = NV_DMA_V0_ACCESS_RD,
343 .start = dmac->handle + 0x0000,
344 .limit = dmac->handle + 0x0fff,
345 }, sizeof(struct nv_dma_v0), &pushbuf);
346 if (ret)
347 return ret;
348
349 args->pushbuf = nvif_handle(&pushbuf);
350
351 ret = nv50_chan_create(device, disp, oclass, head, data, size,
352 &dmac->base);
353 nvif_object_fini(&pushbuf);
354 if (ret)
355 return ret;
356
357 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
358 &(struct nv_dma_v0) {
359 .target = NV_DMA_V0_TARGET_VRAM,
360 .access = NV_DMA_V0_ACCESS_RDWR,
361 .start = syncbuf + 0x0000,
362 .limit = syncbuf + 0x0fff,
363 }, sizeof(struct nv_dma_v0),
364 &dmac->sync);
365 if (ret)
366 return ret;
367
368 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
369 &(struct nv_dma_v0) {
370 .target = NV_DMA_V0_TARGET_VRAM,
371 .access = NV_DMA_V0_ACCESS_RDWR,
372 .start = 0,
373 .limit = device->info.ram_user - 1,
374 }, sizeof(struct nv_dma_v0),
375 &dmac->vram);
376 if (ret)
377 return ret;
378
379 return ret;
380 }
381
382 /******************************************************************************
383 * Core
384 *****************************************************************************/
385
386 struct nv50_mast {
387 struct nv50_dmac base;
388 };
389
390 static int
391 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
392 u64 syncbuf, struct nv50_mast *core)
393 {
394 struct nv50_disp_core_channel_dma_v0 args = {
395 .pushbuf = 0xb0007d00,
396 };
397 static const s32 oclass[] = {
398 GP104_DISP_CORE_CHANNEL_DMA,
399 GP100_DISP_CORE_CHANNEL_DMA,
400 GM200_DISP_CORE_CHANNEL_DMA,
401 GM107_DISP_CORE_CHANNEL_DMA,
402 GK110_DISP_CORE_CHANNEL_DMA,
403 GK104_DISP_CORE_CHANNEL_DMA,
404 GF110_DISP_CORE_CHANNEL_DMA,
405 GT214_DISP_CORE_CHANNEL_DMA,
406 GT206_DISP_CORE_CHANNEL_DMA,
407 GT200_DISP_CORE_CHANNEL_DMA,
408 G82_DISP_CORE_CHANNEL_DMA,
409 NV50_DISP_CORE_CHANNEL_DMA,
410 0
411 };
412
413 return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
414 syncbuf, &core->base);
415 }
416
417 /******************************************************************************
418 * Base
419 *****************************************************************************/
420
421 struct nv50_sync {
422 struct nv50_dmac base;
423 u32 addr;
424 u32 data;
425 };
426
427 static int
428 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
429 int head, u64 syncbuf, struct nv50_sync *base)
430 {
431 struct nv50_disp_base_channel_dma_v0 args = {
432 .pushbuf = 0xb0007c00 | head,
433 .head = head,
434 };
435 static const s32 oclass[] = {
436 GK110_DISP_BASE_CHANNEL_DMA,
437 GK104_DISP_BASE_CHANNEL_DMA,
438 GF110_DISP_BASE_CHANNEL_DMA,
439 GT214_DISP_BASE_CHANNEL_DMA,
440 GT200_DISP_BASE_CHANNEL_DMA,
441 G82_DISP_BASE_CHANNEL_DMA,
442 NV50_DISP_BASE_CHANNEL_DMA,
443 0
444 };
445
446 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
447 syncbuf, &base->base);
448 }
449
450 /******************************************************************************
451 * Overlay
452 *****************************************************************************/
453
454 struct nv50_ovly {
455 struct nv50_dmac base;
456 };
457
458 static int
459 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
460 int head, u64 syncbuf, struct nv50_ovly *ovly)
461 {
462 struct nv50_disp_overlay_channel_dma_v0 args = {
463 .pushbuf = 0xb0007e00 | head,
464 .head = head,
465 };
466 static const s32 oclass[] = {
467 GK104_DISP_OVERLAY_CONTROL_DMA,
468 GF110_DISP_OVERLAY_CONTROL_DMA,
469 GT214_DISP_OVERLAY_CHANNEL_DMA,
470 GT200_DISP_OVERLAY_CHANNEL_DMA,
471 G82_DISP_OVERLAY_CHANNEL_DMA,
472 NV50_DISP_OVERLAY_CHANNEL_DMA,
473 0
474 };
475
476 return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
477 syncbuf, &ovly->base);
478 }
479
480 struct nv50_head {
481 struct nouveau_crtc base;
482 struct nouveau_bo *image;
483 struct nv50_curs curs;
484 struct nv50_sync sync;
485 struct nv50_ovly ovly;
486 struct nv50_oimm oimm;
487
488 struct nv50_head_atom arm;
489 struct nv50_head_atom asy;
490 };
491
492 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
493 #define nv50_curs(c) (&nv50_head(c)->curs)
494 #define nv50_sync(c) (&nv50_head(c)->sync)
495 #define nv50_ovly(c) (&nv50_head(c)->ovly)
496 #define nv50_oimm(c) (&nv50_head(c)->oimm)
497 #define nv50_chan(c) (&(c)->base.base)
498 #define nv50_vers(c) nv50_chan(c)->user.oclass
499
500 struct nv50_fbdma {
501 struct list_head head;
502 struct nvif_object core;
503 struct nvif_object base[4];
504 };
505
506 struct nv50_disp {
507 struct nvif_object *disp;
508 struct nv50_mast mast;
509
510 struct list_head fbdma;
511
512 struct nouveau_bo *sync;
513 };
514
515 static struct nv50_disp *
516 nv50_disp(struct drm_device *dev)
517 {
518 return nouveau_display(dev)->priv;
519 }
520
521 #define nv50_mast(d) (&nv50_disp(d)->mast)
522
523 static struct drm_crtc *
524 nv50_display_crtc_get(struct drm_encoder *encoder)
525 {
526 return nouveau_encoder(encoder)->crtc;
527 }
528
529 /******************************************************************************
530 * EVO channel helpers
531 *****************************************************************************/
532 static u32 *
533 evo_wait(void *evoc, int nr)
534 {
535 struct nv50_dmac *dmac = evoc;
536 struct nvif_device *device = dmac->base.device;
537 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
538
539 mutex_lock(&dmac->lock);
540 if (put + nr >= (PAGE_SIZE / 4) - 8) {
541 dmac->ptr[put] = 0x20000000;
542
543 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
544 if (nvif_msec(device, 2000,
545 if (!nvif_rd32(&dmac->base.user, 0x0004))
546 break;
547 ) < 0) {
548 mutex_unlock(&dmac->lock);
549 printk(KERN_ERR "nouveau: evo channel stalled\n");
550 return NULL;
551 }
552
553 put = 0;
554 }
555
556 return dmac->ptr + put;
557 }
558
559 static void
560 evo_kick(u32 *push, void *evoc)
561 {
562 struct nv50_dmac *dmac = evoc;
563 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
564 mutex_unlock(&dmac->lock);
565 }
566
567 #define evo_mthd(p,m,s) do { \
568 const u32 _m = (m), _s = (s); \
569 if (drm_debug & DRM_UT_KMS) \
570 printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__); \
571 *((p)++) = ((_s << 18) | _m); \
572 } while(0)
573
574 #define evo_data(p,d) do { \
575 const u32 _d = (d); \
576 if (drm_debug & DRM_UT_KMS) \
577 printk(KERN_ERR "\t%08x\n", _d); \
578 *((p)++) = _d; \
579 } while(0)
580
581 static bool
582 evo_sync_wait(void *data)
583 {
584 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
585 return true;
586 usleep_range(1, 2);
587 return false;
588 }
589
590 static int
591 evo_sync(struct drm_device *dev)
592 {
593 struct nvif_device *device = &nouveau_drm(dev)->device;
594 struct nv50_disp *disp = nv50_disp(dev);
595 struct nv50_mast *mast = nv50_mast(dev);
596 u32 *push = evo_wait(mast, 8);
597 if (push) {
598 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
599 evo_mthd(push, 0x0084, 1);
600 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
601 evo_mthd(push, 0x0080, 2);
602 evo_data(push, 0x00000000);
603 evo_data(push, 0x00000000);
604 evo_kick(push, mast);
605 if (nvif_msec(device, 2000,
606 if (evo_sync_wait(disp->sync))
607 break;
608 ) >= 0)
609 return 0;
610 }
611
612 return -EBUSY;
613 }
614
615 /******************************************************************************
616 * Page flipping channel
617 *****************************************************************************/
618 struct nouveau_bo *
619 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
620 {
621 return nv50_disp(dev)->sync;
622 }
623
624 struct nv50_display_flip {
625 struct nv50_disp *disp;
626 struct nv50_sync *chan;
627 };
628
629 static bool
630 nv50_display_flip_wait(void *data)
631 {
632 struct nv50_display_flip *flip = data;
633 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
634 flip->chan->data)
635 return true;
636 usleep_range(1, 2);
637 return false;
638 }
639
640 void
641 nv50_display_flip_stop(struct drm_crtc *crtc)
642 {
643 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
644 struct nv50_display_flip flip = {
645 .disp = nv50_disp(crtc->dev),
646 .chan = nv50_sync(crtc),
647 };
648 u32 *push;
649
650 push = evo_wait(flip.chan, 8);
651 if (push) {
652 evo_mthd(push, 0x0084, 1);
653 evo_data(push, 0x00000000);
654 evo_mthd(push, 0x0094, 1);
655 evo_data(push, 0x00000000);
656 evo_mthd(push, 0x00c0, 1);
657 evo_data(push, 0x00000000);
658 evo_mthd(push, 0x0080, 1);
659 evo_data(push, 0x00000000);
660 evo_kick(push, flip.chan);
661 }
662
663 nvif_msec(device, 2000,
664 if (nv50_display_flip_wait(&flip))
665 break;
666 );
667 }
668
669 int
670 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
671 struct nouveau_channel *chan, u32 swap_interval)
672 {
673 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
674 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
675 struct nv50_head *head = nv50_head(crtc);
676 struct nv50_sync *sync = nv50_sync(crtc);
677 u32 *push;
678 int ret;
679
680 if (crtc->primary->fb->width != fb->width ||
681 crtc->primary->fb->height != fb->height)
682 return -EINVAL;
683
684 swap_interval <<= 4;
685 if (swap_interval == 0)
686 swap_interval |= 0x100;
687 if (chan == NULL)
688 evo_sync(crtc->dev);
689
690 push = evo_wait(sync, 128);
691 if (unlikely(push == NULL))
692 return -EBUSY;
693
694 if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
695 ret = RING_SPACE(chan, 8);
696 if (ret)
697 return ret;
698
699 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
700 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
701 OUT_RING (chan, sync->addr ^ 0x10);
702 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
703 OUT_RING (chan, sync->data + 1);
704 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
705 OUT_RING (chan, sync->addr);
706 OUT_RING (chan, sync->data);
707 } else
708 if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
709 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
710 ret = RING_SPACE(chan, 12);
711 if (ret)
712 return ret;
713
714 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
715 OUT_RING (chan, chan->vram.handle);
716 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
717 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
718 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
719 OUT_RING (chan, sync->data + 1);
720 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
721 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
722 OUT_RING (chan, upper_32_bits(addr));
723 OUT_RING (chan, lower_32_bits(addr));
724 OUT_RING (chan, sync->data);
725 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
726 } else
727 if (chan) {
728 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
729 ret = RING_SPACE(chan, 10);
730 if (ret)
731 return ret;
732
733 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
734 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
735 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
736 OUT_RING (chan, sync->data + 1);
737 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
738 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
739 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
740 OUT_RING (chan, upper_32_bits(addr));
741 OUT_RING (chan, lower_32_bits(addr));
742 OUT_RING (chan, sync->data);
743 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
744 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
745 }
746
747 if (chan) {
748 sync->addr ^= 0x10;
749 sync->data++;
750 FIRE_RING (chan);
751 }
752
753 /* queue the flip */
754 evo_mthd(push, 0x0100, 1);
755 evo_data(push, 0xfffe0000);
756 evo_mthd(push, 0x0084, 1);
757 evo_data(push, swap_interval);
758 if (!(swap_interval & 0x00000100)) {
759 evo_mthd(push, 0x00e0, 1);
760 evo_data(push, 0x40000000);
761 }
762 evo_mthd(push, 0x0088, 4);
763 evo_data(push, sync->addr);
764 evo_data(push, sync->data++);
765 evo_data(push, sync->data);
766 evo_data(push, sync->base.sync.handle);
767 evo_mthd(push, 0x00a0, 2);
768 evo_data(push, 0x00000000);
769 evo_data(push, 0x00000000);
770 evo_mthd(push, 0x00c0, 1);
771 evo_data(push, nv_fb->r_handle);
772 evo_mthd(push, 0x0110, 2);
773 evo_data(push, 0x00000000);
774 evo_data(push, 0x00000000);
775 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
776 evo_mthd(push, 0x0800, 5);
777 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
778 evo_data(push, 0);
779 evo_data(push, (fb->height << 16) | fb->width);
780 evo_data(push, nv_fb->r_pitch);
781 evo_data(push, nv_fb->r_format);
782 } else {
783 evo_mthd(push, 0x0400, 5);
784 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
785 evo_data(push, 0);
786 evo_data(push, (fb->height << 16) | fb->width);
787 evo_data(push, nv_fb->r_pitch);
788 evo_data(push, nv_fb->r_format);
789 }
790 evo_mthd(push, 0x0080, 1);
791 evo_data(push, 0x00000000);
792 evo_kick(push, sync);
793
794 nouveau_bo_ref(nv_fb->nvbo, &head->image);
795 return 0;
796 }
797
798 /******************************************************************************
799 * Head
800 *****************************************************************************/
801 static void
802 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
803 {
804 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
805 u32 bounds = 0;
806 u32 *push;
807
808 if (asyh->base.cpp) {
809 switch (asyh->base.cpp) {
810 case 8: bounds |= 0x00000500; break;
811 case 4: bounds |= 0x00000300; break;
812 case 2: bounds |= 0x00000100; break;
813 default:
814 WARN_ON(1);
815 break;
816 }
817 bounds |= 0x00000001;
818 }
819
820 if ((push = evo_wait(core, 2))) {
821 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
822 evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
823 else
824 evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
825 evo_data(push, bounds);
826 evo_kick(push, core);
827 }
828 }
829
830 static void
831 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
832 {
833 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
834 u32 bounds = 0;
835 u32 *push;
836
837 if (asyh->base.cpp) {
838 switch (asyh->base.cpp) {
839 case 8: bounds |= 0x00000500; break;
840 case 4: bounds |= 0x00000300; break;
841 case 2: bounds |= 0x00000100; break;
842 case 1: bounds |= 0x00000000; break;
843 default:
844 WARN_ON(1);
845 break;
846 }
847 bounds |= 0x00000001;
848 }
849
850 if ((push = evo_wait(core, 2))) {
851 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
852 evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
853 else
854 evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
855 evo_data(push, bounds);
856 evo_kick(push, core);
857 }
858 }
859
860 static void
861 nv50_head_curs_clr(struct nv50_head *head)
862 {
863 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
864 u32 *push;
865 if ((push = evo_wait(core, 4))) {
866 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
867 evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
868 evo_data(push, 0x05000000);
869 } else
870 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
871 evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
872 evo_data(push, 0x05000000);
873 evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
874 evo_data(push, 0x00000000);
875 } else {
876 evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
877 evo_data(push, 0x05000000);
878 evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
879 evo_data(push, 0x00000000);
880 }
881 evo_kick(push, core);
882 }
883 }
884
885 static void
886 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
887 {
888 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
889 u32 *push;
890 if ((push = evo_wait(core, 5))) {
891 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
892 evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
893 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
894 (asyh->curs.format << 24));
895 evo_data(push, asyh->curs.offset >> 8);
896 } else
897 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
898 evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
899 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
900 (asyh->curs.format << 24));
901 evo_data(push, asyh->curs.offset >> 8);
902 evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
903 evo_data(push, asyh->curs.handle);
904 } else {
905 evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
906 evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
907 (asyh->curs.format << 24));
908 evo_data(push, asyh->curs.offset >> 8);
909 evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
910 evo_data(push, asyh->curs.handle);
911 }
912 evo_kick(push, core);
913 }
914 }
915
916 static void
917 nv50_head_core_clr(struct nv50_head *head)
918 {
919 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
920 u32 *push;
921 if ((push = evo_wait(core, 2))) {
922 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
923 evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
924 else
925 evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
926 evo_data(push, 0x00000000);
927 evo_kick(push, core);
928 }
929 }
930
931 static void
932 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
933 {
934 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
935 u32 *push;
936 if ((push = evo_wait(core, 9))) {
937 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
938 evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
939 evo_data(push, asyh->core.offset >> 8);
940 evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
941 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
942 evo_data(push, asyh->core.layout << 20 |
943 (asyh->core.pitch >> 8) << 8 |
944 asyh->core.block);
945 evo_data(push, asyh->core.kind << 16 |
946 asyh->core.format << 8);
947 evo_data(push, asyh->core.handle);
948 evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
949 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
950 } else
951 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
952 evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
953 evo_data(push, asyh->core.offset >> 8);
954 evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
955 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
956 evo_data(push, asyh->core.layout << 20 |
957 (asyh->core.pitch >> 8) << 8 |
958 asyh->core.block);
959 evo_data(push, asyh->core.format << 8);
960 evo_data(push, asyh->core.handle);
961 evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
962 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
963 } else {
964 evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
965 evo_data(push, asyh->core.offset >> 8);
966 evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
967 evo_data(push, (asyh->core.h << 16) | asyh->core.w);
968 evo_data(push, asyh->core.layout << 24 |
969 (asyh->core.pitch >> 8) << 8 |
970 asyh->core.block);
971 evo_data(push, asyh->core.format << 8);
972 evo_data(push, asyh->core.handle);
973 evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
974 evo_data(push, (asyh->core.y << 16) | asyh->core.x);
975 }
976 evo_kick(push, core);
977 }
978 }
979
980 static void
981 nv50_head_lut_clr(struct nv50_head *head)
982 {
983 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
984 u32 *push;
985 if ((push = evo_wait(core, 4))) {
986 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
987 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
988 evo_data(push, 0x40000000);
989 } else
990 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
991 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
992 evo_data(push, 0x40000000);
993 evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
994 evo_data(push, 0x00000000);
995 } else {
996 evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
997 evo_data(push, 0x03000000);
998 evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
999 evo_data(push, 0x00000000);
1000 }
1001 evo_kick(push, core);
1002 }
1003 }
1004
1005 static void
1006 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1007 {
1008 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1009 u32 *push;
1010 if ((push = evo_wait(core, 7))) {
1011 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1012 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1013 evo_data(push, 0xc0000000);
1014 evo_data(push, asyh->lut.offset >> 8);
1015 } else
1016 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1017 evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1018 evo_data(push, 0xc0000000);
1019 evo_data(push, asyh->lut.offset >> 8);
1020 evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1021 evo_data(push, asyh->lut.handle);
1022 } else {
1023 evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1024 evo_data(push, 0x83000000);
1025 evo_data(push, asyh->lut.offset >> 8);
1026 evo_data(push, 0x00000000);
1027 evo_data(push, 0x00000000);
1028 evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1029 evo_data(push, asyh->lut.handle);
1030 }
1031 evo_kick(push, core);
1032 }
1033 }
1034
1035 static void
1036 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1037 {
1038 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1039 struct nv50_head_mode *m = &asyh->mode;
1040 u32 *push;
1041 if ((push = evo_wait(core, 14))) {
1042 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1043 evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1044 evo_data(push, 0x00800000 | m->clock);
1045 evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1046 evo_mthd(push, 0x0810 + (head->base.index * 0x400), 6);
1047 evo_data(push, 0x00000000);
1048 evo_data(push, (m->v.active << 16) | m->h.active );
1049 evo_data(push, (m->v.synce << 16) | m->h.synce );
1050 evo_data(push, (m->v.blanke << 16) | m->h.blanke );
1051 evo_data(push, (m->v.blanks << 16) | m->h.blanks );
1052 evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1053 evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1054 evo_data(push, 0x00000000);
1055 } else {
1056 evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1057 evo_data(push, 0x00000000);
1058 evo_data(push, (m->v.active << 16) | m->h.active );
1059 evo_data(push, (m->v.synce << 16) | m->h.synce );
1060 evo_data(push, (m->v.blanke << 16) | m->h.blanke );
1061 evo_data(push, (m->v.blanks << 16) | m->h.blanks );
1062 evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1063 evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1064 evo_data(push, 0x00000000); /* ??? */
1065 evo_data(push, 0xffffff00);
1066 evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1067 evo_data(push, m->clock * 1000);
1068 evo_data(push, 0x00200000); /* ??? */
1069 evo_data(push, m->clock * 1000);
1070 }
1071 evo_kick(push, core);
1072 }
1073 }
1074
1075 static void
1076 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1077 {
1078 struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1079 u32 *push;
1080 if ((push = evo_wait(core, 10))) {
1081 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1082 evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1083 evo_data(push, 0x00000000);
1084 evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1085 evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1086 evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1087 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1088 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1089 } else {
1090 evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1091 evo_data(push, 0x00000000);
1092 evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1093 evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1094 evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1095 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1096 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1097 evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1098 }
1099 evo_kick(push, core);
1100 }
1101 }
1102
1103 static void
1104 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1105 {
1106 if (asyh->clr.core && (!asyh->set.core || y))
1107 nv50_head_lut_clr(head);
1108 if (asyh->clr.core && (!asyh->set.core || y))
1109 nv50_head_core_clr(head);
1110 if (asyh->clr.curs && (!asyh->set.curs || y))
1111 nv50_head_curs_clr(head);
1112 }
1113
1114 static void
1115 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1116 {
1117 if (asyh->set.view ) nv50_head_view (head, asyh);
1118 if (asyh->set.mode ) nv50_head_mode (head, asyh);
1119 if (asyh->set.core ) nv50_head_lut_set (head, asyh);
1120 if (asyh->set.core ) nv50_head_core_set(head, asyh);
1121 if (asyh->set.curs ) nv50_head_curs_set(head, asyh);
1122 if (asyh->set.base ) nv50_head_base (head, asyh);
1123 if (asyh->set.ovly ) nv50_head_ovly (head, asyh);
1124 }
1125
1126 static void
1127 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1128 struct nv50_head_atom *asyh,
1129 struct nouveau_conn_atom *asyc)
1130 {
1131 struct drm_connector *connector = asyc->state.connector;
1132 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1133 struct drm_display_mode *umode = &asyh->state.mode;
1134 int mode = asyc->scaler.mode;
1135 struct edid *edid;
1136
1137 if (connector->edid_blob_ptr)
1138 edid = (struct edid *)connector->edid_blob_ptr->data;
1139 else
1140 edid = NULL;
1141
1142 if (!asyc->scaler.full) {
1143 if (mode == DRM_MODE_SCALE_NONE)
1144 omode = umode;
1145 } else {
1146 /* Non-EDID LVDS/eDP mode. */
1147 mode = DRM_MODE_SCALE_FULLSCREEN;
1148 }
1149
1150 asyh->view.iW = umode->hdisplay;
1151 asyh->view.iH = umode->vdisplay;
1152 asyh->view.oW = omode->hdisplay;
1153 asyh->view.oH = omode->vdisplay;
1154 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
1155 asyh->view.oH *= 2;
1156
1157 /* Add overscan compensation if necessary, will keep the aspect
1158 * ratio the same as the backend mode unless overridden by the
1159 * user setting both hborder and vborder properties.
1160 */
1161 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
1162 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
1163 drm_detect_hdmi_monitor(edid)))) {
1164 u32 bX = asyc->scaler.underscan.hborder;
1165 u32 bY = asyc->scaler.underscan.vborder;
1166 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
1167
1168 if (bX) {
1169 asyh->view.oW -= (bX * 2);
1170 if (bY) asyh->view.oH -= (bY * 2);
1171 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
1172 } else {
1173 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
1174 if (bY) asyh->view.oH -= (bY * 2);
1175 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
1176 }
1177 }
1178
1179 /* Handle CENTER/ASPECT scaling, taking into account the areas
1180 * removed already for overscan compensation.
1181 */
1182 switch (mode) {
1183 case DRM_MODE_SCALE_CENTER:
1184 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
1185 asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH);
1186 /* fall-through */
1187 case DRM_MODE_SCALE_ASPECT:
1188 if (asyh->view.oH < asyh->view.oW) {
1189 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
1190 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
1191 } else {
1192 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
1193 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
1194 }
1195 break;
1196 default:
1197 break;
1198 }
1199
1200 asyh->set.view = true;
1201 }
1202
1203 static void
1204 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1205 {
1206 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1207 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1208 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1209 u32 hbackp = mode->htotal - mode->hsync_end;
1210 u32 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1211 u32 hfrontp = mode->hsync_start - mode->hdisplay;
1212 u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1213 struct nv50_head_mode *m = &asyh->mode;
1214
1215 m->h.active = mode->htotal;
1216 m->h.synce = mode->hsync_end - mode->hsync_start - 1;
1217 m->h.blanke = m->h.synce + hbackp;
1218 m->h.blanks = mode->htotal - hfrontp - 1;
1219
1220 m->v.active = mode->vtotal * vscan / ilace;
1221 m->v.synce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1222 m->v.blanke = m->v.synce + vbackp;
1223 m->v.blanks = m->v.active - vfrontp - 1;
1224
1225 /*XXX: Safe underestimate, even "0" works */
1226 m->v.blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
1227 m->v.blankus *= 1000;
1228 m->v.blankus /= mode->clock;
1229
1230 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1231 m->v.blank2e = m->v.active + m->v.synce + vbackp;
1232 m->v.blank2s = m->v.blank2e + (mode->vdisplay * vscan / ilace);
1233 m->v.active = (m->v.active * 2) + 1;
1234 m->interlace = true;
1235 } else {
1236 m->v.blank2e = 0;
1237 m->v.blank2s = 1;
1238 m->interlace = false;
1239 }
1240 m->clock = mode->clock;
1241
1242 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
1243 asyh->set.mode = true;
1244 }
1245
1246 static int
1247 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
1248 {
1249 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1250 struct nv50_disp *disp = nv50_disp(crtc->dev);
1251 struct nv50_head *head = nv50_head(crtc);
1252 struct nv50_head_atom *armh = &head->arm;
1253 struct nv50_head_atom *asyh = nv50_head_atom(state);
1254
1255 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
1256 asyh->clr.mask = 0;
1257 asyh->set.mask = 0;
1258
1259 if (asyh->state.active) {
1260 if (asyh->state.mode_changed)
1261 nv50_head_atomic_check_mode(head, asyh);
1262
1263 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
1264 asyh->core.x = asyh->base.x;
1265 asyh->core.y = asyh->base.y;
1266 asyh->core.w = asyh->base.w;
1267 asyh->core.h = asyh->base.h;
1268 } else
1269 if ((asyh->core.visible = asyh->curs.visible)) {
1270 /*XXX: We need to either find some way of having the
1271 * primary base layer appear black, while still
1272 * being able to display the other layers, or we
1273 * need to allocate a dummy black surface here.
1274 */
1275 asyh->core.x = 0;
1276 asyh->core.y = 0;
1277 asyh->core.w = asyh->state.mode.hdisplay;
1278 asyh->core.h = asyh->state.mode.vdisplay;
1279 }
1280 asyh->core.handle = disp->mast.base.vram.handle;
1281 asyh->core.offset = 0;
1282 asyh->core.format = 0xcf;
1283 asyh->core.kind = 0;
1284 asyh->core.layout = 1;
1285 asyh->core.block = 0;
1286 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
1287 asyh->lut.handle = disp->mast.base.vram.handle;
1288 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
1289 asyh->set.base = armh->base.cpp != asyh->base.cpp;
1290 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
1291 } else {
1292 asyh->core.visible = false;
1293 asyh->curs.visible = false;
1294 asyh->base.cpp = 0;
1295 asyh->ovly.cpp = 0;
1296 }
1297
1298 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
1299 if (asyh->core.visible) {
1300 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
1301 asyh->set.core = true;
1302 } else
1303 if (armh->core.visible) {
1304 asyh->clr.core = true;
1305 }
1306
1307 if (asyh->curs.visible) {
1308 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
1309 asyh->set.curs = true;
1310 } else
1311 if (armh->curs.visible) {
1312 asyh->clr.curs = true;
1313 }
1314 } else {
1315 asyh->clr.core = armh->core.visible;
1316 asyh->clr.curs = armh->curs.visible;
1317 asyh->set.core = asyh->core.visible;
1318 asyh->set.curs = asyh->curs.visible;
1319 }
1320
1321 memcpy(armh, asyh, sizeof(*asyh));
1322 asyh->state.mode_changed = 0;
1323 return 0;
1324 }
1325
1326 /******************************************************************************
1327 * CRTC
1328 *****************************************************************************/
1329 static int
1330 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
1331 {
1332 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1333 struct nouveau_connector *nv_connector;
1334 struct drm_connector *connector;
1335 u32 *push, mode = 0x00;
1336
1337 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1338 connector = &nv_connector->base;
1339 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
1340 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
1341 mode = DITHERING_MODE_DYNAMIC2X2;
1342 } else {
1343 mode = nv_connector->dithering_mode;
1344 }
1345
1346 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
1347 if (connector->display_info.bpc >= 8)
1348 mode |= DITHERING_DEPTH_8BPC;
1349 } else {
1350 mode |= nv_connector->dithering_depth;
1351 }
1352
1353 push = evo_wait(mast, 4);
1354 if (push) {
1355 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1356 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
1357 evo_data(push, mode);
1358 } else
1359 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
1360 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
1361 evo_data(push, mode);
1362 } else {
1363 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
1364 evo_data(push, mode);
1365 }
1366
1367 if (update) {
1368 evo_mthd(push, 0x0080, 1);
1369 evo_data(push, 0x00000000);
1370 }
1371 evo_kick(push, mast);
1372 }
1373
1374 return 0;
1375 }
1376
1377 static int
1378 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
1379 {
1380 struct nv50_head *head = nv50_head(&nv_crtc->base);
1381 struct nv50_head_atom *asyh = &head->asy;
1382 struct drm_crtc *crtc = &nv_crtc->base;
1383 struct nouveau_connector *nv_connector;
1384 struct nouveau_conn_atom asyc;
1385
1386 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1387
1388 asyc.state.connector = &nv_connector->base;
1389 asyc.scaler.mode = nv_connector->scaling_mode;
1390 asyc.scaler.full = nv_connector->scaling_full;
1391 asyc.scaler.underscan.mode = nv_connector->underscan;
1392 asyc.scaler.underscan.hborder = nv_connector->underscan_hborder;
1393 asyc.scaler.underscan.vborder = nv_connector->underscan_vborder;
1394 nv50_head_atomic_check(&head->base.base, &asyh->state);
1395 nv50_head_atomic_check_view(&head->arm, asyh, &asyc);
1396 nv50_head_flush_set(head, asyh);
1397
1398 if (update) {
1399 nv50_display_flip_stop(crtc);
1400 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1401 }
1402
1403 return 0;
1404 }
1405
1406 static int
1407 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
1408 {
1409 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1410 u32 *push;
1411
1412 push = evo_wait(mast, 8);
1413 if (!push)
1414 return -ENOMEM;
1415
1416 evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
1417 evo_data(push, usec);
1418 evo_kick(push, mast);
1419 return 0;
1420 }
1421
1422 static int
1423 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
1424 {
1425 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1426 u32 *push, hue, vib;
1427 int adj;
1428
1429 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
1430 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
1431 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
1432
1433 push = evo_wait(mast, 16);
1434 if (push) {
1435 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1436 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
1437 evo_data(push, (hue << 20) | (vib << 8));
1438 } else {
1439 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
1440 evo_data(push, (hue << 20) | (vib << 8));
1441 }
1442
1443 if (update) {
1444 evo_mthd(push, 0x0080, 1);
1445 evo_data(push, 0x00000000);
1446 }
1447 evo_kick(push, mast);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static int
1454 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
1455 int x, int y, bool update)
1456 {
1457 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
1458 struct nv50_head *head = nv50_head(&nv_crtc->base);
1459 struct nv50_head_atom *asyh = &head->asy;
1460 const struct drm_format_info *info;
1461
1462 info = drm_format_info(nvfb->base.pixel_format);
1463 if (!info || !info->depth)
1464 return -EINVAL;
1465
1466 asyh->base.depth = info->depth;
1467 asyh->base.cpp = info->cpp[0];
1468 asyh->base.x = x;
1469 asyh->base.y = y;
1470 asyh->base.w = nvfb->base.width;
1471 asyh->base.h = nvfb->base.height;
1472 nv50_head_atomic_check(&head->base.base, &asyh->state);
1473 nv50_head_flush_set(head, asyh);
1474
1475 if (update) {
1476 struct nv50_mast *core = nv50_mast(nv_crtc->base.dev);
1477 u32 *push = evo_wait(core, 2);
1478 if (push) {
1479 evo_mthd(push, 0x0080, 1);
1480 evo_data(push, 0x00000000);
1481 evo_kick(push, core);
1482 }
1483 }
1484
1485 nv_crtc->fb.handle = nvfb->r_handle;
1486 return 0;
1487 }
1488
1489 static void
1490 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
1491 {
1492 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1493 struct nv50_head *head = nv50_head(&nv_crtc->base);
1494 struct nv50_head_atom *asyh = &head->asy;
1495
1496 asyh->curs.visible = true;
1497 asyh->curs.handle = mast->base.vram.handle;
1498 asyh->curs.offset = nv_crtc->cursor.nvbo->bo.offset;
1499 asyh->curs.layout = 1;
1500 asyh->curs.format = 1;
1501 nv50_head_atomic_check(&head->base.base, &asyh->state);
1502 nv50_head_flush_set(head, asyh);
1503 }
1504
1505 static void
1506 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
1507 {
1508 struct nv50_head *head = nv50_head(&nv_crtc->base);
1509 struct nv50_head_atom *asyh = &head->asy;
1510
1511 asyh->curs.visible = false;
1512 nv50_head_atomic_check(&head->base.base, &asyh->state);
1513 nv50_head_flush_clr(head, asyh, false);
1514 }
1515
1516 static void
1517 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
1518 {
1519 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1520
1521 if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
1522 nv50_crtc_cursor_show(nv_crtc);
1523 else
1524 nv50_crtc_cursor_hide(nv_crtc);
1525
1526 if (update) {
1527 u32 *push = evo_wait(mast, 2);
1528 if (push) {
1529 evo_mthd(push, 0x0080, 1);
1530 evo_data(push, 0x00000000);
1531 evo_kick(push, mast);
1532 }
1533 }
1534 }
1535
1536 static void
1537 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
1538 {
1539 }
1540
1541 static void
1542 nv50_crtc_prepare(struct drm_crtc *crtc)
1543 {
1544 struct nv50_head *head = nv50_head(crtc);
1545 struct nv50_head_atom *asyh = &head->asy;
1546
1547 nv50_display_flip_stop(crtc);
1548
1549 asyh->state.active = false;
1550 nv50_head_atomic_check(&head->base.base, &asyh->state);
1551 nv50_head_flush_clr(head, asyh, false);
1552 }
1553
1554 static void
1555 nv50_crtc_commit(struct drm_crtc *crtc)
1556 {
1557 struct nv50_head *head = nv50_head(crtc);
1558 struct nv50_head_atom *asyh = &head->asy;
1559
1560 asyh->state.active = true;
1561 nv50_head_atomic_check(&head->base.base, &asyh->state);
1562 nv50_head_flush_set(head, asyh);
1563
1564 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1565 }
1566
1567 static bool
1568 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1569 struct drm_display_mode *adjusted_mode)
1570 {
1571 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1572 return true;
1573 }
1574
1575 static int
1576 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1577 {
1578 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1579 struct nv50_head *head = nv50_head(crtc);
1580 int ret;
1581
1582 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1583 if (ret == 0) {
1584 if (head->image)
1585 nouveau_bo_unpin(head->image);
1586 nouveau_bo_ref(nvfb->nvbo, &head->image);
1587 }
1588
1589 return ret;
1590 }
1591
1592 static int
1593 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1594 struct drm_display_mode *mode, int x, int y,
1595 struct drm_framebuffer *old_fb)
1596 {
1597 struct nv50_mast *mast = nv50_mast(crtc->dev);
1598 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1599 struct nouveau_connector *nv_connector;
1600 int ret;
1601 struct nv50_head *head = nv50_head(crtc);
1602 struct nv50_head_atom *asyh = &head->asy;
1603
1604 memcpy(&asyh->state.mode, umode, sizeof(*umode));
1605 memcpy(&asyh->state.adjusted_mode, mode, sizeof(*mode));
1606 asyh->state.active = true;
1607 asyh->state.mode_changed = true;
1608 nv50_head_atomic_check(&head->base.base, &asyh->state);
1609
1610 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1611 if (ret)
1612 return ret;
1613
1614 nv50_head_flush_set(head, asyh);
1615
1616 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1617 nv50_crtc_set_dither(nv_crtc, false);
1618 nv50_crtc_set_scale(nv_crtc, false);
1619
1620 /* G94 only accepts this after setting scale */
1621 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1622 nv50_crtc_set_raster_vblank_dmi(nv_crtc, asyh->mode.v.blankus);
1623
1624 nv50_crtc_set_color_vibrance(nv_crtc, false);
1625 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1626 return 0;
1627 }
1628
1629 static int
1630 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1631 struct drm_framebuffer *old_fb)
1632 {
1633 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1634 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1635 int ret;
1636
1637 if (!crtc->primary->fb) {
1638 NV_DEBUG(drm, "No FB bound\n");
1639 return 0;
1640 }
1641
1642 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1643 if (ret)
1644 return ret;
1645
1646 nv50_display_flip_stop(crtc);
1647 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1648 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1649 return 0;
1650 }
1651
1652 static int
1653 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1654 struct drm_framebuffer *fb, int x, int y,
1655 enum mode_set_atomic state)
1656 {
1657 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1658 nv50_display_flip_stop(crtc);
1659 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1660 return 0;
1661 }
1662
1663 static void
1664 nv50_crtc_lut_load(struct drm_crtc *crtc)
1665 {
1666 struct nv50_disp *disp = nv50_disp(crtc->dev);
1667 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1668 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1669 int i;
1670
1671 for (i = 0; i < 256; i++) {
1672 u16 r = nv_crtc->lut.r[i] >> 2;
1673 u16 g = nv_crtc->lut.g[i] >> 2;
1674 u16 b = nv_crtc->lut.b[i] >> 2;
1675
1676 if (disp->disp->oclass < GF110_DISP) {
1677 writew(r + 0x0000, lut + (i * 0x08) + 0);
1678 writew(g + 0x0000, lut + (i * 0x08) + 2);
1679 writew(b + 0x0000, lut + (i * 0x08) + 4);
1680 } else {
1681 writew(r + 0x6000, lut + (i * 0x20) + 0);
1682 writew(g + 0x6000, lut + (i * 0x20) + 2);
1683 writew(b + 0x6000, lut + (i * 0x20) + 4);
1684 }
1685 }
1686 }
1687
1688 static void
1689 nv50_crtc_disable(struct drm_crtc *crtc)
1690 {
1691 struct nv50_head *head = nv50_head(crtc);
1692 evo_sync(crtc->dev);
1693 if (head->image)
1694 nouveau_bo_unpin(head->image);
1695 nouveau_bo_ref(NULL, &head->image);
1696 }
1697
1698 static int
1699 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1700 uint32_t handle, uint32_t width, uint32_t height)
1701 {
1702 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1703 struct drm_gem_object *gem = NULL;
1704 struct nouveau_bo *nvbo = NULL;
1705 int ret = 0;
1706
1707 if (handle) {
1708 if (width != 64 || height != 64)
1709 return -EINVAL;
1710
1711 gem = drm_gem_object_lookup(file_priv, handle);
1712 if (unlikely(!gem))
1713 return -ENOENT;
1714 nvbo = nouveau_gem_object(gem);
1715
1716 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1717 }
1718
1719 if (ret == 0) {
1720 if (nv_crtc->cursor.nvbo)
1721 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1722 nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
1723 }
1724 drm_gem_object_unreference_unlocked(gem);
1725
1726 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1727 return ret;
1728 }
1729
1730 static int
1731 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1732 {
1733 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1734 struct nv50_curs *curs = nv50_curs(crtc);
1735 struct nv50_chan *chan = nv50_chan(curs);
1736 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1737 nvif_wr32(&chan->user, 0x0080, 0x00000000);
1738
1739 nv_crtc->cursor_saved_x = x;
1740 nv_crtc->cursor_saved_y = y;
1741 return 0;
1742 }
1743
1744 static int
1745 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1746 uint32_t size)
1747 {
1748 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1749 u32 i;
1750
1751 for (i = 0; i < size; i++) {
1752 nv_crtc->lut.r[i] = r[i];
1753 nv_crtc->lut.g[i] = g[i];
1754 nv_crtc->lut.b[i] = b[i];
1755 }
1756
1757 nv50_crtc_lut_load(crtc);
1758
1759 return 0;
1760 }
1761
1762 static void
1763 nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
1764 {
1765 nv50_crtc_cursor_move(&nv_crtc->base, x, y);
1766
1767 nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1768 }
1769
1770 static void
1771 nv50_crtc_destroy(struct drm_crtc *crtc)
1772 {
1773 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1774 struct nv50_disp *disp = nv50_disp(crtc->dev);
1775 struct nv50_head *head = nv50_head(crtc);
1776 struct nv50_fbdma *fbdma;
1777
1778 list_for_each_entry(fbdma, &disp->fbdma, head) {
1779 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1780 }
1781
1782 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1783 nv50_pioc_destroy(&head->oimm.base);
1784 nv50_dmac_destroy(&head->sync.base, disp->disp);
1785 nv50_pioc_destroy(&head->curs.base);
1786
1787 /*XXX: this shouldn't be necessary, but the core doesn't call
1788 * disconnect() during the cleanup paths
1789 */
1790 if (head->image)
1791 nouveau_bo_unpin(head->image);
1792 nouveau_bo_ref(NULL, &head->image);
1793
1794 /*XXX: ditto */
1795 if (nv_crtc->cursor.nvbo)
1796 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1797 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1798
1799 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1800 if (nv_crtc->lut.nvbo)
1801 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1802 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1803
1804 drm_crtc_cleanup(crtc);
1805 kfree(crtc);
1806 }
1807
1808 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1809 .dpms = nv50_crtc_dpms,
1810 .prepare = nv50_crtc_prepare,
1811 .commit = nv50_crtc_commit,
1812 .mode_fixup = nv50_crtc_mode_fixup,
1813 .mode_set = nv50_crtc_mode_set,
1814 .mode_set_base = nv50_crtc_mode_set_base,
1815 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1816 .load_lut = nv50_crtc_lut_load,
1817 .disable = nv50_crtc_disable,
1818 };
1819
1820 static const struct drm_crtc_funcs nv50_crtc_func = {
1821 .cursor_set = nv50_crtc_cursor_set,
1822 .cursor_move = nv50_crtc_cursor_move,
1823 .gamma_set = nv50_crtc_gamma_set,
1824 .set_config = nouveau_crtc_set_config,
1825 .destroy = nv50_crtc_destroy,
1826 .page_flip = nouveau_crtc_page_flip,
1827 };
1828
1829 static int
1830 nv50_crtc_create(struct drm_device *dev, int index)
1831 {
1832 struct nouveau_drm *drm = nouveau_drm(dev);
1833 struct nvif_device *device = &drm->device;
1834 struct nv50_disp *disp = nv50_disp(dev);
1835 struct nv50_head *head;
1836 struct drm_crtc *crtc;
1837 int ret, i;
1838
1839 head = kzalloc(sizeof(*head), GFP_KERNEL);
1840 if (!head)
1841 return -ENOMEM;
1842
1843 head->base.index = index;
1844 head->base.color_vibrance = 50;
1845 head->base.vibrant_hue = 0;
1846 head->base.cursor.set_pos = nv50_crtc_cursor_restore;
1847 for (i = 0; i < 256; i++) {
1848 head->base.lut.r[i] = i << 8;
1849 head->base.lut.g[i] = i << 8;
1850 head->base.lut.b[i] = i << 8;
1851 }
1852
1853 crtc = &head->base.base;
1854 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1855 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1856 drm_mode_crtc_set_gamma_size(crtc, 256);
1857
1858 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1859 0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1860 if (!ret) {
1861 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1862 if (!ret) {
1863 ret = nouveau_bo_map(head->base.lut.nvbo);
1864 if (ret)
1865 nouveau_bo_unpin(head->base.lut.nvbo);
1866 }
1867 if (ret)
1868 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1869 }
1870
1871 if (ret)
1872 goto out;
1873
1874 /* allocate cursor resources */
1875 ret = nv50_curs_create(device, disp->disp, index, &head->curs);
1876 if (ret)
1877 goto out;
1878
1879 /* allocate page flip / sync resources */
1880 ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,
1881 &head->sync);
1882 if (ret)
1883 goto out;
1884
1885 head->sync.addr = EVO_FLIP_SEM0(index);
1886 head->sync.data = 0x00000000;
1887
1888 /* allocate overlay resources */
1889 ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
1890 if (ret)
1891 goto out;
1892
1893 ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
1894 &head->ovly);
1895 if (ret)
1896 goto out;
1897
1898 out:
1899 if (ret)
1900 nv50_crtc_destroy(crtc);
1901 return ret;
1902 }
1903
1904 /******************************************************************************
1905 * Encoder helpers
1906 *****************************************************************************/
1907 static bool
1908 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1909 const struct drm_display_mode *mode,
1910 struct drm_display_mode *adjusted_mode)
1911 {
1912 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1913 struct nouveau_connector *nv_connector;
1914
1915 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1916 if (nv_connector && nv_connector->native_mode) {
1917 nv_connector->scaling_full = false;
1918 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
1919 switch (nv_connector->type) {
1920 case DCB_CONNECTOR_LVDS:
1921 case DCB_CONNECTOR_LVDS_SPWG:
1922 case DCB_CONNECTOR_eDP:
1923 /* force use of scaler for non-edid modes */
1924 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
1925 return true;
1926 nv_connector->scaling_full = true;
1927 break;
1928 default:
1929 return true;
1930 }
1931 }
1932
1933 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1934 }
1935
1936 return true;
1937 }
1938
1939 /******************************************************************************
1940 * DAC
1941 *****************************************************************************/
1942 static void
1943 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1944 {
1945 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1946 struct nv50_disp *disp = nv50_disp(encoder->dev);
1947 struct {
1948 struct nv50_disp_mthd_v1 base;
1949 struct nv50_disp_dac_pwr_v0 pwr;
1950 } args = {
1951 .base.version = 1,
1952 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1953 .base.hasht = nv_encoder->dcb->hasht,
1954 .base.hashm = nv_encoder->dcb->hashm,
1955 .pwr.state = 1,
1956 .pwr.data = 1,
1957 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1958 mode != DRM_MODE_DPMS_OFF),
1959 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1960 mode != DRM_MODE_DPMS_OFF),
1961 };
1962
1963 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1964 }
1965
1966 static void
1967 nv50_dac_commit(struct drm_encoder *encoder)
1968 {
1969 }
1970
1971 static void
1972 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1973 struct drm_display_mode *adjusted_mode)
1974 {
1975 struct nv50_mast *mast = nv50_mast(encoder->dev);
1976 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1977 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1978 u32 *push;
1979
1980 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1981
1982 push = evo_wait(mast, 8);
1983 if (push) {
1984 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1985 u32 syncs = 0x00000000;
1986
1987 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1988 syncs |= 0x00000001;
1989 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1990 syncs |= 0x00000002;
1991
1992 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1993 evo_data(push, 1 << nv_crtc->index);
1994 evo_data(push, syncs);
1995 } else {
1996 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1997 u32 syncs = 0x00000001;
1998
1999 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2000 syncs |= 0x00000008;
2001 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2002 syncs |= 0x00000010;
2003
2004 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2005 magic |= 0x00000001;
2006
2007 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2008 evo_data(push, syncs);
2009 evo_data(push, magic);
2010 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2011 evo_data(push, 1 << nv_crtc->index);
2012 }
2013
2014 evo_kick(push, mast);
2015 }
2016
2017 nv_encoder->crtc = encoder->crtc;
2018 }
2019
2020 static void
2021 nv50_dac_disconnect(struct drm_encoder *encoder)
2022 {
2023 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2024 struct nv50_mast *mast = nv50_mast(encoder->dev);
2025 const int or = nv_encoder->or;
2026 u32 *push;
2027
2028 if (nv_encoder->crtc) {
2029 nv50_crtc_prepare(nv_encoder->crtc);
2030
2031 push = evo_wait(mast, 4);
2032 if (push) {
2033 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2034 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2035 evo_data(push, 0x00000000);
2036 } else {
2037 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2038 evo_data(push, 0x00000000);
2039 }
2040 evo_kick(push, mast);
2041 }
2042 }
2043
2044 nv_encoder->crtc = NULL;
2045 }
2046
2047 static enum drm_connector_status
2048 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2049 {
2050 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2051 struct nv50_disp *disp = nv50_disp(encoder->dev);
2052 struct {
2053 struct nv50_disp_mthd_v1 base;
2054 struct nv50_disp_dac_load_v0 load;
2055 } args = {
2056 .base.version = 1,
2057 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2058 .base.hasht = nv_encoder->dcb->hasht,
2059 .base.hashm = nv_encoder->dcb->hashm,
2060 };
2061 int ret;
2062
2063 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2064 if (args.load.data == 0)
2065 args.load.data = 340;
2066
2067 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2068 if (ret || !args.load.load)
2069 return connector_status_disconnected;
2070
2071 return connector_status_connected;
2072 }
2073
2074 static void
2075 nv50_dac_destroy(struct drm_encoder *encoder)
2076 {
2077 drm_encoder_cleanup(encoder);
2078 kfree(encoder);
2079 }
2080
2081 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
2082 .dpms = nv50_dac_dpms,
2083 .mode_fixup = nv50_encoder_mode_fixup,
2084 .prepare = nv50_dac_disconnect,
2085 .commit = nv50_dac_commit,
2086 .mode_set = nv50_dac_mode_set,
2087 .disable = nv50_dac_disconnect,
2088 .get_crtc = nv50_display_crtc_get,
2089 .detect = nv50_dac_detect
2090 };
2091
2092 static const struct drm_encoder_funcs nv50_dac_func = {
2093 .destroy = nv50_dac_destroy,
2094 };
2095
2096 static int
2097 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2098 {
2099 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2100 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2101 struct nvkm_i2c_bus *bus;
2102 struct nouveau_encoder *nv_encoder;
2103 struct drm_encoder *encoder;
2104 int type = DRM_MODE_ENCODER_DAC;
2105
2106 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2107 if (!nv_encoder)
2108 return -ENOMEM;
2109 nv_encoder->dcb = dcbe;
2110 nv_encoder->or = ffs(dcbe->or) - 1;
2111
2112 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2113 if (bus)
2114 nv_encoder->i2c = &bus->i2c;
2115
2116 encoder = to_drm_encoder(nv_encoder);
2117 encoder->possible_crtcs = dcbe->heads;
2118 encoder->possible_clones = 0;
2119 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2120 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2121 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
2122
2123 drm_mode_connector_attach_encoder(connector, encoder);
2124 return 0;
2125 }
2126
2127 /******************************************************************************
2128 * Audio
2129 *****************************************************************************/
2130 static void
2131 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
2132 {
2133 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2134 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2135 struct nouveau_connector *nv_connector;
2136 struct nv50_disp *disp = nv50_disp(encoder->dev);
2137 struct __packed {
2138 struct {
2139 struct nv50_disp_mthd_v1 mthd;
2140 struct nv50_disp_sor_hda_eld_v0 eld;
2141 } base;
2142 u8 data[sizeof(nv_connector->base.eld)];
2143 } args = {
2144 .base.mthd.version = 1,
2145 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2146 .base.mthd.hasht = nv_encoder->dcb->hasht,
2147 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2148 (0x0100 << nv_crtc->index),
2149 };
2150
2151 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2152 if (!drm_detect_monitor_audio(nv_connector->edid))
2153 return;
2154
2155 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
2156 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2157
2158 nvif_mthd(disp->disp, 0, &args,
2159 sizeof(args.base) + drm_eld_size(args.data));
2160 }
2161
2162 static void
2163 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2164 {
2165 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2166 struct nv50_disp *disp = nv50_disp(encoder->dev);
2167 struct {
2168 struct nv50_disp_mthd_v1 base;
2169 struct nv50_disp_sor_hda_eld_v0 eld;
2170 } args = {
2171 .base.version = 1,
2172 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2173 .base.hasht = nv_encoder->dcb->hasht,
2174 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2175 (0x0100 << nv_crtc->index),
2176 };
2177
2178 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2179 }
2180
2181 /******************************************************************************
2182 * HDMI
2183 *****************************************************************************/
2184 static void
2185 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
2186 {
2187 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2188 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2189 struct nv50_disp *disp = nv50_disp(encoder->dev);
2190 struct {
2191 struct nv50_disp_mthd_v1 base;
2192 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2193 } args = {
2194 .base.version = 1,
2195 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2196 .base.hasht = nv_encoder->dcb->hasht,
2197 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2198 (0x0100 << nv_crtc->index),
2199 .pwr.state = 1,
2200 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2201 };
2202 struct nouveau_connector *nv_connector;
2203 u32 max_ac_packet;
2204
2205 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2206 if (!drm_detect_hdmi_monitor(nv_connector->edid))
2207 return;
2208
2209 max_ac_packet = mode->htotal - mode->hdisplay;
2210 max_ac_packet -= args.pwr.rekey;
2211 max_ac_packet -= 18; /* constant from tegra */
2212 args.pwr.max_ac_packet = max_ac_packet / 32;
2213
2214 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2215 nv50_audio_mode_set(encoder, mode);
2216 }
2217
2218 static void
2219 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2220 {
2221 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2222 struct nv50_disp *disp = nv50_disp(encoder->dev);
2223 struct {
2224 struct nv50_disp_mthd_v1 base;
2225 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2226 } args = {
2227 .base.version = 1,
2228 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2229 .base.hasht = nv_encoder->dcb->hasht,
2230 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
2231 (0x0100 << nv_crtc->index),
2232 };
2233
2234 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2235 }
2236
2237 /******************************************************************************
2238 * MST
2239 *****************************************************************************/
2240 struct nv50_mstm {
2241 struct nouveau_encoder *outp;
2242
2243 struct drm_dp_mst_topology_mgr mgr;
2244 };
2245
2246 static int
2247 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
2248 {
2249 struct nouveau_encoder *outp = mstm->outp;
2250 struct {
2251 struct nv50_disp_mthd_v1 base;
2252 struct nv50_disp_sor_dp_mst_link_v0 mst;
2253 } args = {
2254 .base.version = 1,
2255 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
2256 .base.hasht = outp->dcb->hasht,
2257 .base.hashm = outp->dcb->hashm,
2258 .mst.state = state,
2259 };
2260 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
2261 struct nvif_object *disp = &drm->display->disp;
2262 int ret;
2263
2264 if (dpcd >= 0x12) {
2265 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
2266 if (ret < 0)
2267 return ret;
2268
2269 dpcd &= ~DP_MST_EN;
2270 if (state)
2271 dpcd |= DP_MST_EN;
2272
2273 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
2274 if (ret < 0)
2275 return ret;
2276 }
2277
2278 return nvif_mthd(disp, 0, &args, sizeof(args));
2279 }
2280
2281 int
2282 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
2283 {
2284 int ret, state = 0;
2285
2286 if (!mstm)
2287 return 0;
2288
2289 if (dpcd[0] >= 0x12 && allow) {
2290 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
2291 if (ret < 0)
2292 return ret;
2293
2294 state = dpcd[1] & DP_MST_CAP;
2295 }
2296
2297 ret = nv50_mstm_enable(mstm, dpcd[0], state);
2298 if (ret)
2299 return ret;
2300
2301 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
2302 if (ret)
2303 return nv50_mstm_enable(mstm, dpcd[0], 0);
2304
2305 return mstm->mgr.mst_state;
2306 }
2307
2308 static void
2309 nv50_mstm_del(struct nv50_mstm **pmstm)
2310 {
2311 struct nv50_mstm *mstm = *pmstm;
2312 if (mstm) {
2313 kfree(*pmstm);
2314 *pmstm = NULL;
2315 }
2316 }
2317
2318 static int
2319 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
2320 int conn_base_id, struct nv50_mstm **pmstm)
2321 {
2322 const int max_payloads = hweight8(outp->dcb->heads);
2323 struct drm_device *dev = outp->base.base.dev;
2324 struct nv50_mstm *mstm;
2325 int ret;
2326
2327 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
2328 return -ENOMEM;
2329 mstm->outp = outp;
2330
2331 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev->dev, aux, aux_max,
2332 max_payloads, conn_base_id);
2333 if (ret)
2334 return ret;
2335
2336 return 0;
2337 }
2338
2339 /******************************************************************************
2340 * SOR
2341 *****************************************************************************/
2342 static void
2343 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
2344 {
2345 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2346 struct nv50_disp *disp = nv50_disp(encoder->dev);
2347 struct {
2348 struct nv50_disp_mthd_v1 base;
2349 struct nv50_disp_sor_pwr_v0 pwr;
2350 } args = {
2351 .base.version = 1,
2352 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
2353 .base.hasht = nv_encoder->dcb->hasht,
2354 .base.hashm = nv_encoder->dcb->hashm,
2355 .pwr.state = mode == DRM_MODE_DPMS_ON,
2356 };
2357 struct {
2358 struct nv50_disp_mthd_v1 base;
2359 struct nv50_disp_sor_dp_pwr_v0 pwr;
2360 } link = {
2361 .base.version = 1,
2362 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
2363 .base.hasht = nv_encoder->dcb->hasht,
2364 .base.hashm = nv_encoder->dcb->hashm,
2365 .pwr.state = mode == DRM_MODE_DPMS_ON,
2366 };
2367 struct drm_device *dev = encoder->dev;
2368 struct drm_encoder *partner;
2369
2370 nv_encoder->last_dpms = mode;
2371
2372 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
2373 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
2374
2375 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
2376 continue;
2377
2378 if (nv_partner != nv_encoder &&
2379 nv_partner->dcb->or == nv_encoder->dcb->or) {
2380 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
2381 return;
2382 break;
2383 }
2384 }
2385
2386 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
2387 args.pwr.state = 1;
2388 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2389 nvif_mthd(disp->disp, 0, &link, sizeof(link));
2390 } else {
2391 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2392 }
2393 }
2394
2395 static void
2396 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
2397 {
2398 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
2399 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
2400 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
2401 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2402 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
2403 evo_data(push, (nv_encoder->ctrl = temp));
2404 } else {
2405 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
2406 evo_data(push, (nv_encoder->ctrl = temp));
2407 }
2408 evo_kick(push, mast);
2409 }
2410 }
2411
2412 static void
2413 nv50_sor_disconnect(struct drm_encoder *encoder)
2414 {
2415 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2416 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
2417
2418 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2419 nv_encoder->crtc = NULL;
2420
2421 if (nv_crtc) {
2422 nv50_crtc_prepare(&nv_crtc->base);
2423 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
2424 nv50_audio_disconnect(encoder, nv_crtc);
2425 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
2426 }
2427 }
2428
2429 static void
2430 nv50_sor_commit(struct drm_encoder *encoder)
2431 {
2432 }
2433
2434 static void
2435 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
2436 struct drm_display_mode *mode)
2437 {
2438 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2439 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2440 struct {
2441 struct nv50_disp_mthd_v1 base;
2442 struct nv50_disp_sor_lvds_script_v0 lvds;
2443 } lvds = {
2444 .base.version = 1,
2445 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
2446 .base.hasht = nv_encoder->dcb->hasht,
2447 .base.hashm = nv_encoder->dcb->hashm,
2448 };
2449 struct nv50_disp *disp = nv50_disp(encoder->dev);
2450 struct nv50_mast *mast = nv50_mast(encoder->dev);
2451 struct drm_device *dev = encoder->dev;
2452 struct nouveau_drm *drm = nouveau_drm(dev);
2453 struct nouveau_connector *nv_connector;
2454 struct nvbios *bios = &drm->vbios;
2455 u32 mask, ctrl;
2456 u8 owner = 1 << nv_crtc->index;
2457 u8 proto = 0xf;
2458 u8 depth = 0x0;
2459
2460 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2461 nv_encoder->crtc = encoder->crtc;
2462
2463 switch (nv_encoder->dcb->type) {
2464 case DCB_OUTPUT_TMDS:
2465 if (nv_encoder->dcb->sorconf.link & 1) {
2466 proto = 0x1;
2467 /* Only enable dual-link if:
2468 * - Need to (i.e. rate > 165MHz)
2469 * - DCB says we can
2470 * - Not an HDMI monitor, since there's no dual-link
2471 * on HDMI.
2472 */
2473 if (mode->clock >= 165000 &&
2474 nv_encoder->dcb->duallink_possible &&
2475 !drm_detect_hdmi_monitor(nv_connector->edid))
2476 proto |= 0x4;
2477 } else {
2478 proto = 0x2;
2479 }
2480
2481 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
2482 break;
2483 case DCB_OUTPUT_LVDS:
2484 proto = 0x0;
2485
2486 if (bios->fp_no_ddc) {
2487 if (bios->fp.dual_link)
2488 lvds.lvds.script |= 0x0100;
2489 if (bios->fp.if_is_24bit)
2490 lvds.lvds.script |= 0x0200;
2491 } else {
2492 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
2493 if (((u8 *)nv_connector->edid)[121] == 2)
2494 lvds.lvds.script |= 0x0100;
2495 } else
2496 if (mode->clock >= bios->fp.duallink_transition_clk) {
2497 lvds.lvds.script |= 0x0100;
2498 }
2499
2500 if (lvds.lvds.script & 0x0100) {
2501 if (bios->fp.strapless_is_24bit & 2)
2502 lvds.lvds.script |= 0x0200;
2503 } else {
2504 if (bios->fp.strapless_is_24bit & 1)
2505 lvds.lvds.script |= 0x0200;
2506 }
2507
2508 if (nv_connector->base.display_info.bpc == 8)
2509 lvds.lvds.script |= 0x0200;
2510 }
2511
2512 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
2513 break;
2514 case DCB_OUTPUT_DP:
2515 if (nv_connector->base.display_info.bpc == 6) {
2516 nv_encoder->dp.datarate = mode->clock * 18 / 8;
2517 depth = 0x2;
2518 } else
2519 if (nv_connector->base.display_info.bpc == 8) {
2520 nv_encoder->dp.datarate = mode->clock * 24 / 8;
2521 depth = 0x5;
2522 } else {
2523 nv_encoder->dp.datarate = mode->clock * 30 / 8;
2524 depth = 0x6;
2525 }
2526
2527 if (nv_encoder->dcb->sorconf.link & 1)
2528 proto = 0x8;
2529 else
2530 proto = 0x9;
2531 nv50_audio_mode_set(encoder, mode);
2532 break;
2533 default:
2534 BUG_ON(1);
2535 break;
2536 }
2537
2538 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
2539
2540 if (nv50_vers(mast) >= GF110_DISP) {
2541 u32 *push = evo_wait(mast, 3);
2542 if (push) {
2543 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2544 u32 syncs = 0x00000001;
2545
2546 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2547 syncs |= 0x00000008;
2548 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2549 syncs |= 0x00000010;
2550
2551 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2552 magic |= 0x00000001;
2553
2554 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2555 evo_data(push, syncs | (depth << 6));
2556 evo_data(push, magic);
2557 evo_kick(push, mast);
2558 }
2559
2560 ctrl = proto << 8;
2561 mask = 0x00000f00;
2562 } else {
2563 ctrl = (depth << 16) | (proto << 8);
2564 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2565 ctrl |= 0x00001000;
2566 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2567 ctrl |= 0x00002000;
2568 mask = 0x000f3f00;
2569 }
2570
2571 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2572 }
2573
2574 static void
2575 nv50_sor_destroy(struct drm_encoder *encoder)
2576 {
2577 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2578 nv50_mstm_del(&nv_encoder->dp.mstm);
2579 drm_encoder_cleanup(encoder);
2580 kfree(encoder);
2581 }
2582
2583 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2584 .dpms = nv50_sor_dpms,
2585 .mode_fixup = nv50_encoder_mode_fixup,
2586 .prepare = nv50_sor_disconnect,
2587 .commit = nv50_sor_commit,
2588 .mode_set = nv50_sor_mode_set,
2589 .disable = nv50_sor_disconnect,
2590 .get_crtc = nv50_display_crtc_get,
2591 };
2592
2593 static const struct drm_encoder_funcs nv50_sor_func = {
2594 .destroy = nv50_sor_destroy,
2595 };
2596
2597 static int
2598 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2599 {
2600 struct nouveau_connector *nv_connector = nouveau_connector(connector);
2601 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2602 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2603 struct nouveau_encoder *nv_encoder;
2604 struct drm_encoder *encoder;
2605 int type, ret;
2606
2607 switch (dcbe->type) {
2608 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2609 case DCB_OUTPUT_TMDS:
2610 case DCB_OUTPUT_DP:
2611 default:
2612 type = DRM_MODE_ENCODER_TMDS;
2613 break;
2614 }
2615
2616 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2617 if (!nv_encoder)
2618 return -ENOMEM;
2619 nv_encoder->dcb = dcbe;
2620 nv_encoder->or = ffs(dcbe->or) - 1;
2621 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2622
2623 encoder = to_drm_encoder(nv_encoder);
2624 encoder->possible_crtcs = dcbe->heads;
2625 encoder->possible_clones = 0;
2626 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
2627 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
2628 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2629
2630 drm_mode_connector_attach_encoder(connector, encoder);
2631
2632 if (dcbe->type == DCB_OUTPUT_DP) {
2633 struct nvkm_i2c_aux *aux =
2634 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
2635 if (aux) {
2636 nv_encoder->i2c = &aux->i2c;
2637 nv_encoder->aux = aux;
2638 }
2639
2640 /*TODO: Use DP Info Table to check for support. */
2641 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
2642 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
2643 nv_connector->base.base.id,
2644 &nv_encoder->dp.mstm);
2645 if (ret)
2646 return ret;
2647 }
2648 } else {
2649 struct nvkm_i2c_bus *bus =
2650 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2651 if (bus)
2652 nv_encoder->i2c = &bus->i2c;
2653 }
2654
2655 return 0;
2656 }
2657
2658 /******************************************************************************
2659 * PIOR
2660 *****************************************************************************/
2661
2662 static void
2663 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2664 {
2665 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2666 struct nv50_disp *disp = nv50_disp(encoder->dev);
2667 struct {
2668 struct nv50_disp_mthd_v1 base;
2669 struct nv50_disp_pior_pwr_v0 pwr;
2670 } args = {
2671 .base.version = 1,
2672 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2673 .base.hasht = nv_encoder->dcb->hasht,
2674 .base.hashm = nv_encoder->dcb->hashm,
2675 .pwr.state = mode == DRM_MODE_DPMS_ON,
2676 .pwr.type = nv_encoder->dcb->type,
2677 };
2678
2679 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2680 }
2681
2682 static bool
2683 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2684 const struct drm_display_mode *mode,
2685 struct drm_display_mode *adjusted_mode)
2686 {
2687 if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2688 return false;
2689 adjusted_mode->clock *= 2;
2690 return true;
2691 }
2692
2693 static void
2694 nv50_pior_commit(struct drm_encoder *encoder)
2695 {
2696 }
2697
2698 static void
2699 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2700 struct drm_display_mode *adjusted_mode)
2701 {
2702 struct nv50_mast *mast = nv50_mast(encoder->dev);
2703 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2704 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2705 struct nouveau_connector *nv_connector;
2706 u8 owner = 1 << nv_crtc->index;
2707 u8 proto, depth;
2708 u32 *push;
2709
2710 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2711 switch (nv_connector->base.display_info.bpc) {
2712 case 10: depth = 0x6; break;
2713 case 8: depth = 0x5; break;
2714 case 6: depth = 0x2; break;
2715 default: depth = 0x0; break;
2716 }
2717
2718 switch (nv_encoder->dcb->type) {
2719 case DCB_OUTPUT_TMDS:
2720 case DCB_OUTPUT_DP:
2721 proto = 0x0;
2722 break;
2723 default:
2724 BUG_ON(1);
2725 break;
2726 }
2727
2728 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2729
2730 push = evo_wait(mast, 8);
2731 if (push) {
2732 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2733 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2734 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2735 ctrl |= 0x00001000;
2736 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2737 ctrl |= 0x00002000;
2738 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2739 evo_data(push, ctrl);
2740 }
2741
2742 evo_kick(push, mast);
2743 }
2744
2745 nv_encoder->crtc = encoder->crtc;
2746 }
2747
2748 static void
2749 nv50_pior_disconnect(struct drm_encoder *encoder)
2750 {
2751 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2752 struct nv50_mast *mast = nv50_mast(encoder->dev);
2753 const int or = nv_encoder->or;
2754 u32 *push;
2755
2756 if (nv_encoder->crtc) {
2757 nv50_crtc_prepare(nv_encoder->crtc);
2758
2759 push = evo_wait(mast, 4);
2760 if (push) {
2761 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2762 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2763 evo_data(push, 0x00000000);
2764 }
2765 evo_kick(push, mast);
2766 }
2767 }
2768
2769 nv_encoder->crtc = NULL;
2770 }
2771
2772 static void
2773 nv50_pior_destroy(struct drm_encoder *encoder)
2774 {
2775 drm_encoder_cleanup(encoder);
2776 kfree(encoder);
2777 }
2778
2779 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2780 .dpms = nv50_pior_dpms,
2781 .mode_fixup = nv50_pior_mode_fixup,
2782 .prepare = nv50_pior_disconnect,
2783 .commit = nv50_pior_commit,
2784 .mode_set = nv50_pior_mode_set,
2785 .disable = nv50_pior_disconnect,
2786 .get_crtc = nv50_display_crtc_get,
2787 };
2788
2789 static const struct drm_encoder_funcs nv50_pior_func = {
2790 .destroy = nv50_pior_destroy,
2791 };
2792
2793 static int
2794 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2795 {
2796 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2797 struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2798 struct nvkm_i2c_bus *bus = NULL;
2799 struct nvkm_i2c_aux *aux = NULL;
2800 struct i2c_adapter *ddc;
2801 struct nouveau_encoder *nv_encoder;
2802 struct drm_encoder *encoder;
2803 int type;
2804
2805 switch (dcbe->type) {
2806 case DCB_OUTPUT_TMDS:
2807 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2808 ddc = bus ? &bus->i2c : NULL;
2809 type = DRM_MODE_ENCODER_TMDS;
2810 break;
2811 case DCB_OUTPUT_DP:
2812 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2813 ddc = aux ? &aux->i2c : NULL;
2814 type = DRM_MODE_ENCODER_TMDS;
2815 break;
2816 default:
2817 return -ENODEV;
2818 }
2819
2820 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2821 if (!nv_encoder)
2822 return -ENOMEM;
2823 nv_encoder->dcb = dcbe;
2824 nv_encoder->or = ffs(dcbe->or) - 1;
2825 nv_encoder->i2c = ddc;
2826 nv_encoder->aux = aux;
2827
2828 encoder = to_drm_encoder(nv_encoder);
2829 encoder->possible_crtcs = dcbe->heads;
2830 encoder->possible_clones = 0;
2831 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2832 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2833 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2834
2835 drm_mode_connector_attach_encoder(connector, encoder);
2836 return 0;
2837 }
2838
2839 /******************************************************************************
2840 * Framebuffer
2841 *****************************************************************************/
2842
2843 static void
2844 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2845 {
2846 int i;
2847 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2848 nvif_object_fini(&fbdma->base[i]);
2849 nvif_object_fini(&fbdma->core);
2850 list_del(&fbdma->head);
2851 kfree(fbdma);
2852 }
2853
2854 static int
2855 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2856 {
2857 struct nouveau_drm *drm = nouveau_drm(dev);
2858 struct nv50_disp *disp = nv50_disp(dev);
2859 struct nv50_mast *mast = nv50_mast(dev);
2860 struct __attribute__ ((packed)) {
2861 struct nv_dma_v0 base;
2862 union {
2863 struct nv50_dma_v0 nv50;
2864 struct gf100_dma_v0 gf100;
2865 struct gf119_dma_v0 gf119;
2866 };
2867 } args = {};
2868 struct nv50_fbdma *fbdma;
2869 struct drm_crtc *crtc;
2870 u32 size = sizeof(args.base);
2871 int ret;
2872
2873 list_for_each_entry(fbdma, &disp->fbdma, head) {
2874 if (fbdma->core.handle == name)
2875 return 0;
2876 }
2877
2878 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2879 if (!fbdma)
2880 return -ENOMEM;
2881 list_add(&fbdma->head, &disp->fbdma);
2882
2883 args.base.target = NV_DMA_V0_TARGET_VRAM;
2884 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2885 args.base.start = offset;
2886 args.base.limit = offset + length - 1;
2887
2888 if (drm->device.info.chipset < 0x80) {
2889 args.nv50.part = NV50_DMA_V0_PART_256;
2890 size += sizeof(args.nv50);
2891 } else
2892 if (drm->device.info.chipset < 0xc0) {
2893 args.nv50.part = NV50_DMA_V0_PART_256;
2894 args.nv50.kind = kind;
2895 size += sizeof(args.nv50);
2896 } else
2897 if (drm->device.info.chipset < 0xd0) {
2898 args.gf100.kind = kind;
2899 size += sizeof(args.gf100);
2900 } else {
2901 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2902 args.gf119.kind = kind;
2903 size += sizeof(args.gf119);
2904 }
2905
2906 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2907 struct nv50_head *head = nv50_head(crtc);
2908 int ret = nvif_object_init(&head->sync.base.base.user, name,
2909 NV_DMA_IN_MEMORY, &args, size,
2910 &fbdma->base[head->base.index]);
2911 if (ret) {
2912 nv50_fbdma_fini(fbdma);
2913 return ret;
2914 }
2915 }
2916
2917 ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY,
2918 &args, size, &fbdma->core);
2919 if (ret) {
2920 nv50_fbdma_fini(fbdma);
2921 return ret;
2922 }
2923
2924 return 0;
2925 }
2926
2927 static void
2928 nv50_fb_dtor(struct drm_framebuffer *fb)
2929 {
2930 }
2931
2932 static int
2933 nv50_fb_ctor(struct drm_framebuffer *fb)
2934 {
2935 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2936 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2937 struct nouveau_bo *nvbo = nv_fb->nvbo;
2938 struct nv50_disp *disp = nv50_disp(fb->dev);
2939 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2940 u8 tile = nvbo->tile_mode;
2941
2942 if (drm->device.info.chipset >= 0xc0)
2943 tile >>= 4; /* yep.. */
2944
2945 switch (fb->depth) {
2946 case 8: nv_fb->r_format = 0x1e00; break;
2947 case 15: nv_fb->r_format = 0xe900; break;
2948 case 16: nv_fb->r_format = 0xe800; break;
2949 case 24:
2950 case 32: nv_fb->r_format = 0xcf00; break;
2951 case 30: nv_fb->r_format = 0xd100; break;
2952 default:
2953 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2954 return -EINVAL;
2955 }
2956
2957 if (disp->disp->oclass < G82_DISP) {
2958 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2959 (fb->pitches[0] | 0x00100000);
2960 nv_fb->r_format |= kind << 16;
2961 } else
2962 if (disp->disp->oclass < GF110_DISP) {
2963 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2964 (fb->pitches[0] | 0x00100000);
2965 } else {
2966 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2967 (fb->pitches[0] | 0x01000000);
2968 }
2969 nv_fb->r_handle = 0xffff0000 | kind;
2970
2971 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2972 drm->device.info.ram_user, kind);
2973 }
2974
2975 /******************************************************************************
2976 * Init
2977 *****************************************************************************/
2978
2979 void
2980 nv50_display_fini(struct drm_device *dev)
2981 {
2982 }
2983
2984 int
2985 nv50_display_init(struct drm_device *dev)
2986 {
2987 struct nv50_disp *disp = nv50_disp(dev);
2988 struct drm_crtc *crtc;
2989 u32 *push;
2990
2991 push = evo_wait(nv50_mast(dev), 32);
2992 if (!push)
2993 return -EBUSY;
2994
2995 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2996 struct nv50_sync *sync = nv50_sync(crtc);
2997
2998 nv50_crtc_lut_load(crtc);
2999 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
3000 }
3001
3002 evo_mthd(push, 0x0088, 1);
3003 evo_data(push, nv50_mast(dev)->base.sync.handle);
3004 evo_kick(push, nv50_mast(dev));
3005 return 0;
3006 }
3007
3008 void
3009 nv50_display_destroy(struct drm_device *dev)
3010 {
3011 struct nv50_disp *disp = nv50_disp(dev);
3012 struct nv50_fbdma *fbdma, *fbtmp;
3013
3014 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
3015 nv50_fbdma_fini(fbdma);
3016 }
3017
3018 nv50_dmac_destroy(&disp->mast.base, disp->disp);
3019
3020 nouveau_bo_unmap(disp->sync);
3021 if (disp->sync)
3022 nouveau_bo_unpin(disp->sync);
3023 nouveau_bo_ref(NULL, &disp->sync);
3024
3025 nouveau_display(dev)->priv = NULL;
3026 kfree(disp);
3027 }
3028
3029 int
3030 nv50_display_create(struct drm_device *dev)
3031 {
3032 struct nvif_device *device = &nouveau_drm(dev)->device;
3033 struct nouveau_drm *drm = nouveau_drm(dev);
3034 struct dcb_table *dcb = &drm->vbios.dcb;
3035 struct drm_connector *connector, *tmp;
3036 struct nv50_disp *disp;
3037 struct dcb_output *dcbe;
3038 int crtcs, ret, i;
3039
3040 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
3041 if (!disp)
3042 return -ENOMEM;
3043 INIT_LIST_HEAD(&disp->fbdma);
3044
3045 nouveau_display(dev)->priv = disp;
3046 nouveau_display(dev)->dtor = nv50_display_destroy;
3047 nouveau_display(dev)->init = nv50_display_init;
3048 nouveau_display(dev)->fini = nv50_display_fini;
3049 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
3050 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
3051 disp->disp = &nouveau_display(dev)->disp;
3052
3053 /* small shared memory area we use for notifiers and semaphores */
3054 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
3055 0, 0x0000, NULL, NULL, &disp->sync);
3056 if (!ret) {
3057 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
3058 if (!ret) {
3059 ret = nouveau_bo_map(disp->sync);
3060 if (ret)
3061 nouveau_bo_unpin(disp->sync);
3062 }
3063 if (ret)
3064 nouveau_bo_ref(NULL, &disp->sync);
3065 }
3066
3067 if (ret)
3068 goto out;
3069
3070 /* allocate master evo channel */
3071 ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
3072 &disp->mast);
3073 if (ret)
3074 goto out;
3075
3076 /* create crtc objects to represent the hw heads */
3077 if (disp->disp->oclass >= GF110_DISP)
3078 crtcs = nvif_rd32(&device->object, 0x022448);
3079 else
3080 crtcs = 2;
3081
3082 for (i = 0; i < crtcs; i++) {
3083 ret = nv50_crtc_create(dev, i);
3084 if (ret)
3085 goto out;
3086 }
3087
3088 /* create encoder/connector objects based on VBIOS DCB table */
3089 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
3090 connector = nouveau_connector_create(dev, dcbe->connector);
3091 if (IS_ERR(connector))
3092 continue;
3093
3094 if (dcbe->location == DCB_LOC_ON_CHIP) {
3095 switch (dcbe->type) {
3096 case DCB_OUTPUT_TMDS:
3097 case DCB_OUTPUT_LVDS:
3098 case DCB_OUTPUT_DP:
3099 ret = nv50_sor_create(connector, dcbe);
3100 break;
3101 case DCB_OUTPUT_ANALOG:
3102 ret = nv50_dac_create(connector, dcbe);
3103 break;
3104 default:
3105 ret = -ENODEV;
3106 break;
3107 }
3108 } else {
3109 ret = nv50_pior_create(connector, dcbe);
3110 }
3111
3112 if (ret) {
3113 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
3114 dcbe->location, dcbe->type,
3115 ffs(dcbe->or) - 1, ret);
3116 ret = 0;
3117 }
3118 }
3119
3120 /* cull any connectors we created that don't have an encoder */
3121 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
3122 if (connector->encoder_ids[0])
3123 continue;
3124
3125 NV_WARN(drm, "%s has no encoders, removing\n",
3126 connector->name);
3127 connector->funcs->destroy(connector);
3128 }
3129
3130 out:
3131 if (ret)
3132 nv50_display_destroy(dev);
3133 return ret;
3134 }
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