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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/gpu/drm/nouveau/nv84_fifo.c
2 * Copyright (C) 2012 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "nouveau_drv.h"
29 #include "nouveau_fifo.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_vm.h"
33 struct nv84_fifo_priv
{
34 struct nouveau_fifo_priv base
;
35 struct nouveau_gpuobj
*playlist
[2];
39 struct nv84_fifo_chan
{
40 struct nouveau_fifo_chan base
;
41 struct nouveau_gpuobj
*ramfc
;
42 struct nouveau_gpuobj
*cache
;
46 nv84_fifo_context_new(struct nouveau_channel
*chan
, int engine
)
48 struct nv84_fifo_priv
*priv
= nv_engine(chan
->dev
, engine
);
49 struct nv84_fifo_chan
*fctx
;
50 struct drm_device
*dev
= chan
->dev
;
51 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
52 u64 ib_offset
= chan
->pushbuf_base
+ chan
->dma
.ib_base
* 4;
57 fctx
= chan
->engctx
[engine
] = kzalloc(sizeof(*fctx
), GFP_KERNEL
);
60 atomic_inc(&chan
->vm
->engref
[engine
]);
62 chan
->user
= ioremap(pci_resource_start(dev
->pdev
, 0) +
63 NV50_USER(chan
->id
), PAGE_SIZE
);
69 ret
= nouveau_gpuobj_new(dev
, chan
, 256, 256, NVOBJ_FLAG_ZERO_ALLOC
|
70 NVOBJ_FLAG_ZERO_FREE
, &fctx
->ramfc
);
74 instance
= fctx
->ramfc
->vinst
>> 8;
76 ret
= nouveau_gpuobj_new(dev
, chan
, 4096, 1024, 0, &fctx
->cache
);
80 nv_wo32(fctx
->ramfc
, 0x3c, 0x403f6078);
81 nv_wo32(fctx
->ramfc
, 0x40, 0x00000000);
82 nv_wo32(fctx
->ramfc
, 0x44, 0x01003fff);
83 nv_wo32(fctx
->ramfc
, 0x48, chan
->pushbuf
->cinst
>> 4);
84 nv_wo32(fctx
->ramfc
, 0x50, lower_32_bits(ib_offset
));
85 nv_wo32(fctx
->ramfc
, 0x54, upper_32_bits(ib_offset
) |
86 drm_order(chan
->dma
.ib_max
+ 1) << 16);
87 nv_wo32(fctx
->ramfc
, 0x60, 0x7fffffff);
88 nv_wo32(fctx
->ramfc
, 0x78, 0x00000000);
89 nv_wo32(fctx
->ramfc
, 0x7c, 0x30000001);
90 nv_wo32(fctx
->ramfc
, 0x80, ((chan
->ramht
->bits
- 9) << 27) |
91 (4 << 24) /* SEARCH_FULL */ |
92 (chan
->ramht
->gpuobj
->cinst
>> 4));
93 nv_wo32(fctx
->ramfc
, 0x88, fctx
->cache
->vinst
>> 10);
94 nv_wo32(fctx
->ramfc
, 0x98, chan
->ramin
->vinst
>> 12);
96 nv_wo32(chan
->ramin
, 0x00, chan
->id
);
97 nv_wo32(chan
->ramin
, 0x04, fctx
->ramfc
->vinst
>> 8);
99 dev_priv
->engine
.instmem
.flush(dev
);
101 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
102 nv_wr32(dev
, 0x002600 + (chan
->id
* 4), 0x80000000 | instance
);
103 nv50_fifo_playlist_update(dev
);
104 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
108 priv
->base
.base
.context_del(chan
, engine
);
113 nv84_fifo_context_del(struct nouveau_channel
*chan
, int engine
)
115 struct nv84_fifo_chan
*fctx
= chan
->engctx
[engine
];
116 struct drm_device
*dev
= chan
->dev
;
117 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
121 /* remove channel from playlist, will context switch if active */
122 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
123 nv_mask(dev
, 0x002600 + (chan
->id
* 4), 0x80000000, 0x00000000);
124 nv50_fifo_playlist_update(dev
);
126 save
= nv_mask(dev
, 0x002520, 0x0000003f, 0x15);
128 /* tell any engines on this channel to unload their contexts */
129 nv_wr32(dev
, 0x0032fc, chan
->ramin
->vinst
>> 12);
130 if (!nv_wait_ne(dev
, 0x0032fc, 0xffffffff, 0xffffffff))
131 NV_INFO(dev
, "PFIFO: channel %d unload timeout\n", chan
->id
);
133 nv_wr32(dev
, 0x002520, save
);
135 nv_wr32(dev
, 0x002600 + (chan
->id
* 4), 0x00000000);
136 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
144 nouveau_gpuobj_ref(NULL
, &fctx
->ramfc
);
145 nouveau_gpuobj_ref(NULL
, &fctx
->cache
);
147 atomic_dec(&chan
->vm
->engref
[engine
]);
148 chan
->engctx
[engine
] = NULL
;
153 nv84_fifo_init(struct drm_device
*dev
, int engine
)
155 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
156 struct nv84_fifo_chan
*fctx
;
160 nv_mask(dev
, 0x000200, 0x00000100, 0x00000000);
161 nv_mask(dev
, 0x000200, 0x00000100, 0x00000100);
162 nv_wr32(dev
, 0x00250c, 0x6f3cfc34);
163 nv_wr32(dev
, 0x002044, 0x01003fff);
165 nv_wr32(dev
, 0x002100, 0xffffffff);
166 nv_wr32(dev
, 0x002140, 0xffffffff);
168 for (i
= 0; i
< 128; i
++) {
169 struct nouveau_channel
*chan
= dev_priv
->channels
.ptr
[i
];
170 if (chan
&& (fctx
= chan
->engctx
[engine
]))
171 instance
= 0x80000000 | fctx
->ramfc
->vinst
>> 8;
173 instance
= 0x00000000;
174 nv_wr32(dev
, 0x002600 + (i
* 4), instance
);
177 nv50_fifo_playlist_update(dev
);
179 nv_wr32(dev
, 0x003200, 1);
180 nv_wr32(dev
, 0x003250, 1);
181 nv_wr32(dev
, 0x002500, 1);
186 nv84_fifo_fini(struct drm_device
*dev
, int engine
, bool suspend
)
188 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
189 struct nv84_fifo_priv
*priv
= nv_engine(dev
, engine
);
193 /* set playlist length to zero, fifo will unload context */
194 nv_wr32(dev
, 0x0032ec, 0);
196 save
= nv_mask(dev
, 0x002520, 0x0000003f, 0x15);
198 /* tell all connected engines to unload their contexts */
199 for (i
= 0; i
< priv
->base
.channels
; i
++) {
200 struct nouveau_channel
*chan
= dev_priv
->channels
.ptr
[i
];
202 nv_wr32(dev
, 0x0032fc, chan
->ramin
->vinst
>> 12);
203 if (!nv_wait_ne(dev
, 0x0032fc, 0xffffffff, 0xffffffff)) {
204 NV_INFO(dev
, "PFIFO: channel %d unload timeout\n", i
);
209 nv_wr32(dev
, 0x002520, save
);
210 nv_wr32(dev
, 0x002140, 0);
215 nv84_fifo_create(struct drm_device
*dev
)
217 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
218 struct nv84_fifo_priv
*priv
;
221 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
225 priv
->base
.base
.destroy
= nv50_fifo_destroy
;
226 priv
->base
.base
.init
= nv84_fifo_init
;
227 priv
->base
.base
.fini
= nv84_fifo_fini
;
228 priv
->base
.base
.context_new
= nv84_fifo_context_new
;
229 priv
->base
.base
.context_del
= nv84_fifo_context_del
;
230 priv
->base
.base
.tlb_flush
= nv50_fifo_tlb_flush
;
231 priv
->base
.channels
= 127;
232 dev_priv
->eng
[NVOBJ_ENGINE_FIFO
] = &priv
->base
.base
;
234 ret
= nouveau_gpuobj_new(dev
, NULL
, priv
->base
.channels
* 4, 0x1000,
235 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->playlist
[0]);
239 ret
= nouveau_gpuobj_new(dev
, NULL
, priv
->base
.channels
* 4, 0x1000,
240 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->playlist
[1]);
244 nouveau_irq_register(dev
, 8, nv04_fifo_isr
);
247 priv
->base
.base
.destroy(dev
, NVOBJ_ENGINE_FIFO
);