1 #ifndef __NVIF_CLASS_H__
2 #define __NVIF_CLASS_H__
4 /*******************************************************************************
6 ******************************************************************************/
8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
9 #define NV_DEVICE 0x00000080
11 #define NV_DMA_FROM_MEMORY 0x00000002
12 #define NV_DMA_TO_MEMORY 0x00000003
13 #define NV_DMA_IN_MEMORY 0x0000003d
15 #define NV03_CHANNEL_DMA 0x0000006b
16 #define NV10_CHANNEL_DMA 0x0000006e
17 #define NV17_CHANNEL_DMA 0x0000176e
18 #define NV40_CHANNEL_DMA 0x0000406e
19 #define NV50_CHANNEL_DMA 0x0000506e
20 #define G82_CHANNEL_DMA 0x0000826e
22 #define NV50_CHANNEL_GPFIFO 0x0000506f
23 #define G82_CHANNEL_GPFIFO 0x0000826f
24 #define FERMI_CHANNEL_GPFIFO 0x0000906f
25 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
28 /*******************************************************************************
30 ******************************************************************************/
32 #define NV_CLIENT_DEVLIST 0x00
34 struct nv_client_devlist_v0
{
42 /*******************************************************************************
44 ******************************************************************************/
49 __u64 device
; /* device identifier, ~0 for client default */
50 #define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
51 #define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
52 #define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
53 #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
54 #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
55 #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
56 #define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL
57 #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
58 #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
59 #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
60 #define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL
61 #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
62 #define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
63 #define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL
64 #define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL
65 #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
66 #define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
67 __u64 disable
; /* disable particular subsystems */
68 __u64 debug0
; /* as above, but *internal* ids, and *NOT* ABI */
71 #define NV_DEVICE_V0_INFO 0x00
73 struct nv_device_info_v0
{
75 #define NV_DEVICE_INFO_V0_IGP 0x00
76 #define NV_DEVICE_INFO_V0_PCI 0x01
77 #define NV_DEVICE_INFO_V0_AGP 0x02
78 #define NV_DEVICE_INFO_V0_PCIE 0x03
79 #define NV_DEVICE_INFO_V0_SOC 0x04
81 __u16 chipset
; /* from NV_PMC_BOOT_0 */
82 __u8 revision
; /* from NV_PMC_BOOT_0 */
83 #define NV_DEVICE_INFO_V0_TNT 0x01
84 #define NV_DEVICE_INFO_V0_CELSIUS 0x02
85 #define NV_DEVICE_INFO_V0_KELVIN 0x03
86 #define NV_DEVICE_INFO_V0_RANKINE 0x04
87 #define NV_DEVICE_INFO_V0_CURIE 0x05
88 #define NV_DEVICE_INFO_V0_TESLA 0x06
89 #define NV_DEVICE_INFO_V0_FERMI 0x07
90 #define NV_DEVICE_INFO_V0_KEPLER 0x08
91 #define NV_DEVICE_INFO_V0_MAXWELL 0x09
99 /*******************************************************************************
101 ******************************************************************************/
105 #define NV_DMA_V0_TARGET_VM 0x00
106 #define NV_DMA_V0_TARGET_VRAM 0x01
107 #define NV_DMA_V0_TARGET_PCI 0x02
108 #define NV_DMA_V0_TARGET_PCI_US 0x03
109 #define NV_DMA_V0_TARGET_AGP 0x04
111 #define NV_DMA_V0_ACCESS_VM 0x00
112 #define NV_DMA_V0_ACCESS_RD 0x01
113 #define NV_DMA_V0_ACCESS_WR 0x02
114 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
119 /* ... chipset-specific class data */
124 #define NV50_DMA_V0_PRIV_VM 0x00
125 #define NV50_DMA_V0_PRIV_US 0x01
126 #define NV50_DMA_V0_PRIV__S 0x02
128 #define NV50_DMA_V0_PART_VM 0x00
129 #define NV50_DMA_V0_PART_256 0x01
130 #define NV50_DMA_V0_PART_1KB 0x02
132 #define NV50_DMA_V0_COMP_NONE 0x00
133 #define NV50_DMA_V0_COMP_1 0x01
134 #define NV50_DMA_V0_COMP_2 0x02
135 #define NV50_DMA_V0_COMP_VM 0x03
137 #define NV50_DMA_V0_KIND_PITCH 0x00
138 #define NV50_DMA_V0_KIND_VM 0x7f
143 struct gf100_dma_v0
{
145 #define GF100_DMA_V0_PRIV_VM 0x00
146 #define GF100_DMA_V0_PRIV_US 0x01
147 #define GF100_DMA_V0_PRIV__S 0x02
149 #define GF100_DMA_V0_KIND_PITCH 0x00
150 #define GF100_DMA_V0_KIND_VM 0xff
155 struct gf110_dma_v0
{
157 #define GF110_DMA_V0_PAGE_LP 0x00
158 #define GF110_DMA_V0_PAGE_SP 0x01
160 #define GF110_DMA_V0_KIND_PITCH 0x00
161 #define GF110_DMA_V0_KIND_VM 0xff
167 /*******************************************************************************
169 ******************************************************************************/
171 struct nvif_perfctr_v0
{
179 #define NVIF_PERFCTR_V0_QUERY 0x00
180 #define NVIF_PERFCTR_V0_SAMPLE 0x01
181 #define NVIF_PERFCTR_V0_READ 0x02
183 struct nvif_perfctr_query_v0
{
190 struct nvif_perfctr_sample
{
193 struct nvif_perfctr_read_v0
{
201 /*******************************************************************************
203 ******************************************************************************/
205 #define NVIF_CONTROL_PSTATE_INFO 0x00
206 #define NVIF_CONTROL_PSTATE_ATTR 0x01
207 #define NVIF_CONTROL_PSTATE_USER 0x02
209 struct nvif_control_pstate_info_v0
{
211 __u8 count
; /* out: number of power states */
212 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
213 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
214 __s8 ustate_ac
; /* out: target pstate index */
215 __s8 ustate_dc
; /* out: target pstate index */
216 __s8 pwrsrc
; /* out: current power source */
217 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
218 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
219 __s8 pstate
; /* out: current pstate index */
223 struct nvif_control_pstate_attr_v0
{
225 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
226 __s8 state
; /* in: index of pstate to query
227 * out: pstate identifier
229 __u8 index
; /* in: index of attribute to query
230 * out: index of next attribute, or 0 if no more
239 struct nvif_control_pstate_user_v0
{
241 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
242 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
243 __s8 ustate
; /* in: pstate identifier */
244 __s8 pwrsrc
; /* in: target power source */
249 /*******************************************************************************
251 ******************************************************************************/
253 struct nv03_channel_dma_v0
{
261 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
263 /*******************************************************************************
265 ******************************************************************************/
267 struct nv50_channel_gpfifo_v0
{
276 struct kepler_channel_gpfifo_a_v0
{
278 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
279 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
280 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
281 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08
282 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
283 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
284 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
293 /*******************************************************************************
295 ******************************************************************************/
298 /*******************************************************************************
300 ******************************************************************************/
302 #define NV50_DISP_MTHD 0x00
304 struct nv50_disp_mthd_v0
{
311 struct nv50_disp_mthd_v1
{
313 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10
314 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
315 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20
316 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
317 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
318 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
319 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
320 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
327 struct nv50_disp_dac_pwr_v0
{
336 struct nv50_disp_dac_load_v0
{