]>
git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 nv40_identify(struct nvkm_device
*device
)
29 switch (device
->chipset
) {
31 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
32 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
33 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
34 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
35 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
36 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
37 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
38 device
->oclass
[NVDEV_SUBDEV_FB
] = nv40_fb_oclass
;
39 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
40 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv04_mmu_oclass
;
41 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
42 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
43 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
44 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
45 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
46 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
47 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
48 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
51 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
52 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
53 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
54 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
55 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
56 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
57 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
58 device
->oclass
[NVDEV_SUBDEV_FB
] = nv41_fb_oclass
;
59 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
60 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv41_mmu_oclass
;
61 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
62 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
63 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
64 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
65 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
66 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
67 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
68 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
71 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
72 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
73 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
74 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
75 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
76 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
77 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
78 device
->oclass
[NVDEV_SUBDEV_FB
] = nv41_fb_oclass
;
79 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
80 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv41_mmu_oclass
;
81 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
82 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
83 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
84 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
85 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
86 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
87 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
88 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
91 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
92 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
93 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
94 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
95 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
96 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
97 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
98 device
->oclass
[NVDEV_SUBDEV_FB
] = nv41_fb_oclass
;
99 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
100 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv41_mmu_oclass
;
101 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
102 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
103 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
104 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
105 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
106 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv40_mpeg_oclass
;
107 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
108 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
111 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
112 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
113 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
114 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
115 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
116 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
117 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
118 device
->oclass
[NVDEV_SUBDEV_FB
] = nv40_fb_oclass
;
119 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
120 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv04_mmu_oclass
;
121 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
122 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
123 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
124 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
125 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
126 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
127 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
128 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
131 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
132 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
133 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
134 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
135 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
136 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
137 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
138 device
->oclass
[NVDEV_SUBDEV_FB
] = nv47_fb_oclass
;
139 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
140 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv41_mmu_oclass
;
141 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
142 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
143 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
144 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
145 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
146 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
147 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
148 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
151 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
152 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
153 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
154 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
155 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
156 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
157 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
158 device
->oclass
[NVDEV_SUBDEV_FB
] = nv49_fb_oclass
;
159 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
160 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv41_mmu_oclass
;
161 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
162 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
163 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
164 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
165 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
166 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
167 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
168 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
171 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
172 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
173 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
174 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
175 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
176 device
->oclass
[NVDEV_SUBDEV_MC
] = nv40_mc_oclass
;
177 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
178 device
->oclass
[NVDEV_SUBDEV_FB
] = nv49_fb_oclass
;
179 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
180 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv41_mmu_oclass
;
181 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
182 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
183 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
184 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
185 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
186 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
187 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
188 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
191 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
192 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
193 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
194 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
195 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
196 device
->oclass
[NVDEV_SUBDEV_MC
] = nv44_mc_oclass
;
197 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
198 device
->oclass
[NVDEV_SUBDEV_FB
] = nv44_fb_oclass
;
199 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
200 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
201 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
202 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
203 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
204 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
205 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
206 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
207 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
208 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
211 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
212 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
213 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
214 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
215 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
216 device
->oclass
[NVDEV_SUBDEV_MC
] = nv4c_mc_oclass
;
217 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
218 device
->oclass
[NVDEV_SUBDEV_FB
] = nv46_fb_oclass
;
219 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
220 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
221 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
222 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
223 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
224 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
225 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
226 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
227 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
228 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
231 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
232 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
233 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
234 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
235 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
236 device
->oclass
[NVDEV_SUBDEV_MC
] = nv44_mc_oclass
;
237 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
238 device
->oclass
[NVDEV_SUBDEV_FB
] = nv44_fb_oclass
;
239 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
240 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
241 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
242 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
243 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
244 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
245 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
246 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
247 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
248 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
251 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
252 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
253 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
254 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
255 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
256 device
->oclass
[NVDEV_SUBDEV_MC
] = nv4c_mc_oclass
;
257 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
258 device
->oclass
[NVDEV_SUBDEV_FB
] = nv46_fb_oclass
;
259 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
260 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
261 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
262 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
263 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
264 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
265 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
266 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
267 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
268 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
271 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
272 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv4e_i2c_oclass
;
273 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
274 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
275 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
276 device
->oclass
[NVDEV_SUBDEV_MC
] = nv4c_mc_oclass
;
277 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
278 device
->oclass
[NVDEV_SUBDEV_FB
] = nv4e_fb_oclass
;
279 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
280 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
281 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
282 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
283 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
284 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
285 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
286 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
287 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
288 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
291 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
292 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
293 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
294 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
295 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
296 device
->oclass
[NVDEV_SUBDEV_MC
] = nv4c_mc_oclass
;
297 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
298 device
->oclass
[NVDEV_SUBDEV_FB
] = nv46_fb_oclass
;
299 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
300 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
301 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
302 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
303 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
304 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
305 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
306 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
307 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
308 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
311 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
312 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
313 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
314 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
315 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
316 device
->oclass
[NVDEV_SUBDEV_MC
] = nv4c_mc_oclass
;
317 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
318 device
->oclass
[NVDEV_SUBDEV_FB
] = nv46_fb_oclass
;
319 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
320 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
321 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
322 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
323 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
324 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
325 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
326 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
327 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
328 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;
331 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
332 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
333 device
->oclass
[NVDEV_SUBDEV_CLK
] = &nv40_clk_oclass
;
334 device
->oclass
[NVDEV_SUBDEV_THERM
] = &nv40_therm_oclass
;
335 device
->oclass
[NVDEV_SUBDEV_DEVINIT
] = nv1a_devinit_oclass
;
336 device
->oclass
[NVDEV_SUBDEV_MC
] = nv4c_mc_oclass
;
337 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
338 device
->oclass
[NVDEV_SUBDEV_FB
] = nv46_fb_oclass
;
339 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv40_instmem_oclass
;
340 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv44_mmu_oclass
;
341 device
->oclass
[NVDEV_SUBDEV_VOLT
] = &nv40_volt_oclass
;
342 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
343 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv40_fifo_oclass
;
344 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
345 device
->oclass
[NVDEV_ENGINE_GR
] = &nv40_gr_oclass
;
346 device
->oclass
[NVDEV_ENGINE_MPEG
] = &nv44_mpeg_oclass
;
347 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
348 device
->oclass
[NVDEV_ENGINE_PM
] = nv40_pm_oclass
;