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drm/nouveau/bus: convert to new-style nvkm_subdev
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nv50.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25
26 int
27 nv50_identify(struct nvkm_device *device)
28 {
29 switch (device->chipset) {
30 case 0x50:
31 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
32 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
33 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
34 device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
35 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
36 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
37 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
38 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
39 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
40 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
41 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
42 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
43 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
44 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
45 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
46 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
47 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
48 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
49 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
50 device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
51 break;
52 case 0x84:
53 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
54 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
55 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
56 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
57 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
58 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
59 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
60 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
62 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
63 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
64 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
65 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
66 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
67 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
68 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
69 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
70 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
71 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
72 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
73 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
74 device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
75 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
76 break;
77 case 0x86:
78 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
79 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
80 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
81 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
82 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
83 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
84 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
85 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
87 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
88 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
89 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
92 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
93 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
94 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
95 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
96 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
97 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
98 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
99 device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
100 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
101 break;
102 case 0x92:
103 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
104 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
105 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
106 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
107 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
108 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
109 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
110 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
111 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
112 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
113 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
114 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
117 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
119 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
120 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
121 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
122 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
123 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
124 device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
125 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
126 break;
127 case 0x94:
128 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
129 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
130 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
131 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
132 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
133 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
134 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
135 device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
136 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
137 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
138 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
139 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
140 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
141 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
142 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
143 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
144 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
145 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
146 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
147 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
148 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
149 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
150 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
151 break;
152 case 0x96:
153 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
154 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
155 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
156 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
157 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
158 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
159 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
160 device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
161 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
162 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
163 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
164 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
165 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
166 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
167 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
168 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
169 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
170 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
171 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
172 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
173 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
174 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
175 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
176 break;
177 case 0x98:
178 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
179 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
180 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
181 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
182 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
183 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
184 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
185 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
186 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
187 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
188 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
189 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
190 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
191 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
192 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
193 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
194 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
195 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
196 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
197 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
198 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
199 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
200 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
201 break;
202 case 0xa0:
203 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
204 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
205 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
206 device->oclass[NVDEV_SUBDEV_CLK ] = g84_clk_oclass;
207 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
208 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
209 device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass;
210 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
211 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
212 device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
213 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
214 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
215 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
216 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
217 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
218 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
219 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
220 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
221 device->oclass[NVDEV_ENGINE_VP ] = &g84_vp_oclass;
222 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
223 device->oclass[NVDEV_ENGINE_BSP ] = &g84_bsp_oclass;
224 device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
225 device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
226 break;
227 case 0xaa:
228 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
229 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
230 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
231 device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
232 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
233 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
234 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
235 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
236 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
237 device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
238 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
239 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
240 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
241 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
242 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
243 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
244 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
245 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
246 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
247 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
248 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
249 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
250 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
251 break;
252 case 0xac:
253 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
254 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
255 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
256 device->oclass[NVDEV_SUBDEV_CLK ] = mcp77_clk_oclass;
257 device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass;
258 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
259 device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass;
260 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
261 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
262 device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
263 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
264 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
265 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
266 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
267 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
268 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
269 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
270 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
271 device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
272 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
273 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
274 device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
275 device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
276 break;
277 case 0xa3:
278 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
279 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
280 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
281 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
282 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
283 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
284 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
285 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
286 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
287 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
288 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
289 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
290 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
291 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
292 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
293 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
294 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
295 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
296 device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
297 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
298 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
299 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
300 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
301 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
302 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
303 break;
304 case 0xa5:
305 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
306 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
307 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
308 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
309 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
310 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
311 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
312 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
313 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
314 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
315 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
316 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
317 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
318 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
319 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
320 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
321 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
322 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
323 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
324 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
325 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
326 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
327 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
328 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
329 break;
330 case 0xa8:
331 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
332 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
333 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
334 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
335 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
336 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
337 device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass;
338 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
340 device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
341 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
342 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
343 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
344 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
345 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
346 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
347 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
348 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
349 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
350 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
351 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
352 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
353 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
354 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
355 break;
356 case 0xaf:
357 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
358 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
359 device->oclass[NVDEV_SUBDEV_FUSE ] = &nv50_fuse_oclass;
360 device->oclass[NVDEV_SUBDEV_CLK ] = &gt215_clk_oclass;
361 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
362 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
363 device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass;
364 device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
365 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
366 device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
367 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
368 device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
369 device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
370 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
371 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
372 device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
373 device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
374 device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
375 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
376 device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
377 device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
378 device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
379 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
380 device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
381 break;
382 default:
383 return -EINVAL;
384 }
385
386 return 0;
387 }
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