drivers/gpu/drm/nouveau/nvkm/engine/disp/coreg94.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <nvif/class.h>
  28
  29 static const struct nv50_disp_mthd_list
  30 g94_disp_core_mthd_sor = {
  31         .mthd = 0x0040,
  32         .addr = 0x000008,
  33         .data = {
  34                 { 0x0600, 0x610794 },
  35                 {}
  36         }
  37 };
  38
  39 const struct nv50_disp_chan_mthd
  40 g94_disp_core_chan_mthd = {
  41         .name = "Core",
  42         .addr = 0x000000,
  43         .prev = 0x000004,
  44         .data = {
  45                 { "Global", 1, &nv50_disp_core_mthd_base },
  46                 {    "DAC", 3, &g84_disp_core_mthd_dac },
  47                 {    "SOR", 4, &g94_disp_core_mthd_sor },
  48                 {   "PIOR", 3, &nv50_disp_core_mthd_pior },
  49                 {   "HEAD", 2, &g84_disp_core_mthd_head },
  50                 {}
  51         }
  52 };
  53
  54 const struct nv50_disp_dmac_oclass
  55 g94_disp_core_oclass = {
  56         .base.oclass = GT206_DISP_CORE_CHANNEL_DMA,
  57         .base.minver = 0,
  58         .base.maxver = 0,
  59         .ctor = nv50_disp_core_new,
  60         .func = &nv50_disp_core_func,
  61         .mthd = &g94_disp_core_chan_mthd,
  62         .chid = 0,
  63 };