drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25
  26 #include <subdev/timer.h>
  27
  28 const struct nv50_disp_mthd_list
  29 gf119_disp_core_mthd_base = {
  30         .mthd = 0x0000,
  31         .addr = 0x000000,
  32         .data = {
  33                 { 0x0080, 0x660080 },
  34                 { 0x0084, 0x660084 },
  35                 { 0x0088, 0x660088 },
  36                 { 0x008c, 0x000000 },
  37                 {}
  38         }
  39 };
  40
  41 const struct nv50_disp_mthd_list
  42 gf119_disp_core_mthd_dac = {
  43         .mthd = 0x0020,
  44         .addr = 0x000020,
  45         .data = {
  46                 { 0x0180, 0x660180 },
  47                 { 0x0184, 0x660184 },
  48                 { 0x0188, 0x660188 },
  49                 { 0x0190, 0x660190 },
  50                 {}
  51         }
  52 };
  53
  54 const struct nv50_disp_mthd_list
  55 gf119_disp_core_mthd_sor = {
  56         .mthd = 0x0020,
  57         .addr = 0x000020,
  58         .data = {
  59                 { 0x0200, 0x660200 },
  60                 { 0x0204, 0x660204 },
  61                 { 0x0208, 0x660208 },
  62                 { 0x0210, 0x660210 },
  63                 {}
  64         }
  65 };
  66
  67 const struct nv50_disp_mthd_list
  68 gf119_disp_core_mthd_pior = {
  69         .mthd = 0x0020,
  70         .addr = 0x000020,
  71         .data = {
  72                 { 0x0300, 0x660300 },
  73                 { 0x0304, 0x660304 },
  74                 { 0x0308, 0x660308 },
  75                 { 0x0310, 0x660310 },
  76                 {}
  77         }
  78 };
  79
  80 static const struct nv50_disp_mthd_list
  81 gf119_disp_core_mthd_head = {
  82         .mthd = 0x0300,
  83         .addr = 0x000300,
  84         .data = {
  85                 { 0x0400, 0x660400 },
  86                 { 0x0404, 0x660404 },
  87                 { 0x0408, 0x660408 },
  88                 { 0x040c, 0x66040c },
  89                 { 0x0410, 0x660410 },
  90                 { 0x0414, 0x660414 },
  91                 { 0x0418, 0x660418 },
  92                 { 0x041c, 0x66041c },
  93                 { 0x0420, 0x660420 },
  94                 { 0x0424, 0x660424 },
  95                 { 0x0428, 0x660428 },
  96                 { 0x042c, 0x66042c },
  97                 { 0x0430, 0x660430 },
  98                 { 0x0434, 0x660434 },
  99                 { 0x0438, 0x660438 },
 100                 { 0x0440, 0x660440 },
 101                 { 0x0444, 0x660444 },
 102                 { 0x0448, 0x660448 },
 103                 { 0x044c, 0x66044c },
 104                 { 0x0450, 0x660450 },
 105                 { 0x0454, 0x660454 },
 106                 { 0x0458, 0x660458 },
 107                 { 0x045c, 0x66045c },
 108                 { 0x0460, 0x660460 },
 109                 { 0x0468, 0x660468 },
 110                 { 0x046c, 0x66046c },
 111                 { 0x0470, 0x660470 },
 112                 { 0x0474, 0x660474 },
 113                 { 0x0480, 0x660480 },
 114                 { 0x0484, 0x660484 },
 115                 { 0x048c, 0x66048c },
 116                 { 0x0490, 0x660490 },
 117                 { 0x0494, 0x660494 },
 118                 { 0x0498, 0x660498 },
 119                 { 0x04b0, 0x6604b0 },
 120                 { 0x04b8, 0x6604b8 },
 121                 { 0x04bc, 0x6604bc },
 122                 { 0x04c0, 0x6604c0 },
 123                 { 0x04c4, 0x6604c4 },
 124                 { 0x04c8, 0x6604c8 },
 125                 { 0x04d0, 0x6604d0 },
 126                 { 0x04d4, 0x6604d4 },
 127                 { 0x04e0, 0x6604e0 },
 128                 { 0x04e4, 0x6604e4 },
 129                 { 0x04e8, 0x6604e8 },
 130                 { 0x04ec, 0x6604ec },
 131                 { 0x04f0, 0x6604f0 },
 132                 { 0x04f4, 0x6604f4 },
 133                 { 0x04f8, 0x6604f8 },
 134                 { 0x04fc, 0x6604fc },
 135                 { 0x0500, 0x660500 },
 136                 { 0x0504, 0x660504 },
 137                 { 0x0508, 0x660508 },
 138                 { 0x050c, 0x66050c },
 139                 { 0x0510, 0x660510 },
 140                 { 0x0514, 0x660514 },
 141                 { 0x0518, 0x660518 },
 142                 { 0x051c, 0x66051c },
 143                 { 0x052c, 0x66052c },
 144                 { 0x0530, 0x660530 },
 145                 { 0x054c, 0x66054c },
 146                 { 0x0550, 0x660550 },
 147                 { 0x0554, 0x660554 },
 148                 { 0x0558, 0x660558 },
 149                 { 0x055c, 0x66055c },
 150                 {}
 151         }
 152 };
 153
 154 const struct nv50_disp_mthd_chan
 155 gf119_disp_core_mthd_chan = {
 156         .name = "Core",
 157         .addr = 0x000000,
 158         .data = {
 159                 { "Global", 1, &gf119_disp_core_mthd_base },
 160                 {    "DAC", 3, &gf119_disp_core_mthd_dac  },
 161                 {    "SOR", 8, &gf119_disp_core_mthd_sor  },
 162                 {   "PIOR", 4, &gf119_disp_core_mthd_pior },
 163                 {   "HEAD", 4, &gf119_disp_core_mthd_head },
 164                 {}
 165         }
 166 };
 167
 168 static int
 169 gf119_disp_core_fini(struct nvkm_object *object, bool suspend)
 170 {
 171         struct nv50_disp *disp = (void *)object->engine;
 172         struct nv50_disp_dmac *mast = (void *)object;
 173         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 174         struct nvkm_device *device = subdev->device;
 175
 176         /* deactivate channel */
 177         nvkm_mask(device, 0x610490, 0x00000010, 0x00000000);
 178         nvkm_mask(device, 0x610490, 0x00000003, 0x00000000);
 179         if (nvkm_msec(device, 2000,
 180                 if (!(nvkm_rd32(device, 0x610490) & 0x001e0000))
 181                         break;
 182         ) < 0) {
 183                 nvkm_error(subdev, "core fini: %08x\n",
 184                            nvkm_rd32(device, 0x610490));
 185                 if (suspend)
 186                         return -EBUSY;
 187         }
 188
 189         /* disable error reporting and completion notification */
 190         nvkm_mask(device, 0x610090, 0x00000001, 0x00000000);
 191         nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000000);
 192
 193         return nv50_disp_chan_fini(&mast->base, suspend);
 194 }
 195
 196 static int
 197 gf119_disp_core_init(struct nvkm_object *object)
 198 {
 199         struct nv50_disp *disp = (void *)object->engine;
 200         struct nv50_disp_dmac *mast = (void *)object;
 201         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 202         struct nvkm_device *device = subdev->device;
 203         int ret;
 204
 205         ret = nv50_disp_chan_init(&mast->base);
 206         if (ret)
 207                 return ret;
 208
 209         /* enable error reporting */
 210         nvkm_mask(device, 0x6100a0, 0x00000001, 0x00000001);
 211
 212         /* initialise channel for dma command submission */
 213         nvkm_wr32(device, 0x610494, mast->push);
 214         nvkm_wr32(device, 0x610498, 0x00010000);
 215         nvkm_wr32(device, 0x61049c, 0x00000001);
 216         nvkm_mask(device, 0x610490, 0x00000010, 0x00000010);
 217         nvkm_wr32(device, 0x640000, 0x00000000);
 218         nvkm_wr32(device, 0x610490, 0x01000013);
 219
 220         /* wait for it to go inactive */
 221         if (nvkm_msec(device, 2000,
 222                 if (!(nvkm_rd32(device, 0x610490) & 0x80000000))
 223                         break;
 224         ) < 0) {
 225                 nvkm_error(subdev, "core init: %08x\n",
 226                            nvkm_rd32(device, 0x610490));
 227                 return -EBUSY;
 228         }
 229
 230         return 0;
 231 }
 232
 233 struct nv50_disp_chan_impl
 234 gf119_disp_core_ofuncs = {
 235         .base.ctor = nv50_disp_core_ctor,
 236         .base.dtor = nv50_disp_dmac_dtor,
 237         .base.init = gf119_disp_core_init,
 238         .base.fini = gf119_disp_core_fini,
 239         .base.ntfy = nv50_disp_chan_ntfy,
 240         .base.map  = nv50_disp_chan_map,
 241         .base.rd32 = nv50_disp_chan_rd32,
 242         .base.wr32 = nv50_disp_chan_wr32,
 243         .chid = 0,
 244         .attach = gf119_disp_dmac_object_attach,
 245         .detach = gf119_disp_dmac_object_detach,
 246 };