drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "dmacnv50.h"
  25
  26 #include <core/client.h>
  27 #include <subdev/timer.h>
  28
  29 #include <nvif/class.h>
  30 #include <nvif/unpack.h>
  31
  32 const struct nv50_disp_mthd_list
  33 nv50_disp_core_mthd_base = {
  34         .mthd = 0x0000,
  35         .addr = 0x000000,
  36         .data = {
  37                 { 0x0080, 0x000000 },
  38                 { 0x0084, 0x610bb8 },
  39                 { 0x0088, 0x610b9c },
  40                 { 0x008c, 0x000000 },
  41                 {}
  42         }
  43 };
  44
  45 static const struct nv50_disp_mthd_list
  46 nv50_disp_core_mthd_dac = {
  47         .mthd = 0x0080,
  48         .addr = 0x000008,
  49         .data = {
  50                 { 0x0400, 0x610b58 },
  51                 { 0x0404, 0x610bdc },
  52                 { 0x0420, 0x610828 },
  53                 {}
  54         }
  55 };
  56
  57 const struct nv50_disp_mthd_list
  58 nv50_disp_core_mthd_sor = {
  59         .mthd = 0x0040,
  60         .addr = 0x000008,
  61         .data = {
  62                 { 0x0600, 0x610b70 },
  63                 {}
  64         }
  65 };
  66
  67 const struct nv50_disp_mthd_list
  68 nv50_disp_core_mthd_pior = {
  69         .mthd = 0x0040,
  70         .addr = 0x000008,
  71         .data = {
  72                 { 0x0700, 0x610b80 },
  73                 {}
  74         }
  75 };
  76
  77 static const struct nv50_disp_mthd_list
  78 nv50_disp_core_mthd_head = {
  79         .mthd = 0x0400,
  80         .addr = 0x000540,
  81         .data = {
  82                 { 0x0800, 0x610ad8 },
  83                 { 0x0804, 0x610ad0 },
  84                 { 0x0808, 0x610a48 },
  85                 { 0x080c, 0x610a78 },
  86                 { 0x0810, 0x610ac0 },
  87                 { 0x0814, 0x610af8 },
  88                 { 0x0818, 0x610b00 },
  89                 { 0x081c, 0x610ae8 },
  90                 { 0x0820, 0x610af0 },
  91                 { 0x0824, 0x610b08 },
  92                 { 0x0828, 0x610b10 },
  93                 { 0x082c, 0x610a68 },
  94                 { 0x0830, 0x610a60 },
  95                 { 0x0834, 0x000000 },
  96                 { 0x0838, 0x610a40 },
  97                 { 0x0840, 0x610a24 },
  98                 { 0x0844, 0x610a2c },
  99                 { 0x0848, 0x610aa8 },
 100                 { 0x084c, 0x610ab0 },
 101                 { 0x0860, 0x610a84 },
 102                 { 0x0864, 0x610a90 },
 103                 { 0x0868, 0x610b18 },
 104                 { 0x086c, 0x610b20 },
 105                 { 0x0870, 0x610ac8 },
 106                 { 0x0874, 0x610a38 },
 107                 { 0x0880, 0x610a58 },
 108                 { 0x0884, 0x610a9c },
 109                 { 0x08a0, 0x610a70 },
 110                 { 0x08a4, 0x610a50 },
 111                 { 0x08a8, 0x610ae0 },
 112                 { 0x08c0, 0x610b28 },
 113                 { 0x08c4, 0x610b30 },
 114                 { 0x08c8, 0x610b40 },
 115                 { 0x08d4, 0x610b38 },
 116                 { 0x08d8, 0x610b48 },
 117                 { 0x08dc, 0x610b50 },
 118                 { 0x0900, 0x610a18 },
 119                 { 0x0904, 0x610ab8 },
 120                 {}
 121         }
 122 };
 123
 124 const struct nv50_disp_mthd_chan
 125 nv50_disp_core_mthd_chan = {
 126         .name = "Core",
 127         .addr = 0x000000,
 128         .data = {
 129                 { "Global", 1, &nv50_disp_core_mthd_base },
 130                 {    "DAC", 3, &nv50_disp_core_mthd_dac  },
 131                 {    "SOR", 2, &nv50_disp_core_mthd_sor  },
 132                 {   "PIOR", 3, &nv50_disp_core_mthd_pior },
 133                 {   "HEAD", 2, &nv50_disp_core_mthd_head },
 134                 {}
 135         }
 136 };
 137
 138 static int
 139 nv50_disp_core_fini(struct nvkm_object *object, bool suspend)
 140 {
 141         struct nv50_disp *disp = (void *)object->engine;
 142         struct nv50_disp_dmac *mast = (void *)object;
 143         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 144         struct nvkm_device *device = subdev->device;
 145
 146         /* deactivate channel */
 147         nvkm_mask(device, 0x610200, 0x00000010, 0x00000000);
 148         nvkm_mask(device, 0x610200, 0x00000003, 0x00000000);
 149         if (nvkm_msec(device, 2000,
 150                 if (!(nvkm_rd32(device, 0x610200) & 0x001e0000))
 151                         break;
 152         ) < 0) {
 153                 nvkm_error(subdev, "core fini: %08x\n",
 154                            nvkm_rd32(device, 0x610200));
 155                 if (suspend)
 156                         return -EBUSY;
 157         }
 158
 159         /* disable error reporting and completion notifications */
 160         nvkm_mask(device, 0x610028, 0x00010001, 0x00000000);
 161
 162         return nv50_disp_chan_fini(&mast->base, suspend);
 163 }
 164
 165 static int
 166 nv50_disp_core_init(struct nvkm_object *object)
 167 {
 168         struct nv50_disp *disp = (void *)object->engine;
 169         struct nv50_disp_dmac *mast = (void *)object;
 170         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 171         struct nvkm_device *device = subdev->device;
 172         int ret;
 173
 174         ret = nv50_disp_chan_init(&mast->base);
 175         if (ret)
 176                 return ret;
 177
 178         /* enable error reporting */
 179         nvkm_mask(device, 0x610028, 0x00010000, 0x00010000);
 180
 181         /* attempt to unstick channel from some unknown state */
 182         if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000)
 183                 nvkm_mask(device, 0x610200, 0x00800000, 0x00800000);
 184         if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000)
 185                 nvkm_mask(device, 0x610200, 0x00600000, 0x00600000);
 186
 187         /* initialise channel for dma command submission */
 188         nvkm_wr32(device, 0x610204, mast->push);
 189         nvkm_wr32(device, 0x610208, 0x00010000);
 190         nvkm_wr32(device, 0x61020c, 0x00000000);
 191         nvkm_mask(device, 0x610200, 0x00000010, 0x00000010);
 192         nvkm_wr32(device, 0x640000, 0x00000000);
 193         nvkm_wr32(device, 0x610200, 0x01000013);
 194
 195         /* wait for it to go inactive */
 196         if (nvkm_msec(device, 2000,
 197                 if (!(nvkm_rd32(device, 0x610200) & 0x80000000))
 198                         break;
 199         ) < 0) {
 200                 nvkm_error(subdev, "core init: %08x\n",
 201                            nvkm_rd32(device, 0x610200));
 202                 return -EBUSY;
 203         }
 204
 205         return 0;
 206 }
 207
 208 int
 209 nv50_disp_core_ctor(struct nvkm_object *parent,
 210                     struct nvkm_object *engine,
 211                     struct nvkm_oclass *oclass, void *data, u32 size,
 212                     struct nvkm_object **pobject)
 213 {
 214         union {
 215                 struct nv50_disp_core_channel_dma_v0 v0;
 216         } *args = data;
 217         struct nv50_disp_dmac *mast;
 218         int ret;
 219
 220         nvif_ioctl(parent, "create disp core channel dma size %d\n", size);
 221         if (nvif_unpack(args->v0, 0, 0, false)) {
 222                 nvif_ioctl(parent, "create disp core channel dma vers %d "
 223                                    "pushbuf %016llx\n",
 224                            args->v0.version, args->v0.pushbuf);
 225         } else
 226                 return ret;
 227
 228         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
 229                                      0, sizeof(*mast), (void **)&mast);
 230         *pobject = nv_object(mast);
 231         if (ret)
 232                 return ret;
 233
 234         return 0;
 235 }
 236
 237 struct nv50_disp_chan_impl
 238 nv50_disp_core_ofuncs = {
 239         .base.ctor = nv50_disp_core_ctor,
 240         .base.dtor = nv50_disp_dmac_dtor,
 241         .base.init = nv50_disp_core_init,
 242         .base.fini = nv50_disp_core_fini,
 243         .base.map  = nv50_disp_chan_map,
 244         .base.ntfy = nv50_disp_chan_ntfy,
 245         .base.rd32 = nv50_disp_chan_rd32,
 246         .base.wr32 = nv50_disp_chan_wr32,
 247         .chid = 0,
 248         .attach = nv50_disp_dmac_object_attach,
 249         .detach = nv50_disp_dmac_object_detach,
 250 };