drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h

   1 #ifndef __NVKM_DISP_DPORT_H__
   2 #define __NVKM_DISP_DPORT_H__
   3 #include <core/os.h>
   4
   5 /* DPCD Receiver Capabilities */
   6 #define DPCD_RC00_DPCD_REV                                              0x00000
   7 #define DPCD_RC01_MAX_LINK_RATE                                         0x00001
   8 #define DPCD_RC02                                                       0x00002
   9 #define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
  10 #define DPCD_RC02_TPS3_SUPPORTED                                           0x40
  11 #define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
  12 #define DPCD_RC03                                                       0x00003
  13 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
  14 #define DPCD_RC0E_AUX_RD_INTERVAL                                       0x0000e
  15
  16 /* DPCD Link Configuration */
  17 #define DPCD_LC00_LINK_BW_SET                                           0x00100
  18 #define DPCD_LC01                                                       0x00101
  19 #define DPCD_LC01_ENHANCED_FRAME_EN                                        0x80
  20 #define DPCD_LC01_LANE_COUNT_SET                                           0x1f
  21 #define DPCD_LC02                                                       0x00102
  22 #define DPCD_LC02_TRAINING_PATTERN_SET                                     0x03
  23 #define DPCD_LC03(l)                                            ((l) +  0x00103)
  24 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED                                 0x20
  25 #define DPCD_LC03_PRE_EMPHASIS_SET                                         0x18
  26 #define DPCD_LC03_MAX_SWING_REACHED                                        0x04
  27 #define DPCD_LC03_VOLTAGE_SWING_SET                                        0x03
  28 #define DPCD_LC0F                                                       0x0010f
  29 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED                           0x40
  30 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET                                   0x30
  31 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED                           0x04
  32 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET                                   0x03
  33 #define DPCD_LC10                                                       0x00110
  34 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED                           0x40
  35 #define DPCD_LC10_LANE3_POST_CURSOR2_SET                                   0x30
  36 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED                           0x04
  37 #define DPCD_LC10_LANE2_POST_CURSOR2_SET                                   0x03
  38
  39 /* DPCD Link/Sink Status */
  40 #define DPCD_LS02                                                       0x00202
  41 #define DPCD_LS02_LANE1_SYMBOL_LOCKED                                      0x40
  42 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE                                    0x20
  43 #define DPCD_LS02_LANE1_CR_DONE                                            0x10
  44 #define DPCD_LS02_LANE0_SYMBOL_LOCKED                                      0x04
  45 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE                                    0x02
  46 #define DPCD_LS02_LANE0_CR_DONE                                            0x01
  47 #define DPCD_LS03                                                       0x00203
  48 #define DPCD_LS03_LANE3_SYMBOL_LOCKED                                      0x40
  49 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE                                    0x20
  50 #define DPCD_LS03_LANE3_CR_DONE                                            0x10
  51 #define DPCD_LS03_LANE2_SYMBOL_LOCKED                                      0x04
  52 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE                                    0x02
  53 #define DPCD_LS03_LANE2_CR_DONE                                            0x01
  54 #define DPCD_LS04                                                       0x00204
  55 #define DPCD_LS04_LINK_STATUS_UPDATED                                      0x80
  56 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED                           0x40
  57 #define DPCD_LS04_INTERLANE_ALIGN_DONE                                     0x01
  58 #define DPCD_LS06                                                       0x00206
  59 #define DPCD_LS06_LANE1_PRE_EMPHASIS                                       0xc0
  60 #define DPCD_LS06_LANE1_VOLTAGE_SWING                                      0x30
  61 #define DPCD_LS06_LANE0_PRE_EMPHASIS                                       0x0c
  62 #define DPCD_LS06_LANE0_VOLTAGE_SWING                                      0x03
  63 #define DPCD_LS07                                                       0x00207
  64 #define DPCD_LS07_LANE3_PRE_EMPHASIS                                       0xc0
  65 #define DPCD_LS07_LANE3_VOLTAGE_SWING                                      0x30
  66 #define DPCD_LS07_LANE2_PRE_EMPHASIS                                       0x0c
  67 #define DPCD_LS07_LANE2_VOLTAGE_SWING                                      0x03
  68 #define DPCD_LS0C                                                       0x0020c
  69 #define DPCD_LS0C_LANE3_POST_CURSOR2                                       0xc0
  70 #define DPCD_LS0C_LANE2_POST_CURSOR2                                       0x30
  71 #define DPCD_LS0C_LANE1_POST_CURSOR2                                       0x0c
  72 #define DPCD_LS0C_LANE0_POST_CURSOR2                                       0x03
  73
  74 /* DPCD Sink Control */
  75 #define DPCD_SC00                                                       0x00600
  76 #define DPCD_SC00_SET_POWER                                                0x03
  77 #define DPCD_SC00_SET_POWER_D0                                             0x01
  78 #define DPCD_SC00_SET_POWER_D3                                             0x03
  79
  80 void nvkm_dp_train(struct work_struct *);
  81 #endif