drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "rootnv50.h"
  26
  27 static int
  28 g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  29               struct nvkm_oclass *oclass, void *data, u32 size,
  30               struct nvkm_object **pobject)
  31 {
  32         struct nv50_disp *disp;
  33         int ret;
  34
  35         ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
  36                                "display", &disp);
  37         *pobject = nv_object(disp);
  38         if (ret)
  39                 return ret;
  40
  41         ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
  42         if (ret)
  43                 return ret;
  44
  45         nv_engine(disp)->sclass = g84_disp_root_oclass;
  46         nv_engine(disp)->cclass = &nv50_disp_cclass;
  47         nv_subdev(disp)->intr = nv50_disp_intr;
  48         INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
  49         disp->sclass = g84_disp_sclass;
  50         disp->head.nr = 2;
  51         disp->dac.nr = 3;
  52         disp->sor.nr = 2;
  53         disp->pior.nr = 3;
  54         disp->dac.power = nv50_dac_power;
  55         disp->dac.sense = nv50_dac_sense;
  56         disp->sor.power = nv50_sor_power;
  57         disp->sor.hdmi = g84_hdmi_ctrl;
  58         disp->pior.power = nv50_pior_power;
  59         return 0;
  60 }
  61
  62 struct nvkm_oclass *
  63 g84_disp_oclass = &(struct nv50_disp_impl) {
  64         .base.base.handle = NV_ENGINE(DISP, 0x82),
  65         .base.base.ofuncs = &(struct nvkm_ofuncs) {
  66                 .ctor = g84_disp_ctor,
  67                 .dtor = _nvkm_disp_dtor,
  68                 .init = _nvkm_disp_init,
  69                 .fini = _nvkm_disp_fini,
  70         },
  71         .base.outp.internal.crt = nv50_dac_output_new,
  72         .base.outp.internal.tmds = nv50_sor_output_new,
  73         .base.outp.internal.lvds = nv50_sor_output_new,
  74         .base.outp.external.tmds = nv50_pior_output_new,
  75         .base.outp.external.dp = nv50_pior_dp_new,
  76         .base.vblank = &nv50_disp_vblank_func,
  77         .mthd.core = &g84_disp_core_mthd_chan,
  78         .mthd.base = &g84_disp_base_mthd_chan,
  79         .mthd.ovly = &g84_disp_ovly_mthd_chan,
  80         .mthd.prev = 0x000004,
  81         .head.scanoutpos = nv50_disp_root_scanoutpos,
  82 }.base.base;