drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "rootnv50.h"
  26
  27 static const struct nvkm_disp_func
  28 gm107_disp = {
  29         .root = &gm107_disp_root_oclass,
  30 };
  31
  32 static int
  33 gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  34                 struct nvkm_oclass *oclass, void *data, u32 size,
  35                 struct nvkm_object **pobject)
  36 {
  37         struct nvkm_device *device = (void *)parent;
  38         struct nv50_disp *disp;
  39         int heads = nvkm_rd32(device, 0x022448);
  40         int ret;
  41
  42         ret = nvkm_disp_create(parent, engine, oclass, heads,
  43                                "PDISP", "display", &disp);
  44         *pobject = nv_object(disp);
  45         if (ret)
  46                 return ret;
  47
  48         disp->base.func = &gm107_disp;
  49
  50         ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
  51         if (ret)
  52                 return ret;
  53
  54         nv_subdev(disp)->intr = gf119_disp_intr;
  55         INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
  56         disp->head.nr = heads;
  57         disp->dac.nr = 3;
  58         disp->sor.nr = 4;
  59         disp->dac.power = nv50_dac_power;
  60         disp->dac.sense = nv50_dac_sense;
  61         disp->sor.power = nv50_sor_power;
  62         disp->sor.hda_eld = gf119_hda_eld;
  63         disp->sor.hdmi = gk104_hdmi_ctrl;
  64         return 0;
  65 }
  66
  67 struct nvkm_oclass *
  68 gm107_disp_oclass = &(struct nv50_disp_impl) {
  69         .base.base.handle = NV_ENGINE(DISP, 0x07),
  70         .base.base.ofuncs = &(struct nvkm_ofuncs) {
  71                 .ctor = gm107_disp_ctor,
  72                 .dtor = _nvkm_disp_dtor,
  73                 .init = _nvkm_disp_init,
  74                 .fini = _nvkm_disp_fini,
  75         },
  76         .base.outp.internal.crt = nv50_dac_output_new,
  77         .base.outp.internal.tmds = nv50_sor_output_new,
  78         .base.outp.internal.lvds = nv50_sor_output_new,
  79         .base.outp.internal.dp = gf119_sor_dp_new,
  80         .base.vblank = &gf119_disp_vblank_func,
  81         .head.scanoutpos = gf119_disp_root_scanoutpos,
  82 }.base.base;