drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <core/client.h>
  28 #include <core/enum.h>
  29 #include <core/gpuobj.h>
  30 #include <subdev/bios.h>
  31 #include <subdev/bios/disp.h>
  32 #include <subdev/bios/init.h>
  33 #include <subdev/bios/pll.h>
  34 #include <subdev/devinit.h>
  35
  36 static const struct nvkm_disp_oclass *
  37 nv50_disp_root_(struct nvkm_disp *base)
  38 {
  39         return nv50_disp(base)->func->root;
  40 }
  41
  42 static int
  43 nv50_disp_outp_internal_crt_(struct nvkm_disp *base, int index,
  44                              struct dcb_output *dcb, struct nvkm_output **poutp)
  45 {
  46         struct nv50_disp *disp = nv50_disp(base);
  47         return disp->func->outp.internal.crt(base, index, dcb, poutp);
  48 }
  49
  50 static int
  51 nv50_disp_outp_internal_tmds_(struct nvkm_disp *base, int index,
  52                               struct dcb_output *dcb,
  53                               struct nvkm_output **poutp)
  54 {
  55         struct nv50_disp *disp = nv50_disp(base);
  56         return disp->func->outp.internal.tmds(base, index, dcb, poutp);
  57 }
  58
  59 static int
  60 nv50_disp_outp_internal_lvds_(struct nvkm_disp *base, int index,
  61                               struct dcb_output *dcb,
  62                               struct nvkm_output **poutp)
  63 {
  64         struct nv50_disp *disp = nv50_disp(base);
  65         return disp->func->outp.internal.lvds(base, index, dcb, poutp);
  66 }
  67
  68 static int
  69 nv50_disp_outp_internal_dp_(struct nvkm_disp *base, int index,
  70                             struct dcb_output *dcb, struct nvkm_output **poutp)
  71 {
  72         struct nv50_disp *disp = nv50_disp(base);
  73         if (disp->func->outp.internal.dp)
  74                 return disp->func->outp.internal.dp(base, index, dcb, poutp);
  75         return -ENODEV;
  76 }
  77
  78 static int
  79 nv50_disp_outp_external_tmds_(struct nvkm_disp *base, int index,
  80                               struct dcb_output *dcb,
  81                               struct nvkm_output **poutp)
  82 {
  83         struct nv50_disp *disp = nv50_disp(base);
  84         if (disp->func->outp.external.tmds)
  85                 return disp->func->outp.external.tmds(base, index, dcb, poutp);
  86         return -ENODEV;
  87 }
  88
  89 static int
  90 nv50_disp_outp_external_dp_(struct nvkm_disp *base, int index,
  91                             struct dcb_output *dcb, struct nvkm_output **poutp)
  92 {
  93         struct nv50_disp *disp = nv50_disp(base);
  94         if (disp->func->outp.external.dp)
  95                 return disp->func->outp.external.dp(base, index, dcb, poutp);
  96         return -ENODEV;
  97 }
  98
  99 static void
 100 nv50_disp_vblank_fini_(struct nvkm_disp *base, int head)
 101 {
 102         struct nv50_disp *disp = nv50_disp(base);
 103         disp->func->head.vblank_fini(disp, head);
 104 }
 105
 106 static void
 107 nv50_disp_vblank_init_(struct nvkm_disp *base, int head)
 108 {
 109         struct nv50_disp *disp = nv50_disp(base);
 110         disp->func->head.vblank_init(disp, head);
 111 }
 112
 113 static void
 114 nv50_disp_intr_(struct nvkm_disp *base)
 115 {
 116         struct nv50_disp *disp = nv50_disp(base);
 117         disp->func->intr(disp);
 118 }
 119
 120 static void *
 121 nv50_disp_dtor_(struct nvkm_disp *base)
 122 {
 123         struct nv50_disp *disp = nv50_disp(base);
 124         nvkm_event_fini(&disp->uevent);
 125         return disp;
 126 }
 127
 128 static const struct nvkm_disp_func
 129 nv50_disp_ = {
 130         .dtor = nv50_disp_dtor_,
 131         .intr = nv50_disp_intr_,
 132         .root = nv50_disp_root_,
 133         .outp.internal.crt = nv50_disp_outp_internal_crt_,
 134         .outp.internal.tmds = nv50_disp_outp_internal_tmds_,
 135         .outp.internal.lvds = nv50_disp_outp_internal_lvds_,
 136         .outp.internal.dp = nv50_disp_outp_internal_dp_,
 137         .outp.external.tmds = nv50_disp_outp_external_tmds_,
 138         .outp.external.dp = nv50_disp_outp_external_dp_,
 139         .head.vblank_init = nv50_disp_vblank_init_,
 140         .head.vblank_fini = nv50_disp_vblank_fini_,
 141 };
 142
 143 int
 144 nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
 145                int index, int heads, struct nvkm_disp **pdisp)
 146 {
 147         struct nv50_disp *disp;
 148         int ret;
 149
 150         if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL)))
 151                 return -ENOMEM;
 152         INIT_WORK(&disp->supervisor, func->super);
 153         disp->func = func;
 154         *pdisp = &disp->base;
 155
 156         ret = nvkm_disp_ctor(&nv50_disp_, device, index, heads, &disp->base);
 157         if (ret)
 158                 return ret;
 159
 160         return nvkm_event_init(func->uevent, 1, 1 + (heads * 4), &disp->uevent);
 161 }
 162
 163 void
 164 nv50_disp_vblank_fini(struct nv50_disp *disp, int head)
 165 {
 166         struct nvkm_device *device = disp->base.engine.subdev.device;
 167         nvkm_mask(device, 0x61002c, (4 << head), 0);
 168 }
 169
 170 void
 171 nv50_disp_vblank_init(struct nv50_disp *disp, int head)
 172 {
 173         struct nvkm_device *device = disp->base.engine.subdev.device;
 174         nvkm_mask(device, 0x61002c, (4 << head), (4 << head));
 175 }
 176
 177 static const struct nvkm_enum
 178 nv50_disp_intr_error_type[] = {
 179         { 3, "ILLEGAL_MTHD" },
 180         { 4, "INVALID_VALUE" },
 181         { 5, "INVALID_STATE" },
 182         { 7, "INVALID_HANDLE" },
 183         {}
 184 };
 185
 186 static const struct nvkm_enum
 187 nv50_disp_intr_error_code[] = {
 188         { 0x00, "" },
 189         {}
 190 };
 191
 192 static void
 193 nv50_disp_intr_error(struct nv50_disp *disp, int chid)
 194 {
 195         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 196         struct nvkm_device *device = subdev->device;
 197         u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08));
 198         u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08));
 199         u32 code = (addr & 0x00ff0000) >> 16;
 200         u32 type = (addr & 0x00007000) >> 12;
 201         u32 mthd = (addr & 0x00000ffc);
 202         const struct nvkm_enum *ec, *et;
 203
 204         et = nvkm_enum_find(nv50_disp_intr_error_type, type);
 205         ec = nvkm_enum_find(nv50_disp_intr_error_code, code);
 206
 207         nvkm_error(subdev,
 208                    "ERROR %d [%s] %02x [%s] chid %d mthd %04x data %08x\n",
 209                    type, et ? et->name : "", code, ec ? ec->name : "",
 210                    chid, mthd, data);
 211
 212         if (chid < ARRAY_SIZE(disp->chan)) {
 213                 switch (mthd) {
 214                 case 0x0080:
 215                         nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
 216                         break;
 217                 default:
 218                         break;
 219                 }
 220         }
 221
 222         nvkm_wr32(device, 0x610020, 0x00010000 << chid);
 223         nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000);
 224 }
 225
 226 static struct nvkm_output *
 227 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
 228             u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 229             struct nvbios_outp *info)
 230 {
 231         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 232         struct nvkm_bios *bios = subdev->device->bios;
 233         struct nvkm_output *outp;
 234         u16 mask, type;
 235
 236         if (or < 4) {
 237                 type = DCB_OUTPUT_ANALOG;
 238                 mask = 0;
 239         } else
 240         if (or < 8) {
 241                 switch (ctrl & 0x00000f00) {
 242                 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
 243                 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
 244                 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
 245                 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
 246                 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
 247                 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
 248                 default:
 249                         nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl);
 250                         return NULL;
 251                 }
 252                 or  -= 4;
 253         } else {
 254                 or   = or - 8;
 255                 type = 0x0010;
 256                 mask = 0;
 257                 switch (ctrl & 0x00000f00) {
 258                 case 0x00000000: type |= disp->pior.type[or]; break;
 259                 default:
 260                         nvkm_error(subdev, "unknown PIOR mc %08x\n", ctrl);
 261                         return NULL;
 262                 }
 263         }
 264
 265         mask  = 0x00c0 & (mask << 6);
 266         mask |= 0x0001 << or;
 267         mask |= 0x0100 << head;
 268
 269         list_for_each_entry(outp, &disp->base.outp, head) {
 270                 if ((outp->info.hasht & 0xff) == type &&
 271                     (outp->info.hashm & mask) == mask) {
 272                         *data = nvbios_outp_match(bios, outp->info.hasht,
 273                                                         outp->info.hashm,
 274                                                   ver, hdr, cnt, len, info);
 275                         if (!*data)
 276                                 return NULL;
 277                         return outp;
 278                 }
 279         }
 280
 281         return NULL;
 282 }
 283
 284 static struct nvkm_output *
 285 exec_script(struct nv50_disp *disp, int head, int id)
 286 {
 287         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 288         struct nvkm_device *device = subdev->device;
 289         struct nvkm_bios *bios = device->bios;
 290         struct nvkm_output *outp;
 291         struct nvbios_outp info;
 292         u8  ver, hdr, cnt, len;
 293         u32 data, ctrl = 0;
 294         u32 reg;
 295         int i;
 296
 297         /* DAC */
 298         for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
 299                 ctrl = nvkm_rd32(device, 0x610b5c + (i * 8));
 300
 301         /* SOR */
 302         if (!(ctrl & (1 << head))) {
 303                 if (device->chipset  < 0x90 ||
 304                     device->chipset == 0x92 ||
 305                     device->chipset == 0xa0) {
 306                         reg = 0x610b74;
 307                 } else {
 308                         reg = 0x610798;
 309                 }
 310                 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
 311                         ctrl = nvkm_rd32(device, reg + (i * 8));
 312                 i += 4;
 313         }
 314
 315         /* PIOR */
 316         if (!(ctrl & (1 << head))) {
 317                 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
 318                         ctrl = nvkm_rd32(device, 0x610b84 + (i * 8));
 319                 i += 8;
 320         }
 321
 322         if (!(ctrl & (1 << head)))
 323                 return NULL;
 324         i--;
 325
 326         outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
 327         if (outp) {
 328                 struct nvbios_init init = {
 329                         .subdev = subdev,
 330                         .bios = bios,
 331                         .offset = info.script[id],
 332                         .outp = &outp->info,
 333                         .crtc = head,
 334                         .execute = 1,
 335                 };
 336
 337                 nvbios_exec(&init);
 338         }
 339
 340         return outp;
 341 }
 342
 343 static struct nvkm_output *
 344 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
 345 {
 346         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 347         struct nvkm_device *device = subdev->device;
 348         struct nvkm_bios *bios = device->bios;
 349         struct nvkm_output *outp;
 350         struct nvbios_outp info1;
 351         struct nvbios_ocfg info2;
 352         u8  ver, hdr, cnt, len;
 353         u32 data, ctrl = 0;
 354         u32 reg;
 355         int i;
 356
 357         /* DAC */
 358         for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
 359                 ctrl = nvkm_rd32(device, 0x610b58 + (i * 8));
 360
 361         /* SOR */
 362         if (!(ctrl & (1 << head))) {
 363                 if (device->chipset  < 0x90 ||
 364                     device->chipset == 0x92 ||
 365                     device->chipset == 0xa0) {
 366                         reg = 0x610b70;
 367                 } else {
 368                         reg = 0x610794;
 369                 }
 370                 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
 371                         ctrl = nvkm_rd32(device, reg + (i * 8));
 372                 i += 4;
 373         }
 374
 375         /* PIOR */
 376         if (!(ctrl & (1 << head))) {
 377                 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
 378                         ctrl = nvkm_rd32(device, 0x610b80 + (i * 8));
 379                 i += 8;
 380         }
 381
 382         if (!(ctrl & (1 << head)))
 383                 return NULL;
 384         i--;
 385
 386         outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
 387         if (!outp)
 388                 return NULL;
 389
 390         *conf = (ctrl & 0x00000f00) >> 8;
 391         if (outp->info.location == 0) {
 392                 switch (outp->info.type) {
 393                 case DCB_OUTPUT_TMDS:
 394                         if (*conf == 5)
 395                                 *conf |= 0x0100;
 396                         break;
 397                 case DCB_OUTPUT_LVDS:
 398                         *conf |= disp->sor.lvdsconf;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         } else {
 404                 *conf = (ctrl & 0x00000f00) >> 8;
 405                 pclk = pclk / 2;
 406         }
 407
 408         data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
 409                                  &ver, &hdr, &cnt, &len, &info2);
 410         if (data && id < 0xff) {
 411                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
 412                 if (data) {
 413                         struct nvbios_init init = {
 414                                 .subdev = subdev,
 415                                 .bios = bios,
 416                                 .offset = data,
 417                                 .outp = &outp->info,
 418                                 .crtc = head,
 419                                 .execute = 1,
 420                         };
 421
 422                         nvbios_exec(&init);
 423                 }
 424         }
 425
 426         return outp;
 427 }
 428
 429 static void
 430 nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head)
 431 {
 432         exec_script(disp, head, 1);
 433 }
 434
 435 static void
 436 nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head)
 437 {
 438         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 439         struct nvkm_output *outp = exec_script(disp, head, 2);
 440
 441         /* the binary driver does this outside of the supervisor handling
 442          * (after the third supervisor from a detach).  we (currently?)
 443          * allow both detach/attach to happen in the same set of
 444          * supervisor interrupts, so it would make sense to execute this
 445          * (full power down?) script after all the detach phases of the
 446          * supervisor handling.  like with training if needed from the
 447          * second supervisor, nvidia doesn't do this, so who knows if it's
 448          * entirely safe, but it does appear to work..
 449          *
 450          * without this script being run, on some configurations i've
 451          * seen, switching from DP to TMDS on a DP connector may result
 452          * in a blank screen (SOR_PWR off/on can restore it)
 453          */
 454         if (outp && outp->info.type == DCB_OUTPUT_DP) {
 455                 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
 456                 struct nvbios_init init = {
 457                         .subdev = subdev,
 458                         .bios = subdev->device->bios,
 459                         .outp = &outp->info,
 460                         .crtc = head,
 461                         .offset = outpdp->info.script[4],
 462                         .execute = 1,
 463                 };
 464
 465                 nvbios_exec(&init);
 466                 atomic_set(&outpdp->lt.done, 0);
 467         }
 468 }
 469
 470 static void
 471 nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head)
 472 {
 473         struct nvkm_device *device = disp->base.engine.subdev.device;
 474         struct nvkm_devinit *devinit = device->devinit;
 475         u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
 476         if (pclk)
 477                 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
 478 }
 479
 480 static void
 481 nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head,
 482                           struct dcb_output *outp, u32 pclk)
 483 {
 484         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 485         struct nvkm_device *device = subdev->device;
 486         const int link = !(outp->sorconf.link & 1);
 487         const int   or = ffs(outp->or) - 1;
 488         const u32 soff = (  or * 0x800);
 489         const u32 loff = (link * 0x080) + soff;
 490         const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8));
 491         const u32 symbol = 100000;
 492         const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff;
 493         const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff;
 494         const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff;
 495         u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
 496         u32 clksor = nvkm_rd32(device, 0x614300 + soff);
 497         int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
 498         int TU, VTUi, VTUf, VTUa;
 499         u64 link_data_rate, link_ratio, unk;
 500         u32 best_diff = 64 * symbol;
 501         u32 link_nr, link_bw, bits;
 502         u64 value;
 503
 504         link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
 505         link_nr = hweight32(dpctrl & 0x000f0000);
 506
 507         /* symbols/hblank - algorithm taken from comments in tegra driver */
 508         value = vblanke + vactive - vblanks - 7;
 509         value = value * link_bw;
 510         do_div(value, pclk);
 511         value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
 512         nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value);
 513
 514         /* symbols/vblank - algorithm taken from comments in tegra driver */
 515         value = vblanks - vblanke - 25;
 516         value = value * link_bw;
 517         do_div(value, pclk);
 518         value = value - ((36 / link_nr) + 3) - 1;
 519         nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value);
 520
 521         /* watermark / activesym */
 522         if      ((ctrl & 0xf0000) == 0x60000) bits = 30;
 523         else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
 524         else                                  bits = 18;
 525
 526         link_data_rate = (pclk * bits / 8) / link_nr;
 527
 528         /* calculate ratio of packed data rate to link symbol rate */
 529         link_ratio = link_data_rate * symbol;
 530         do_div(link_ratio, link_bw);
 531
 532         for (TU = 64; TU >= 32; TU--) {
 533                 /* calculate average number of valid symbols in each TU */
 534                 u32 tu_valid = link_ratio * TU;
 535                 u32 calc, diff;
 536
 537                 /* find a hw representation for the fraction.. */
 538                 VTUi = tu_valid / symbol;
 539                 calc = VTUi * symbol;
 540                 diff = tu_valid - calc;
 541                 if (diff) {
 542                         if (diff >= (symbol / 2)) {
 543                                 VTUf = symbol / (symbol - diff);
 544                                 if (symbol - (VTUf * diff))
 545                                         VTUf++;
 546
 547                                 if (VTUf <= 15) {
 548                                         VTUa  = 1;
 549                                         calc += symbol - (symbol / VTUf);
 550                                 } else {
 551                                         VTUa  = 0;
 552                                         VTUf  = 1;
 553                                         calc += symbol;
 554                                 }
 555                         } else {
 556                                 VTUa  = 0;
 557                                 VTUf  = min((int)(symbol / diff), 15);
 558                                 calc += symbol / VTUf;
 559                         }
 560
 561                         diff = calc - tu_valid;
 562                 } else {
 563                         /* no remainder, but the hw doesn't like the fractional
 564                          * part to be zero.  decrement the integer part and
 565                          * have the fraction add a whole symbol back
 566                          */
 567                         VTUa = 0;
 568                         VTUf = 1;
 569                         VTUi--;
 570                 }
 571
 572                 if (diff < best_diff) {
 573                         best_diff = diff;
 574                         bestTU = TU;
 575                         bestVTUa = VTUa;
 576                         bestVTUf = VTUf;
 577                         bestVTUi = VTUi;
 578                         if (diff == 0)
 579                                 break;
 580                 }
 581         }
 582
 583         if (!bestTU) {
 584                 nvkm_error(subdev, "unable to find suitable dp config\n");
 585                 return;
 586         }
 587
 588         /* XXX close to vbios numbers, but not right */
 589         unk  = (symbol - link_ratio) * bestTU;
 590         unk *= link_ratio;
 591         do_div(unk, symbol);
 592         do_div(unk, symbol);
 593         unk += 6;
 594
 595         nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2);
 596         nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
 597                                                    bestVTUf << 16 |
 598                                                    bestVTUi << 8 | unk);
 599 }
 600
 601 static void
 602 nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head)
 603 {
 604         struct nvkm_device *device = disp->base.engine.subdev.device;
 605         struct nvkm_output *outp;
 606         u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
 607         u32 hval, hreg = 0x614200 + (head * 0x800);
 608         u32 oval, oreg;
 609         u32 mask, conf;
 610
 611         outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
 612         if (!outp)
 613                 return;
 614
 615         /* we allow both encoder attach and detach operations to occur
 616          * within a single supervisor (ie. modeset) sequence.  the
 617          * encoder detach scripts quite often switch off power to the
 618          * lanes, which requires the link to be re-trained.
 619          *
 620          * this is not generally an issue as the sink "must" (heh)
 621          * signal an irq when it's lost sync so the driver can
 622          * re-train.
 623          *
 624          * however, on some boards, if one does not configure at least
 625          * the gpu side of the link *before* attaching, then various
 626          * things can go horribly wrong (PDISP disappearing from mmio,
 627          * third supervisor never happens, etc).
 628          *
 629          * the solution is simply to retrain here, if necessary.  last
 630          * i checked, the binary driver userspace does not appear to
 631          * trigger this situation (it forces an UPDATE between steps).
 632          */
 633         if (outp->info.type == DCB_OUTPUT_DP) {
 634                 u32 soff = (ffs(outp->info.or) - 1) * 0x08;
 635                 u32 ctrl, datarate;
 636
 637                 if (outp->info.location == 0) {
 638                         ctrl = nvkm_rd32(device, 0x610794 + soff);
 639                         soff = 1;
 640                 } else {
 641                         ctrl = nvkm_rd32(device, 0x610b80 + soff);
 642                         soff = 2;
 643                 }
 644
 645                 switch ((ctrl & 0x000f0000) >> 16) {
 646                 case 6: datarate = pclk * 30; break;
 647                 case 5: datarate = pclk * 24; break;
 648                 case 2:
 649                 default:
 650                         datarate = pclk * 18;
 651                         break;
 652                 }
 653
 654                 if (nvkm_output_dp_train(outp, datarate / soff, true))
 655                         OUTP_ERR(outp, "link not trained before attach");
 656         }
 657
 658         exec_clkcmp(disp, head, 0, pclk, &conf);
 659
 660         if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) {
 661                 oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800;
 662                 oval = 0x00000000;
 663                 hval = 0x00000000;
 664                 mask = 0xffffffff;
 665         } else
 666         if (!outp->info.location) {
 667                 if (outp->info.type == DCB_OUTPUT_DP)
 668                         nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk);
 669                 oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800;
 670                 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
 671                 hval = 0x00000000;
 672                 mask = 0x00000707;
 673         } else {
 674                 oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800;
 675                 oval = 0x00000001;
 676                 hval = 0x00000001;
 677                 mask = 0x00000707;
 678         }
 679
 680         nvkm_mask(device, hreg, 0x0000000f, hval);
 681         nvkm_mask(device, oreg, mask, oval);
 682 }
 683
 684 /* If programming a TMDS output on a SOR that can also be configured for
 685  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 686  *
 687  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 688  * the VBIOS scripts on at least one board I have only switch it off on
 689  * link 0, causing a blank display if the output has previously been
 690  * programmed for DisplayPort.
 691  */
 692 static void
 693 nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp,
 694                             struct dcb_output *outp)
 695 {
 696         struct nvkm_device *device = disp->base.engine.subdev.device;
 697         struct nvkm_bios *bios = device->bios;
 698         const int link = !(outp->sorconf.link & 1);
 699         const int   or = ffs(outp->or) - 1;
 700         const u32 loff = (or * 0x800) + (link * 0x80);
 701         const u16 mask = (outp->sorconf.link << 6) | outp->or;
 702         struct dcb_output match;
 703         u8  ver, hdr;
 704
 705         if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match))
 706                 nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000);
 707 }
 708
 709 static void
 710 nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head)
 711 {
 712         struct nvkm_device *device = disp->base.engine.subdev.device;
 713         struct nvkm_output *outp;
 714         u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
 715         u32 conf;
 716
 717         outp = exec_clkcmp(disp, head, 1, pclk, &conf);
 718         if (!outp)
 719                 return;
 720
 721         if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS)
 722                 nv50_disp_intr_unk40_0_tmds(disp, &outp->info);
 723 }
 724
 725 void
 726 nv50_disp_intr_supervisor(struct work_struct *work)
 727 {
 728         struct nv50_disp *disp =
 729                 container_of(work, struct nv50_disp, supervisor);
 730         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
 731         struct nvkm_device *device = subdev->device;
 732         u32 super = nvkm_rd32(device, 0x610030);
 733         int head;
 734
 735         nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super);
 736
 737         if (disp->super & 0x00000010) {
 738                 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
 739                 for (head = 0; head < disp->base.head.nr; head++) {
 740                         if (!(super & (0x00000020 << head)))
 741                                 continue;
 742                         if (!(super & (0x00000080 << head)))
 743                                 continue;
 744                         nv50_disp_intr_unk10_0(disp, head);
 745                 }
 746         } else
 747         if (disp->super & 0x00000020) {
 748                 for (head = 0; head < disp->base.head.nr; head++) {
 749                         if (!(super & (0x00000080 << head)))
 750                                 continue;
 751                         nv50_disp_intr_unk20_0(disp, head);
 752                 }
 753                 for (head = 0; head < disp->base.head.nr; head++) {
 754                         if (!(super & (0x00000200 << head)))
 755                                 continue;
 756                         nv50_disp_intr_unk20_1(disp, head);
 757                 }
 758                 for (head = 0; head < disp->base.head.nr; head++) {
 759                         if (!(super & (0x00000080 << head)))
 760                                 continue;
 761                         nv50_disp_intr_unk20_2(disp, head);
 762                 }
 763         } else
 764         if (disp->super & 0x00000040) {
 765                 for (head = 0; head < disp->base.head.nr; head++) {
 766                         if (!(super & (0x00000080 << head)))
 767                                 continue;
 768                         nv50_disp_intr_unk40_0(disp, head);
 769                 }
 770         }
 771
 772         nvkm_wr32(device, 0x610030, 0x80000000);
 773 }
 774
 775 void
 776 nv50_disp_intr(struct nv50_disp *disp)
 777 {
 778         struct nvkm_device *device = disp->base.engine.subdev.device;
 779         u32 intr0 = nvkm_rd32(device, 0x610020);
 780         u32 intr1 = nvkm_rd32(device, 0x610024);
 781
 782         while (intr0 & 0x001f0000) {
 783                 u32 chid = __ffs(intr0 & 0x001f0000) - 16;
 784                 nv50_disp_intr_error(disp, chid);
 785                 intr0 &= ~(0x00010000 << chid);
 786         }
 787
 788         while (intr0 & 0x0000001f) {
 789                 u32 chid = __ffs(intr0 & 0x0000001f);
 790                 nv50_disp_chan_uevent_send(disp, chid);
 791                 intr0 &= ~(0x00000001 << chid);
 792         }
 793
 794         if (intr1 & 0x00000004) {
 795                 nvkm_disp_vblank(&disp->base, 0);
 796                 nvkm_wr32(device, 0x610024, 0x00000004);
 797         }
 798
 799         if (intr1 & 0x00000008) {
 800                 nvkm_disp_vblank(&disp->base, 1);
 801                 nvkm_wr32(device, 0x610024, 0x00000008);
 802         }
 803
 804         if (intr1 & 0x00000070) {
 805                 disp->super = (intr1 & 0x00000070);
 806                 schedule_work(&disp->supervisor);
 807                 nvkm_wr32(device, 0x610024, disp->super);
 808         }
 809 }
 810
 811 static const struct nv50_disp_func
 812 nv50_disp = {
 813         .intr = nv50_disp_intr,
 814         .uevent = &nv50_disp_chan_uevent,
 815         .super = nv50_disp_intr_supervisor,
 816         .root = &nv50_disp_root_oclass,
 817         .head.vblank_init = nv50_disp_vblank_init,
 818         .head.vblank_fini = nv50_disp_vblank_fini,
 819         .head.scanoutpos = nv50_disp_root_scanoutpos,
 820         .outp.internal.crt = nv50_dac_output_new,
 821         .outp.internal.tmds = nv50_sor_output_new,
 822         .outp.internal.lvds = nv50_sor_output_new,
 823         .outp.external.tmds = nv50_pior_output_new,
 824         .outp.external.dp = nv50_pior_dp_new,
 825         .dac.nr = 3,
 826         .dac.power = nv50_dac_power,
 827         .dac.sense = nv50_dac_sense,
 828         .sor.nr = 2,
 829         .sor.power = nv50_sor_power,
 830         .pior.nr = 3,
 831         .pior.power = nv50_pior_power,
 832 };
 833
 834 int
 835 nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
 836 {
 837         return nv50_disp_new_(&nv50_disp, device, index, 2, pdisp);
 838 }