drivers/gpu/drm/nouveau/nvkm/engine/disp/piocnv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "channv50.h"
  25 #include "rootnv50.h"
  26
  27 #include <subdev/timer.h>
  28
  29 static void
  30 nv50_disp_pioc_fini(struct nv50_disp_chan *chan)
  31 {
  32         struct nv50_disp *disp = chan->root->disp;
  33         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  34         struct nvkm_device *device = subdev->device;
  35         int chid = chan->chid;
  36
  37         nvkm_mask(device, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);
  38         if (nvkm_msec(device, 2000,
  39                 if (!(nvkm_rd32(device, 0x610200 + (chid * 0x10)) & 0x00030000))
  40                         break;
  41         ) < 0) {
  42                 nvkm_error(subdev, "ch %d timeout: %08x\n", chid,
  43                            nvkm_rd32(device, 0x610200 + (chid * 0x10)));
  44         }
  45 }
  46
  47 static int
  48 nv50_disp_pioc_init(struct nv50_disp_chan *chan)
  49 {
  50         struct nv50_disp *disp = chan->root->disp;
  51         struct nvkm_subdev *subdev = &disp->base.engine.subdev;
  52         struct nvkm_device *device = subdev->device;
  53         int chid = chan->chid;
  54
  55         nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00002000);
  56         if (nvkm_msec(device, 2000,
  57                 if (!(nvkm_rd32(device, 0x610200 + (chid * 0x10)) & 0x00030000))
  58                         break;
  59         ) < 0) {
  60                 nvkm_error(subdev, "ch %d timeout0: %08x\n", chid,
  61                            nvkm_rd32(device, 0x610200 + (chid * 0x10)));
  62                 return -EBUSY;
  63         }
  64
  65         nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00000001);
  66         if (nvkm_msec(device, 2000,
  67                 u32 tmp = nvkm_rd32(device, 0x610200 + (chid * 0x10));
  68                 if ((tmp & 0x00030000) == 0x00010000)
  69                         break;
  70         ) < 0) {
  71                 nvkm_error(subdev, "ch %d timeout1: %08x\n", chid,
  72                            nvkm_rd32(device, 0x610200 + (chid * 0x10)));
  73                 return -EBUSY;
  74         }
  75
  76         return 0;
  77 }
  78
  79 const struct nv50_disp_chan_func
  80 nv50_disp_pioc_func = {
  81         .init = nv50_disp_pioc_init,
  82         .fini = nv50_disp_pioc_fini,
  83 };