drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs <bskeggs@redhat.com>
  23  */
  24
  25 #include "nvc0.h"
  26 #include "ctxnvc0.h"
  27
  28 /*******************************************************************************
  29  * PGRAPH register lists
  30  ******************************************************************************/
  31
  32 static const struct nvc0_gr_init
  33 nvd7_gr_init_pe_0[] = {
  34         { 0x41980c,   1, 0x04, 0x00000010 },
  35         { 0x419844,   1, 0x04, 0x00000000 },
  36         { 0x41984c,   1, 0x04, 0x00005bc8 },
  37         { 0x419850,   3, 0x04, 0x00000000 },
  38         {}
  39 };
  40
  41 const struct nvc0_gr_init
  42 nvd7_gr_init_pes_0[] = {
  43         { 0x41be04,   1, 0x04, 0x00000000 },
  44         { 0x41be08,   1, 0x04, 0x00000004 },
  45         { 0x41be0c,   1, 0x04, 0x00000000 },
  46         { 0x41be10,   1, 0x04, 0x003b8bc7 },
  47         { 0x41be14,   2, 0x04, 0x00000000 },
  48         {}
  49 };
  50
  51 const struct nvc0_gr_init
  52 nvd7_gr_init_wwdx_0[] = {
  53         { 0x41bfd4,   1, 0x04, 0x00800000 },
  54         { 0x41bfdc,   1, 0x04, 0x00000000 },
  55         { 0x41bff8,   2, 0x04, 0x00000000 },
  56         {}
  57 };
  58
  59 const struct nvc0_gr_init
  60 nvd7_gr_init_cbm_0[] = {
  61         { 0x41becc,   1, 0x04, 0x00000000 },
  62         { 0x41bee8,   2, 0x04, 0x00000000 },
  63         {}
  64 };
  65
  66 static const struct nvc0_gr_pack
  67 nvd7_gr_pack_mmio[] = {
  68         { nvc0_gr_init_main_0 },
  69         { nvc0_gr_init_fe_0 },
  70         { nvc0_gr_init_pri_0 },
  71         { nvc0_gr_init_rstr2d_0 },
  72         { nvd9_gr_init_pd_0 },
  73         { nvd9_gr_init_ds_0 },
  74         { nvc0_gr_init_scc_0 },
  75         { nvd9_gr_init_prop_0 },
  76         { nvc1_gr_init_gpc_unk_0 },
  77         { nvc0_gr_init_setup_0 },
  78         { nvc0_gr_init_crstr_0 },
  79         { nvc1_gr_init_setup_1 },
  80         { nvc0_gr_init_zcull_0 },
  81         { nvd9_gr_init_gpm_0 },
  82         { nvd9_gr_init_gpc_unk_1 },
  83         { nvc0_gr_init_gcc_0 },
  84         { nvc0_gr_init_tpccs_0 },
  85         { nvd9_gr_init_tex_0 },
  86         { nvd7_gr_init_pe_0 },
  87         { nvc0_gr_init_l1c_0 },
  88         { nvc0_gr_init_mpc_0 },
  89         { nvd9_gr_init_sm_0 },
  90         { nvd7_gr_init_pes_0 },
  91         { nvd7_gr_init_wwdx_0 },
  92         { nvd7_gr_init_cbm_0 },
  93         { nvc0_gr_init_be_0 },
  94         { nvd9_gr_init_fe_1 },
  95         {}
  96 };
  97
  98 /*******************************************************************************
  99  * PGRAPH engine/subdev functions
 100  ******************************************************************************/
 101
 102 #include "fuc/hubnvd7.fuc3.h"
 103
 104 struct nvc0_gr_ucode
 105 nvd7_gr_fecs_ucode = {
 106         .code.data = nvd7_grhub_code,
 107         .code.size = sizeof(nvd7_grhub_code),
 108         .data.data = nvd7_grhub_data,
 109         .data.size = sizeof(nvd7_grhub_data),
 110 };
 111
 112 #include "fuc/gpcnvd7.fuc3.h"
 113
 114 struct nvc0_gr_ucode
 115 nvd7_gr_gpccs_ucode = {
 116         .code.data = nvd7_grgpc_code,
 117         .code.size = sizeof(nvd7_grgpc_code),
 118         .data.data = nvd7_grgpc_data,
 119         .data.size = sizeof(nvd7_grgpc_data),
 120 };
 121
 122 struct nouveau_oclass *
 123 nvd7_gr_oclass = &(struct nvc0_gr_oclass) {
 124         .base.handle = NV_ENGINE(GR, 0xd7),
 125         .base.ofuncs = &(struct nouveau_ofuncs) {
 126                 .ctor = nvc0_gr_ctor,
 127                 .dtor = nvc0_gr_dtor,
 128                 .init = nvc0_gr_init,
 129                 .fini = _nouveau_gr_fini,
 130         },
 131         .cclass = &nvd7_grctx_oclass,
 132         .sclass = nvc8_gr_sclass,
 133         .mmio = nvd7_gr_pack_mmio,
 134         .fecs.ucode = &nvd7_gr_fecs_ucode,
 135         .gpccs.ucode = &nvd7_gr_gpccs_ucode,
 136         .ppc_nr = 1,
 137 }.base;