drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <subdev/bios.h>
  25 #include <subdev/bios/bit.h>
  26 #include <subdev/bios/dp.h>
  27
  28 static u16
  29 nvbios_dp_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
  30 {
  31         struct bit_entry d;
  32
  33         if (!bit_entry(bios, 'd', &d)) {
  34                 if (d.version == 1 && d.length >= 2) {
  35                         u16 data = nvbios_rd16(bios, d.offset);
  36                         if (data) {
  37                                 *ver = nvbios_rd08(bios, data + 0x00);
  38                                 switch (*ver) {
  39                                 case 0x21:
  40                                 case 0x30:
  41                                 case 0x40:
  42                                 case 0x41:
  43                                 case 0x42:
  44                                         *hdr = nvbios_rd08(bios, data + 0x01);
  45                                         *len = nvbios_rd08(bios, data + 0x02);
  46                                         *cnt = nvbios_rd08(bios, data + 0x03);
  47                                         return data;
  48                                 default:
  49                                         break;
  50                                 }
  51                         }
  52                 }
  53         }
  54
  55         return 0x0000;
  56 }
  57
  58 static u16
  59 nvbios_dpout_entry(struct nvkm_bios *bios, u8 idx,
  60                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
  61 {
  62         u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len);
  63         if (data && idx < *cnt) {
  64                 u16 outp = nvbios_rd16(bios, data + *hdr + idx * *len);
  65                 switch (*ver * !!outp) {
  66                 case 0x21:
  67                 case 0x30:
  68                         *hdr = nvbios_rd08(bios, data + 0x04);
  69                         *len = nvbios_rd08(bios, data + 0x05);
  70                         *cnt = nvbios_rd08(bios, outp + 0x04);
  71                         break;
  72                 case 0x40:
  73                 case 0x41:
  74                 case 0x42:
  75                         *hdr = nvbios_rd08(bios, data + 0x04);
  76                         *cnt = 0;
  77                         *len = 0;
  78                         break;
  79                 default:
  80                         break;
  81                 }
  82                 return outp;
  83         }
  84         *ver = 0x00;
  85         return 0x0000;
  86 }
  87
  88 u16
  89 nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx,
  90                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
  91                    struct nvbios_dpout *info)
  92 {
  93         u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
  94         memset(info, 0x00, sizeof(*info));
  95         if (data && *ver) {
  96                 info->type = nvbios_rd16(bios, data + 0x00);
  97                 info->mask = nvbios_rd16(bios, data + 0x02);
  98                 switch (*ver) {
  99                 case 0x21:
 100                 case 0x30:
 101                         info->flags     = nvbios_rd08(bios, data + 0x05);
 102                         info->script[0] = nvbios_rd16(bios, data + 0x06);
 103                         info->script[1] = nvbios_rd16(bios, data + 0x08);
 104                         info->lnkcmp    = nvbios_rd16(bios, data + 0x0a);
 105                         if (*len >= 0x0f) {
 106                                 info->script[2] = nvbios_rd16(bios, data + 0x0c);
 107                                 info->script[3] = nvbios_rd16(bios, data + 0x0e);
 108                         }
 109                         if (*len >= 0x11)
 110                                 info->script[4] = nvbios_rd16(bios, data + 0x10);
 111                         break;
 112                 case 0x40:
 113                 case 0x41:
 114                 case 0x42:
 115                         info->flags     = nvbios_rd08(bios, data + 0x04);
 116                         info->script[0] = nvbios_rd16(bios, data + 0x05);
 117                         info->script[1] = nvbios_rd16(bios, data + 0x07);
 118                         info->lnkcmp    = nvbios_rd16(bios, data + 0x09);
 119                         info->script[2] = nvbios_rd16(bios, data + 0x0b);
 120                         info->script[3] = nvbios_rd16(bios, data + 0x0d);
 121                         info->script[4] = nvbios_rd16(bios, data + 0x0f);
 122                         break;
 123                 default:
 124                         data = 0x0000;
 125                         break;
 126                 }
 127         }
 128         return data;
 129 }
 130
 131 u16
 132 nvbios_dpout_match(struct nvkm_bios *bios, u16 type, u16 mask,
 133                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 134                    struct nvbios_dpout *info)
 135 {
 136         u16 data, idx = 0;
 137         while ((data = nvbios_dpout_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) {
 138                 if (data && info->type == type) {
 139                         if ((info->mask & mask) == mask)
 140                                 break;
 141                 }
 142         }
 143         return data;
 144 }
 145
 146 static u16
 147 nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
 148                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
 149 {
 150         if (*ver >= 0x40) {
 151                 outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
 152                 *hdr = *hdr + (*len * * cnt);
 153                 *len = nvbios_rd08(bios, outp + 0x06);
 154                 *cnt = nvbios_rd08(bios, outp + 0x07) *
 155                        nvbios_rd08(bios, outp + 0x05);
 156         }
 157
 158         if (idx < *cnt)
 159                 return outp + *hdr + (idx * *len);
 160
 161         return 0x0000;
 162 }
 163
 164 u16
 165 nvbios_dpcfg_parse(struct nvkm_bios *bios, u16 outp, u8 idx,
 166                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 167                    struct nvbios_dpcfg *info)
 168 {
 169         u16 data = nvbios_dpcfg_entry(bios, outp, idx, ver, hdr, cnt, len);
 170         memset(info, 0x00, sizeof(*info));
 171         if (data) {
 172                 switch (*ver) {
 173                 case 0x21:
 174                         info->dc    = nvbios_rd08(bios, data + 0x02);
 175                         info->pe    = nvbios_rd08(bios, data + 0x03);
 176                         info->tx_pu = nvbios_rd08(bios, data + 0x04);
 177                         break;
 178                 case 0x30:
 179                 case 0x40:
 180                 case 0x41:
 181                         info->pc    = nvbios_rd08(bios, data + 0x00);
 182                         info->dc    = nvbios_rd08(bios, data + 0x01);
 183                         info->pe    = nvbios_rd08(bios, data + 0x02);
 184                         info->tx_pu = nvbios_rd08(bios, data + 0x03);
 185                         break;
 186                 case 0x42:
 187                         info->dc    = nvbios_rd08(bios, data + 0x00);
 188                         info->pe    = nvbios_rd08(bios, data + 0x01);
 189                         info->tx_pu = nvbios_rd08(bios, data + 0x02);
 190                         break;
 191                 default:
 192                         data = 0x0000;
 193                         break;
 194                 }
 195         }
 196         return data;
 197 }
 198
 199 u16
 200 nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
 201                    u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 202                    struct nvbios_dpcfg *info)
 203 {
 204         u8 idx = 0xff;
 205         u16 data;
 206
 207         if (*ver >= 0x30) {
 208                 const u8 vsoff[] = { 0, 4, 7, 9 };
 209                 idx = (pc * 10) + vsoff[vs] + pe;
 210                 if (*ver >= 0x40 && *ver <= 0x41 && *hdr >= 0x12)
 211                         idx += nvbios_rd08(bios, outp + 0x11) * 40;
 212                 else
 213                 if (*ver >= 0x42)
 214                         idx += nvbios_rd08(bios, outp + 0x11) * 10;
 215         } else {
 216                 while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
 217                                                   ver, hdr, cnt, len))) {
 218                         if (nvbios_rd08(bios, data + 0x00) == vs &&
 219                             nvbios_rd08(bios, data + 0x01) == pe)
 220                                 break;
 221                 }
 222         }
 223
 224         return nvbios_dpcfg_parse(bios, outp, idx, ver, hdr, cnt, len, info);
 225 }