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drm/nouveau/bios/dp: support DP Info Table 2.0
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvkm / subdev / bios / init.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/bmp.h>
27 #include <subdev/bios/conn.h>
28 #include <subdev/bios/dcb.h>
29 #include <subdev/bios/dp.h>
30 #include <subdev/bios/gpio.h>
31 #include <subdev/bios/init.h>
32 #include <subdev/bios/ramcfg.h>
33
34 #include <subdev/devinit.h>
35 #include <subdev/gpio.h>
36 #include <subdev/i2c.h>
37 #include <subdev/vga.h>
38
39 #include <linux/kernel.h>
40
41 #define bioslog(lvl, fmt, args...) do { \
42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
45 } while(0)
46 #define cont(fmt, args...) do { \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
48 printk(fmt, ##args); \
49 } while(0)
50 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
51 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
52 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
53
54 /******************************************************************************
55 * init parser control flow helpers
56 *****************************************************************************/
57
58 static inline bool
59 init_exec(struct nvbios_init *init)
60 {
61 return (init->execute == 1) || ((init->execute & 5) == 5);
62 }
63
64 static inline void
65 init_exec_set(struct nvbios_init *init, bool exec)
66 {
67 if (exec) init->execute &= 0xfd;
68 else init->execute |= 0x02;
69 }
70
71 static inline void
72 init_exec_inv(struct nvbios_init *init)
73 {
74 init->execute ^= 0x02;
75 }
76
77 static inline void
78 init_exec_force(struct nvbios_init *init, bool exec)
79 {
80 if (exec) init->execute |= 0x04;
81 else init->execute &= 0xfb;
82 }
83
84 /******************************************************************************
85 * init parser wrappers for normal register/i2c/whatever accessors
86 *****************************************************************************/
87
88 static inline int
89 init_or(struct nvbios_init *init)
90 {
91 if (init_exec(init)) {
92 if (init->or >= 0)
93 return init->or;
94 error("script needs OR!!\n");
95 }
96 return 0;
97 }
98
99 static inline int
100 init_link(struct nvbios_init *init)
101 {
102 if (init_exec(init)) {
103 if (init->link)
104 return init->link == 2;
105 error("script needs OR link\n");
106 }
107 return 0;
108 }
109
110 static inline int
111 init_head(struct nvbios_init *init)
112 {
113 if (init_exec(init)) {
114 if (init->head >= 0)
115 return init->head;
116 error("script needs head\n");
117 }
118 return 0;
119 }
120
121 static u8
122 init_conn(struct nvbios_init *init)
123 {
124 struct nvkm_bios *bios = init->subdev->device->bios;
125 struct nvbios_connE connE;
126 u8 ver, hdr;
127 u32 conn;
128
129 if (init_exec(init)) {
130 if (init->outp) {
131 conn = init->outp->connector;
132 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
133 if (conn)
134 return connE.type;
135 }
136
137 error("script needs connector type\n");
138 }
139
140 return 0xff;
141 }
142
143 static inline u32
144 init_nvreg(struct nvbios_init *init, u32 reg)
145 {
146 struct nvkm_devinit *devinit = init->subdev->device->devinit;
147
148 /* C51 (at least) sometimes has the lower bits set which the VBIOS
149 * interprets to mean that access needs to go through certain IO
150 * ports instead. The NVIDIA binary driver has been seen to access
151 * these through the NV register address, so lets assume we can
152 * do the same
153 */
154 reg &= ~0x00000003;
155
156 /* GF8+ display scripts need register addresses mangled a bit to
157 * select a specific CRTC/OR
158 */
159 if (init->subdev->device->card_type >= NV_50) {
160 if (reg & 0x80000000) {
161 reg += init_head(init) * 0x800;
162 reg &= ~0x80000000;
163 }
164
165 if (reg & 0x40000000) {
166 reg += init_or(init) * 0x800;
167 reg &= ~0x40000000;
168 if (reg & 0x20000000) {
169 reg += init_link(init) * 0x80;
170 reg &= ~0x20000000;
171 }
172 }
173 }
174
175 if (reg & ~0x00fffffc)
176 warn("unknown bits in register 0x%08x\n", reg);
177
178 return nvkm_devinit_mmio(devinit, reg);
179 }
180
181 static u32
182 init_rd32(struct nvbios_init *init, u32 reg)
183 {
184 struct nvkm_device *device = init->subdev->device;
185 reg = init_nvreg(init, reg);
186 if (reg != ~0 && init_exec(init))
187 return nvkm_rd32(device, reg);
188 return 0x00000000;
189 }
190
191 static void
192 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
193 {
194 struct nvkm_device *device = init->subdev->device;
195 reg = init_nvreg(init, reg);
196 if (reg != ~0 && init_exec(init))
197 nvkm_wr32(device, reg, val);
198 }
199
200 static u32
201 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
202 {
203 struct nvkm_device *device = init->subdev->device;
204 reg = init_nvreg(init, reg);
205 if (reg != ~0 && init_exec(init)) {
206 u32 tmp = nvkm_rd32(device, reg);
207 nvkm_wr32(device, reg, (tmp & ~mask) | val);
208 return tmp;
209 }
210 return 0x00000000;
211 }
212
213 static u8
214 init_rdport(struct nvbios_init *init, u16 port)
215 {
216 if (init_exec(init))
217 return nvkm_rdport(init->subdev->device, init->head, port);
218 return 0x00;
219 }
220
221 static void
222 init_wrport(struct nvbios_init *init, u16 port, u8 value)
223 {
224 if (init_exec(init))
225 nvkm_wrport(init->subdev->device, init->head, port, value);
226 }
227
228 static u8
229 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
230 {
231 struct nvkm_subdev *subdev = init->subdev;
232 if (init_exec(init)) {
233 int head = init->head < 0 ? 0 : init->head;
234 return nvkm_rdvgai(subdev->device, head, port, index);
235 }
236 return 0x00;
237 }
238
239 static void
240 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
241 {
242 struct nvkm_device *device = init->subdev->device;
243
244 /* force head 0 for updates to cr44, it only exists on first head */
245 if (device->card_type < NV_50) {
246 if (port == 0x03d4 && index == 0x44)
247 init->head = 0;
248 }
249
250 if (init_exec(init)) {
251 int head = init->head < 0 ? 0 : init->head;
252 nvkm_wrvgai(device, head, port, index, value);
253 }
254
255 /* select head 1 if cr44 write selected it */
256 if (device->card_type < NV_50) {
257 if (port == 0x03d4 && index == 0x44 && value == 3)
258 init->head = 1;
259 }
260 }
261
262 static struct i2c_adapter *
263 init_i2c(struct nvbios_init *init, int index)
264 {
265 struct nvkm_i2c *i2c = init->subdev->device->i2c;
266 struct nvkm_i2c_bus *bus;
267
268 if (index == 0xff) {
269 index = NVKM_I2C_BUS_PRI;
270 if (init->outp && init->outp->i2c_upper_default)
271 index = NVKM_I2C_BUS_SEC;
272 } else
273 if (index == 0x80) {
274 index = NVKM_I2C_BUS_PRI;
275 } else
276 if (index == 0x81) {
277 index = NVKM_I2C_BUS_SEC;
278 }
279
280 bus = nvkm_i2c_bus_find(i2c, index);
281 return bus ? &bus->i2c : NULL;
282 }
283
284 static int
285 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
286 {
287 struct i2c_adapter *adap = init_i2c(init, index);
288 if (adap && init_exec(init))
289 return nvkm_rdi2cr(adap, addr, reg);
290 return -ENODEV;
291 }
292
293 static int
294 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
295 {
296 struct i2c_adapter *adap = init_i2c(init, index);
297 if (adap && init_exec(init))
298 return nvkm_wri2cr(adap, addr, reg, val);
299 return -ENODEV;
300 }
301
302 static struct nvkm_i2c_aux *
303 init_aux(struct nvbios_init *init)
304 {
305 struct nvkm_i2c *i2c = init->subdev->device->i2c;
306 if (!init->outp) {
307 if (init_exec(init))
308 error("script needs output for aux\n");
309 return NULL;
310 }
311 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index);
312 }
313
314 static u8
315 init_rdauxr(struct nvbios_init *init, u32 addr)
316 {
317 struct nvkm_i2c_aux *aux = init_aux(init);
318 u8 data;
319
320 if (aux && init_exec(init)) {
321 int ret = nvkm_rdaux(aux, addr, &data, 1);
322 if (ret == 0)
323 return data;
324 trace("auxch read failed with %d\n", ret);
325 }
326
327 return 0x00;
328 }
329
330 static int
331 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
332 {
333 struct nvkm_i2c_aux *aux = init_aux(init);
334 if (aux && init_exec(init)) {
335 int ret = nvkm_wraux(aux, addr, &data, 1);
336 if (ret)
337 trace("auxch write failed with %d\n", ret);
338 return ret;
339 }
340 return -ENODEV;
341 }
342
343 static void
344 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
345 {
346 struct nvkm_devinit *devinit = init->subdev->device->devinit;
347 if (init_exec(init)) {
348 int ret = nvkm_devinit_pll_set(devinit, id, freq);
349 if (ret)
350 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
351 }
352 }
353
354 /******************************************************************************
355 * parsing of bios structures that are required to execute init tables
356 *****************************************************************************/
357
358 static u16
359 init_table(struct nvkm_bios *bios, u16 *len)
360 {
361 struct bit_entry bit_I;
362
363 if (!bit_entry(bios, 'I', &bit_I)) {
364 *len = bit_I.length;
365 return bit_I.offset;
366 }
367
368 if (bmp_version(bios) >= 0x0510) {
369 *len = 14;
370 return bios->bmp_offset + 75;
371 }
372
373 return 0x0000;
374 }
375
376 static u16
377 init_table_(struct nvbios_init *init, u16 offset, const char *name)
378 {
379 struct nvkm_bios *bios = init->subdev->device->bios;
380 u16 len, data = init_table(bios, &len);
381 if (data) {
382 if (len >= offset + 2) {
383 data = nvbios_rd16(bios, data + offset);
384 if (data)
385 return data;
386
387 warn("%s pointer invalid\n", name);
388 return 0x0000;
389 }
390
391 warn("init data too short for %s pointer", name);
392 return 0x0000;
393 }
394
395 warn("init data not found\n");
396 return 0x0000;
397 }
398
399 #define init_script_table(b) init_table_((b), 0x00, "script table")
400 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
401 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
402 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
403 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
404 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
405 #define init_function_table(b) init_table_((b), 0x0c, "function table")
406 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
407
408 static u16
409 init_script(struct nvkm_bios *bios, int index)
410 {
411 struct nvbios_init init = { .subdev = &bios->subdev };
412 u16 bmp_ver = bmp_version(bios), data;
413
414 if (bmp_ver && bmp_ver < 0x0510) {
415 if (index > 1 || bmp_ver < 0x0100)
416 return 0x0000;
417
418 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
419 return nvbios_rd16(bios, data + (index * 2));
420 }
421
422 data = init_script_table(&init);
423 if (data)
424 return nvbios_rd16(bios, data + (index * 2));
425
426 return 0x0000;
427 }
428
429 static u16
430 init_unknown_script(struct nvkm_bios *bios)
431 {
432 u16 len, data = init_table(bios, &len);
433 if (data && len >= 16)
434 return nvbios_rd16(bios, data + 14);
435 return 0x0000;
436 }
437
438 static u8
439 init_ram_restrict_group_count(struct nvbios_init *init)
440 {
441 return nvbios_ramcfg_count(init->subdev->device->bios);
442 }
443
444 static u8
445 init_ram_restrict(struct nvbios_init *init)
446 {
447 /* This appears to be the behaviour of the VBIOS parser, and *is*
448 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
449 * avoid fucking up the memory controller (somehow) by reading it
450 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
451 *
452 * Preserving the non-caching behaviour on earlier chipsets just
453 * in case *not* re-reading the strap causes similar breakage.
454 */
455 if (!init->ramcfg || init->subdev->device->bios->version.major < 0x70)
456 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
457 return (init->ramcfg & 0x7fffffff);
458 }
459
460 static u8
461 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
462 {
463 struct nvkm_bios *bios = init->subdev->device->bios;
464 u16 table = init_xlat_table(init);
465 if (table) {
466 u16 data = nvbios_rd16(bios, table + (index * 2));
467 if (data)
468 return nvbios_rd08(bios, data + offset);
469 warn("xlat table pointer %d invalid\n", index);
470 }
471 return 0x00;
472 }
473
474 /******************************************************************************
475 * utility functions used by various init opcode handlers
476 *****************************************************************************/
477
478 static bool
479 init_condition_met(struct nvbios_init *init, u8 cond)
480 {
481 struct nvkm_bios *bios = init->subdev->device->bios;
482 u16 table = init_condition_table(init);
483 if (table) {
484 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0);
485 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4);
486 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8);
487 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
488 cond, reg, msk, val);
489 return (init_rd32(init, reg) & msk) == val;
490 }
491 return false;
492 }
493
494 static bool
495 init_io_condition_met(struct nvbios_init *init, u8 cond)
496 {
497 struct nvkm_bios *bios = init->subdev->device->bios;
498 u16 table = init_io_condition_table(init);
499 if (table) {
500 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0);
501 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2);
502 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3);
503 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4);
504 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
505 cond, port, index, mask, value);
506 return (init_rdvgai(init, port, index) & mask) == value;
507 }
508 return false;
509 }
510
511 static bool
512 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
513 {
514 struct nvkm_bios *bios = init->subdev->device->bios;
515 u16 table = init_io_flag_condition_table(init);
516 if (table) {
517 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0);
518 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2);
519 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3);
520 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4);
521 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5);
522 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7);
523 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8);
524 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
525 return (nvbios_rd08(bios, data + ioval) & dmask) == value;
526 }
527 return false;
528 }
529
530 static inline u32
531 init_shift(u32 data, u8 shift)
532 {
533 if (shift < 0x80)
534 return data >> shift;
535 return data << (0x100 - shift);
536 }
537
538 static u32
539 init_tmds_reg(struct nvbios_init *init, u8 tmds)
540 {
541 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
542 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
543 * CR58 for CR57 = 0 to index a table of offsets to the basic
544 * 0x6808b0 address.
545 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
546 * CR58 for CR57 = 0 to index a table of offsets to the basic
547 * 0x6808b0 address, and then flip the offset by 8.
548 */
549 const int pramdac_offset[13] = {
550 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
551 const u32 pramdac_table[4] = {
552 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
553
554 if (tmds >= 0x80) {
555 if (init->outp) {
556 u32 dacoffset = pramdac_offset[init->outp->or];
557 if (tmds == 0x81)
558 dacoffset ^= 8;
559 return 0x6808b0 + dacoffset;
560 }
561
562 if (init_exec(init))
563 error("tmds opcodes need dcb\n");
564 } else {
565 if (tmds < ARRAY_SIZE(pramdac_table))
566 return pramdac_table[tmds];
567
568 error("tmds selector 0x%02x unknown\n", tmds);
569 }
570
571 return 0;
572 }
573
574 /******************************************************************************
575 * init opcode handlers
576 *****************************************************************************/
577
578 /**
579 * init_reserved - stub for various unknown/unused single-byte opcodes
580 *
581 */
582 static void
583 init_reserved(struct nvbios_init *init)
584 {
585 struct nvkm_bios *bios = init->subdev->device->bios;
586 u8 opcode = nvbios_rd08(bios, init->offset);
587 u8 length, i;
588
589 switch (opcode) {
590 case 0xaa:
591 length = 4;
592 break;
593 default:
594 length = 1;
595 break;
596 }
597
598 trace("RESERVED 0x%02x\t", opcode);
599 for (i = 1; i < length; i++)
600 cont(" 0x%02x", nvbios_rd08(bios, init->offset + i));
601 cont("\n");
602 init->offset += length;
603 }
604
605 /**
606 * INIT_DONE - opcode 0x71
607 *
608 */
609 static void
610 init_done(struct nvbios_init *init)
611 {
612 trace("DONE\n");
613 init->offset = 0x0000;
614 }
615
616 /**
617 * INIT_IO_RESTRICT_PROG - opcode 0x32
618 *
619 */
620 static void
621 init_io_restrict_prog(struct nvbios_init *init)
622 {
623 struct nvkm_bios *bios = init->subdev->device->bios;
624 u16 port = nvbios_rd16(bios, init->offset + 1);
625 u8 index = nvbios_rd08(bios, init->offset + 3);
626 u8 mask = nvbios_rd08(bios, init->offset + 4);
627 u8 shift = nvbios_rd08(bios, init->offset + 5);
628 u8 count = nvbios_rd08(bios, init->offset + 6);
629 u32 reg = nvbios_rd32(bios, init->offset + 7);
630 u8 conf, i;
631
632 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
633 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
634 reg, port, index, mask, shift);
635 init->offset += 11;
636
637 conf = (init_rdvgai(init, port, index) & mask) >> shift;
638 for (i = 0; i < count; i++) {
639 u32 data = nvbios_rd32(bios, init->offset);
640
641 if (i == conf) {
642 trace("\t0x%08x *\n", data);
643 init_wr32(init, reg, data);
644 } else {
645 trace("\t0x%08x\n", data);
646 }
647
648 init->offset += 4;
649 }
650 trace("}]\n");
651 }
652
653 /**
654 * INIT_REPEAT - opcode 0x33
655 *
656 */
657 static void
658 init_repeat(struct nvbios_init *init)
659 {
660 struct nvkm_bios *bios = init->subdev->device->bios;
661 u8 count = nvbios_rd08(bios, init->offset + 1);
662 u16 repeat = init->repeat;
663
664 trace("REPEAT\t0x%02x\n", count);
665 init->offset += 2;
666
667 init->repeat = init->offset;
668 init->repend = init->offset;
669 while (count--) {
670 init->offset = init->repeat;
671 nvbios_exec(init);
672 if (count)
673 trace("REPEAT\t0x%02x\n", count);
674 }
675 init->offset = init->repend;
676 init->repeat = repeat;
677 }
678
679 /**
680 * INIT_IO_RESTRICT_PLL - opcode 0x34
681 *
682 */
683 static void
684 init_io_restrict_pll(struct nvbios_init *init)
685 {
686 struct nvkm_bios *bios = init->subdev->device->bios;
687 u16 port = nvbios_rd16(bios, init->offset + 1);
688 u8 index = nvbios_rd08(bios, init->offset + 3);
689 u8 mask = nvbios_rd08(bios, init->offset + 4);
690 u8 shift = nvbios_rd08(bios, init->offset + 5);
691 s8 iofc = nvbios_rd08(bios, init->offset + 6);
692 u8 count = nvbios_rd08(bios, init->offset + 7);
693 u32 reg = nvbios_rd32(bios, init->offset + 8);
694 u8 conf, i;
695
696 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
697 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
698 reg, port, index, mask, shift, iofc);
699 init->offset += 12;
700
701 conf = (init_rdvgai(init, port, index) & mask) >> shift;
702 for (i = 0; i < count; i++) {
703 u32 freq = nvbios_rd16(bios, init->offset) * 10;
704
705 if (i == conf) {
706 trace("\t%dkHz *\n", freq);
707 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
708 freq *= 2;
709 init_prog_pll(init, reg, freq);
710 } else {
711 trace("\t%dkHz\n", freq);
712 }
713
714 init->offset += 2;
715 }
716 trace("}]\n");
717 }
718
719 /**
720 * INIT_END_REPEAT - opcode 0x36
721 *
722 */
723 static void
724 init_end_repeat(struct nvbios_init *init)
725 {
726 trace("END_REPEAT\n");
727 init->offset += 1;
728
729 if (init->repeat) {
730 init->repend = init->offset;
731 init->offset = 0;
732 }
733 }
734
735 /**
736 * INIT_COPY - opcode 0x37
737 *
738 */
739 static void
740 init_copy(struct nvbios_init *init)
741 {
742 struct nvkm_bios *bios = init->subdev->device->bios;
743 u32 reg = nvbios_rd32(bios, init->offset + 1);
744 u8 shift = nvbios_rd08(bios, init->offset + 5);
745 u8 smask = nvbios_rd08(bios, init->offset + 6);
746 u16 port = nvbios_rd16(bios, init->offset + 7);
747 u8 index = nvbios_rd08(bios, init->offset + 9);
748 u8 mask = nvbios_rd08(bios, init->offset + 10);
749 u8 data;
750
751 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
752 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
753 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
754 (shift & 0x80) ? (0x100 - shift) : shift, smask);
755 init->offset += 11;
756
757 data = init_rdvgai(init, port, index) & mask;
758 data |= init_shift(init_rd32(init, reg), shift) & smask;
759 init_wrvgai(init, port, index, data);
760 }
761
762 /**
763 * INIT_NOT - opcode 0x38
764 *
765 */
766 static void
767 init_not(struct nvbios_init *init)
768 {
769 trace("NOT\n");
770 init->offset += 1;
771 init_exec_inv(init);
772 }
773
774 /**
775 * INIT_IO_FLAG_CONDITION - opcode 0x39
776 *
777 */
778 static void
779 init_io_flag_condition(struct nvbios_init *init)
780 {
781 struct nvkm_bios *bios = init->subdev->device->bios;
782 u8 cond = nvbios_rd08(bios, init->offset + 1);
783
784 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
785 init->offset += 2;
786
787 if (!init_io_flag_condition_met(init, cond))
788 init_exec_set(init, false);
789 }
790
791 /**
792 * INIT_GENERIC_CONDITION - opcode 0x3a
793 *
794 */
795 static void
796 init_generic_condition(struct nvbios_init *init)
797 {
798 struct nvkm_bios *bios = init->subdev->device->bios;
799 struct nvbios_dpout info;
800 u8 cond = nvbios_rd08(bios, init->offset + 1);
801 u8 size = nvbios_rd08(bios, init->offset + 2);
802 u8 ver, hdr, cnt, len;
803 u16 data;
804
805 trace("GENERIC_CONDITION\t0x%02x 0x%02x\n", cond, size);
806 init->offset += 3;
807
808 switch (cond) {
809 case 0:
810 if (init_conn(init) != DCB_CONNECTOR_eDP)
811 init_exec_set(init, false);
812 break;
813 case 1:
814 case 2:
815 if ( init->outp &&
816 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
817 (init->outp->or << 0) |
818 (init->outp->sorconf.link << 6),
819 &ver, &hdr, &cnt, &len, &info)))
820 {
821 if (!(info.flags & cond))
822 init_exec_set(init, false);
823 break;
824 }
825
826 if (init_exec(init))
827 warn("script needs dp output table data\n");
828 break;
829 case 5:
830 if (!(init_rdauxr(init, 0x0d) & 1))
831 init_exec_set(init, false);
832 break;
833 default:
834 warn("INIT_GENERIC_CONDITON: unknown 0x%02x\n", cond);
835 init->offset += size;
836 break;
837 }
838 }
839
840 /**
841 * INIT_IO_MASK_OR - opcode 0x3b
842 *
843 */
844 static void
845 init_io_mask_or(struct nvbios_init *init)
846 {
847 struct nvkm_bios *bios = init->subdev->device->bios;
848 u8 index = nvbios_rd08(bios, init->offset + 1);
849 u8 or = init_or(init);
850 u8 data;
851
852 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
853 init->offset += 2;
854
855 data = init_rdvgai(init, 0x03d4, index);
856 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
857 }
858
859 /**
860 * INIT_IO_OR - opcode 0x3c
861 *
862 */
863 static void
864 init_io_or(struct nvbios_init *init)
865 {
866 struct nvkm_bios *bios = init->subdev->device->bios;
867 u8 index = nvbios_rd08(bios, init->offset + 1);
868 u8 or = init_or(init);
869 u8 data;
870
871 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
872 init->offset += 2;
873
874 data = init_rdvgai(init, 0x03d4, index);
875 init_wrvgai(init, 0x03d4, index, data | (1 << or));
876 }
877
878 /**
879 * INIT_ANDN_REG - opcode 0x47
880 *
881 */
882 static void
883 init_andn_reg(struct nvbios_init *init)
884 {
885 struct nvkm_bios *bios = init->subdev->device->bios;
886 u32 reg = nvbios_rd32(bios, init->offset + 1);
887 u32 mask = nvbios_rd32(bios, init->offset + 5);
888
889 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
890 init->offset += 9;
891
892 init_mask(init, reg, mask, 0);
893 }
894
895 /**
896 * INIT_OR_REG - opcode 0x48
897 *
898 */
899 static void
900 init_or_reg(struct nvbios_init *init)
901 {
902 struct nvkm_bios *bios = init->subdev->device->bios;
903 u32 reg = nvbios_rd32(bios, init->offset + 1);
904 u32 mask = nvbios_rd32(bios, init->offset + 5);
905
906 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
907 init->offset += 9;
908
909 init_mask(init, reg, 0, mask);
910 }
911
912 /**
913 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
914 *
915 */
916 static void
917 init_idx_addr_latched(struct nvbios_init *init)
918 {
919 struct nvkm_bios *bios = init->subdev->device->bios;
920 u32 creg = nvbios_rd32(bios, init->offset + 1);
921 u32 dreg = nvbios_rd32(bios, init->offset + 5);
922 u32 mask = nvbios_rd32(bios, init->offset + 9);
923 u32 data = nvbios_rd32(bios, init->offset + 13);
924 u8 count = nvbios_rd08(bios, init->offset + 17);
925
926 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
927 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
928 init->offset += 18;
929
930 while (count--) {
931 u8 iaddr = nvbios_rd08(bios, init->offset + 0);
932 u8 idata = nvbios_rd08(bios, init->offset + 1);
933
934 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
935 init->offset += 2;
936
937 init_wr32(init, dreg, idata);
938 init_mask(init, creg, ~mask, data | iaddr);
939 }
940 }
941
942 /**
943 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
944 *
945 */
946 static void
947 init_io_restrict_pll2(struct nvbios_init *init)
948 {
949 struct nvkm_bios *bios = init->subdev->device->bios;
950 u16 port = nvbios_rd16(bios, init->offset + 1);
951 u8 index = nvbios_rd08(bios, init->offset + 3);
952 u8 mask = nvbios_rd08(bios, init->offset + 4);
953 u8 shift = nvbios_rd08(bios, init->offset + 5);
954 u8 count = nvbios_rd08(bios, init->offset + 6);
955 u32 reg = nvbios_rd32(bios, init->offset + 7);
956 u8 conf, i;
957
958 trace("IO_RESTRICT_PLL2\t"
959 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
960 reg, port, index, mask, shift);
961 init->offset += 11;
962
963 conf = (init_rdvgai(init, port, index) & mask) >> shift;
964 for (i = 0; i < count; i++) {
965 u32 freq = nvbios_rd32(bios, init->offset);
966 if (i == conf) {
967 trace("\t%dkHz *\n", freq);
968 init_prog_pll(init, reg, freq);
969 } else {
970 trace("\t%dkHz\n", freq);
971 }
972 init->offset += 4;
973 }
974 trace("}]\n");
975 }
976
977 /**
978 * INIT_PLL2 - opcode 0x4b
979 *
980 */
981 static void
982 init_pll2(struct nvbios_init *init)
983 {
984 struct nvkm_bios *bios = init->subdev->device->bios;
985 u32 reg = nvbios_rd32(bios, init->offset + 1);
986 u32 freq = nvbios_rd32(bios, init->offset + 5);
987
988 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
989 init->offset += 9;
990
991 init_prog_pll(init, reg, freq);
992 }
993
994 /**
995 * INIT_I2C_BYTE - opcode 0x4c
996 *
997 */
998 static void
999 init_i2c_byte(struct nvbios_init *init)
1000 {
1001 struct nvkm_bios *bios = init->subdev->device->bios;
1002 u8 index = nvbios_rd08(bios, init->offset + 1);
1003 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1004 u8 count = nvbios_rd08(bios, init->offset + 3);
1005
1006 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1007 init->offset += 4;
1008
1009 while (count--) {
1010 u8 reg = nvbios_rd08(bios, init->offset + 0);
1011 u8 mask = nvbios_rd08(bios, init->offset + 1);
1012 u8 data = nvbios_rd08(bios, init->offset + 2);
1013 int val;
1014
1015 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1016 init->offset += 3;
1017
1018 val = init_rdi2cr(init, index, addr, reg);
1019 if (val < 0)
1020 continue;
1021 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1022 }
1023 }
1024
1025 /**
1026 * INIT_ZM_I2C_BYTE - opcode 0x4d
1027 *
1028 */
1029 static void
1030 init_zm_i2c_byte(struct nvbios_init *init)
1031 {
1032 struct nvkm_bios *bios = init->subdev->device->bios;
1033 u8 index = nvbios_rd08(bios, init->offset + 1);
1034 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1035 u8 count = nvbios_rd08(bios, init->offset + 3);
1036
1037 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1038 init->offset += 4;
1039
1040 while (count--) {
1041 u8 reg = nvbios_rd08(bios, init->offset + 0);
1042 u8 data = nvbios_rd08(bios, init->offset + 1);
1043
1044 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1045 init->offset += 2;
1046
1047 init_wri2cr(init, index, addr, reg, data);
1048 }
1049 }
1050
1051 /**
1052 * INIT_ZM_I2C - opcode 0x4e
1053 *
1054 */
1055 static void
1056 init_zm_i2c(struct nvbios_init *init)
1057 {
1058 struct nvkm_bios *bios = init->subdev->device->bios;
1059 u8 index = nvbios_rd08(bios, init->offset + 1);
1060 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
1061 u8 count = nvbios_rd08(bios, init->offset + 3);
1062 u8 data[256], i;
1063
1064 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1065 init->offset += 4;
1066
1067 for (i = 0; i < count; i++) {
1068 data[i] = nvbios_rd08(bios, init->offset);
1069 trace("\t0x%02x\n", data[i]);
1070 init->offset++;
1071 }
1072
1073 if (init_exec(init)) {
1074 struct i2c_adapter *adap = init_i2c(init, index);
1075 struct i2c_msg msg = {
1076 .addr = addr, .flags = 0, .len = count, .buf = data,
1077 };
1078 int ret;
1079
1080 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1)
1081 warn("i2c wr failed, %d\n", ret);
1082 }
1083 }
1084
1085 /**
1086 * INIT_TMDS - opcode 0x4f
1087 *
1088 */
1089 static void
1090 init_tmds(struct nvbios_init *init)
1091 {
1092 struct nvkm_bios *bios = init->subdev->device->bios;
1093 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1094 u8 addr = nvbios_rd08(bios, init->offset + 2);
1095 u8 mask = nvbios_rd08(bios, init->offset + 3);
1096 u8 data = nvbios_rd08(bios, init->offset + 4);
1097 u32 reg = init_tmds_reg(init, tmds);
1098
1099 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1100 tmds, addr, mask, data);
1101 init->offset += 5;
1102
1103 if (reg == 0)
1104 return;
1105
1106 init_wr32(init, reg + 0, addr | 0x00010000);
1107 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1108 init_wr32(init, reg + 0, addr);
1109 }
1110
1111 /**
1112 * INIT_ZM_TMDS_GROUP - opcode 0x50
1113 *
1114 */
1115 static void
1116 init_zm_tmds_group(struct nvbios_init *init)
1117 {
1118 struct nvkm_bios *bios = init->subdev->device->bios;
1119 u8 tmds = nvbios_rd08(bios, init->offset + 1);
1120 u8 count = nvbios_rd08(bios, init->offset + 2);
1121 u32 reg = init_tmds_reg(init, tmds);
1122
1123 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1124 init->offset += 3;
1125
1126 while (count--) {
1127 u8 addr = nvbios_rd08(bios, init->offset + 0);
1128 u8 data = nvbios_rd08(bios, init->offset + 1);
1129
1130 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1131 init->offset += 2;
1132
1133 init_wr32(init, reg + 4, data);
1134 init_wr32(init, reg + 0, addr);
1135 }
1136 }
1137
1138 /**
1139 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1140 *
1141 */
1142 static void
1143 init_cr_idx_adr_latch(struct nvbios_init *init)
1144 {
1145 struct nvkm_bios *bios = init->subdev->device->bios;
1146 u8 addr0 = nvbios_rd08(bios, init->offset + 1);
1147 u8 addr1 = nvbios_rd08(bios, init->offset + 2);
1148 u8 base = nvbios_rd08(bios, init->offset + 3);
1149 u8 count = nvbios_rd08(bios, init->offset + 4);
1150 u8 save0;
1151
1152 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1153 init->offset += 5;
1154
1155 save0 = init_rdvgai(init, 0x03d4, addr0);
1156 while (count--) {
1157 u8 data = nvbios_rd08(bios, init->offset);
1158
1159 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1160 init->offset += 1;
1161
1162 init_wrvgai(init, 0x03d4, addr0, base++);
1163 init_wrvgai(init, 0x03d4, addr1, data);
1164 }
1165 init_wrvgai(init, 0x03d4, addr0, save0);
1166 }
1167
1168 /**
1169 * INIT_CR - opcode 0x52
1170 *
1171 */
1172 static void
1173 init_cr(struct nvbios_init *init)
1174 {
1175 struct nvkm_bios *bios = init->subdev->device->bios;
1176 u8 addr = nvbios_rd08(bios, init->offset + 1);
1177 u8 mask = nvbios_rd08(bios, init->offset + 2);
1178 u8 data = nvbios_rd08(bios, init->offset + 3);
1179 u8 val;
1180
1181 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1182 init->offset += 4;
1183
1184 val = init_rdvgai(init, 0x03d4, addr) & mask;
1185 init_wrvgai(init, 0x03d4, addr, val | data);
1186 }
1187
1188 /**
1189 * INIT_ZM_CR - opcode 0x53
1190 *
1191 */
1192 static void
1193 init_zm_cr(struct nvbios_init *init)
1194 {
1195 struct nvkm_bios *bios = init->subdev->device->bios;
1196 u8 addr = nvbios_rd08(bios, init->offset + 1);
1197 u8 data = nvbios_rd08(bios, init->offset + 2);
1198
1199 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1200 init->offset += 3;
1201
1202 init_wrvgai(init, 0x03d4, addr, data);
1203 }
1204
1205 /**
1206 * INIT_ZM_CR_GROUP - opcode 0x54
1207 *
1208 */
1209 static void
1210 init_zm_cr_group(struct nvbios_init *init)
1211 {
1212 struct nvkm_bios *bios = init->subdev->device->bios;
1213 u8 count = nvbios_rd08(bios, init->offset + 1);
1214
1215 trace("ZM_CR_GROUP\n");
1216 init->offset += 2;
1217
1218 while (count--) {
1219 u8 addr = nvbios_rd08(bios, init->offset + 0);
1220 u8 data = nvbios_rd08(bios, init->offset + 1);
1221
1222 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1223 init->offset += 2;
1224
1225 init_wrvgai(init, 0x03d4, addr, data);
1226 }
1227 }
1228
1229 /**
1230 * INIT_CONDITION_TIME - opcode 0x56
1231 *
1232 */
1233 static void
1234 init_condition_time(struct nvbios_init *init)
1235 {
1236 struct nvkm_bios *bios = init->subdev->device->bios;
1237 u8 cond = nvbios_rd08(bios, init->offset + 1);
1238 u8 retry = nvbios_rd08(bios, init->offset + 2);
1239 u8 wait = min((u16)retry * 50, 100);
1240
1241 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1242 init->offset += 3;
1243
1244 if (!init_exec(init))
1245 return;
1246
1247 while (wait--) {
1248 if (init_condition_met(init, cond))
1249 return;
1250 mdelay(20);
1251 }
1252
1253 init_exec_set(init, false);
1254 }
1255
1256 /**
1257 * INIT_LTIME - opcode 0x57
1258 *
1259 */
1260 static void
1261 init_ltime(struct nvbios_init *init)
1262 {
1263 struct nvkm_bios *bios = init->subdev->device->bios;
1264 u16 msec = nvbios_rd16(bios, init->offset + 1);
1265
1266 trace("LTIME\t0x%04x\n", msec);
1267 init->offset += 3;
1268
1269 if (init_exec(init))
1270 mdelay(msec);
1271 }
1272
1273 /**
1274 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1275 *
1276 */
1277 static void
1278 init_zm_reg_sequence(struct nvbios_init *init)
1279 {
1280 struct nvkm_bios *bios = init->subdev->device->bios;
1281 u32 base = nvbios_rd32(bios, init->offset + 1);
1282 u8 count = nvbios_rd08(bios, init->offset + 5);
1283
1284 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1285 init->offset += 6;
1286
1287 while (count--) {
1288 u32 data = nvbios_rd32(bios, init->offset);
1289
1290 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1291 init->offset += 4;
1292
1293 init_wr32(init, base, data);
1294 base += 4;
1295 }
1296 }
1297
1298 /**
1299 * INIT_PLL_INDIRECT - opcode 0x59
1300 *
1301 */
1302 static void
1303 init_pll_indirect(struct nvbios_init *init)
1304 {
1305 struct nvkm_bios *bios = init->subdev->device->bios;
1306 u32 reg = nvbios_rd32(bios, init->offset + 1);
1307 u16 addr = nvbios_rd16(bios, init->offset + 5);
1308 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000;
1309
1310 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1311 reg, addr, freq);
1312 init->offset += 7;
1313
1314 init_prog_pll(init, reg, freq);
1315 }
1316
1317 /**
1318 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1319 *
1320 */
1321 static void
1322 init_zm_reg_indirect(struct nvbios_init *init)
1323 {
1324 struct nvkm_bios *bios = init->subdev->device->bios;
1325 u32 reg = nvbios_rd32(bios, init->offset + 1);
1326 u16 addr = nvbios_rd16(bios, init->offset + 5);
1327 u32 data = nvbios_rd32(bios, addr);
1328
1329 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1330 reg, addr, data);
1331 init->offset += 7;
1332
1333 init_wr32(init, addr, data);
1334 }
1335
1336 /**
1337 * INIT_SUB_DIRECT - opcode 0x5b
1338 *
1339 */
1340 static void
1341 init_sub_direct(struct nvbios_init *init)
1342 {
1343 struct nvkm_bios *bios = init->subdev->device->bios;
1344 u16 addr = nvbios_rd16(bios, init->offset + 1);
1345 u16 save;
1346
1347 trace("SUB_DIRECT\t0x%04x\n", addr);
1348
1349 if (init_exec(init)) {
1350 save = init->offset;
1351 init->offset = addr;
1352 if (nvbios_exec(init)) {
1353 error("error parsing sub-table\n");
1354 return;
1355 }
1356 init->offset = save;
1357 }
1358
1359 init->offset += 3;
1360 }
1361
1362 /**
1363 * INIT_JUMP - opcode 0x5c
1364 *
1365 */
1366 static void
1367 init_jump(struct nvbios_init *init)
1368 {
1369 struct nvkm_bios *bios = init->subdev->device->bios;
1370 u16 offset = nvbios_rd16(bios, init->offset + 1);
1371
1372 trace("JUMP\t0x%04x\n", offset);
1373
1374 if (init_exec(init))
1375 init->offset = offset;
1376 else
1377 init->offset += 3;
1378 }
1379
1380 /**
1381 * INIT_I2C_IF - opcode 0x5e
1382 *
1383 */
1384 static void
1385 init_i2c_if(struct nvbios_init *init)
1386 {
1387 struct nvkm_bios *bios = init->subdev->device->bios;
1388 u8 index = nvbios_rd08(bios, init->offset + 1);
1389 u8 addr = nvbios_rd08(bios, init->offset + 2);
1390 u8 reg = nvbios_rd08(bios, init->offset + 3);
1391 u8 mask = nvbios_rd08(bios, init->offset + 4);
1392 u8 data = nvbios_rd08(bios, init->offset + 5);
1393 u8 value;
1394
1395 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1396 index, addr, reg, mask, data);
1397 init->offset += 6;
1398 init_exec_force(init, true);
1399
1400 value = init_rdi2cr(init, index, addr, reg);
1401 if ((value & mask) != data)
1402 init_exec_set(init, false);
1403
1404 init_exec_force(init, false);
1405 }
1406
1407 /**
1408 * INIT_COPY_NV_REG - opcode 0x5f
1409 *
1410 */
1411 static void
1412 init_copy_nv_reg(struct nvbios_init *init)
1413 {
1414 struct nvkm_bios *bios = init->subdev->device->bios;
1415 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1416 u8 shift = nvbios_rd08(bios, init->offset + 5);
1417 u32 smask = nvbios_rd32(bios, init->offset + 6);
1418 u32 sxor = nvbios_rd32(bios, init->offset + 10);
1419 u32 dreg = nvbios_rd32(bios, init->offset + 14);
1420 u32 dmask = nvbios_rd32(bios, init->offset + 18);
1421 u32 data;
1422
1423 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1424 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1425 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1426 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1427 init->offset += 22;
1428
1429 data = init_shift(init_rd32(init, sreg), shift);
1430 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1431 }
1432
1433 /**
1434 * INIT_ZM_INDEX_IO - opcode 0x62
1435 *
1436 */
1437 static void
1438 init_zm_index_io(struct nvbios_init *init)
1439 {
1440 struct nvkm_bios *bios = init->subdev->device->bios;
1441 u16 port = nvbios_rd16(bios, init->offset + 1);
1442 u8 index = nvbios_rd08(bios, init->offset + 3);
1443 u8 data = nvbios_rd08(bios, init->offset + 4);
1444
1445 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1446 init->offset += 5;
1447
1448 init_wrvgai(init, port, index, data);
1449 }
1450
1451 /**
1452 * INIT_COMPUTE_MEM - opcode 0x63
1453 *
1454 */
1455 static void
1456 init_compute_mem(struct nvbios_init *init)
1457 {
1458 struct nvkm_devinit *devinit = init->subdev->device->devinit;
1459
1460 trace("COMPUTE_MEM\n");
1461 init->offset += 1;
1462
1463 init_exec_force(init, true);
1464 if (init_exec(init))
1465 nvkm_devinit_meminit(devinit);
1466 init_exec_force(init, false);
1467 }
1468
1469 /**
1470 * INIT_RESET - opcode 0x65
1471 *
1472 */
1473 static void
1474 init_reset(struct nvbios_init *init)
1475 {
1476 struct nvkm_bios *bios = init->subdev->device->bios;
1477 u32 reg = nvbios_rd32(bios, init->offset + 1);
1478 u32 data1 = nvbios_rd32(bios, init->offset + 5);
1479 u32 data2 = nvbios_rd32(bios, init->offset + 9);
1480 u32 savepci19;
1481
1482 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1483 init->offset += 13;
1484 init_exec_force(init, true);
1485
1486 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1487 init_wr32(init, reg, data1);
1488 udelay(10);
1489 init_wr32(init, reg, data2);
1490 init_wr32(init, 0x00184c, savepci19);
1491 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1492
1493 init_exec_force(init, false);
1494 }
1495
1496 /**
1497 * INIT_CONFIGURE_MEM - opcode 0x66
1498 *
1499 */
1500 static u16
1501 init_configure_mem_clk(struct nvbios_init *init)
1502 {
1503 u16 mdata = bmp_mem_init_table(init->subdev->device->bios);
1504 if (mdata)
1505 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1506 return mdata;
1507 }
1508
1509 static void
1510 init_configure_mem(struct nvbios_init *init)
1511 {
1512 struct nvkm_bios *bios = init->subdev->device->bios;
1513 u16 mdata, sdata;
1514 u32 addr, data;
1515
1516 trace("CONFIGURE_MEM\n");
1517 init->offset += 1;
1518
1519 if (bios->version.major > 2) {
1520 init_done(init);
1521 return;
1522 }
1523 init_exec_force(init, true);
1524
1525 mdata = init_configure_mem_clk(init);
1526 sdata = bmp_sdr_seq_table(bios);
1527 if (nvbios_rd08(bios, mdata) & 0x01)
1528 sdata = bmp_ddr_seq_table(bios);
1529 mdata += 6; /* skip to data */
1530
1531 data = init_rdvgai(init, 0x03c4, 0x01);
1532 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1533
1534 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) {
1535 switch (addr) {
1536 case 0x10021c: /* CKE_NORMAL */
1537 case 0x1002d0: /* CMD_REFRESH */
1538 case 0x1002d4: /* CMD_PRECHARGE */
1539 data = 0x00000001;
1540 break;
1541 default:
1542 data = nvbios_rd32(bios, mdata);
1543 mdata += 4;
1544 if (data == 0xffffffff)
1545 continue;
1546 break;
1547 }
1548
1549 init_wr32(init, addr, data);
1550 }
1551
1552 init_exec_force(init, false);
1553 }
1554
1555 /**
1556 * INIT_CONFIGURE_CLK - opcode 0x67
1557 *
1558 */
1559 static void
1560 init_configure_clk(struct nvbios_init *init)
1561 {
1562 struct nvkm_bios *bios = init->subdev->device->bios;
1563 u16 mdata, clock;
1564
1565 trace("CONFIGURE_CLK\n");
1566 init->offset += 1;
1567
1568 if (bios->version.major > 2) {
1569 init_done(init);
1570 return;
1571 }
1572 init_exec_force(init, true);
1573
1574 mdata = init_configure_mem_clk(init);
1575
1576 /* NVPLL */
1577 clock = nvbios_rd16(bios, mdata + 4) * 10;
1578 init_prog_pll(init, 0x680500, clock);
1579
1580 /* MPLL */
1581 clock = nvbios_rd16(bios, mdata + 2) * 10;
1582 if (nvbios_rd08(bios, mdata) & 0x01)
1583 clock *= 2;
1584 init_prog_pll(init, 0x680504, clock);
1585
1586 init_exec_force(init, false);
1587 }
1588
1589 /**
1590 * INIT_CONFIGURE_PREINIT - opcode 0x68
1591 *
1592 */
1593 static void
1594 init_configure_preinit(struct nvbios_init *init)
1595 {
1596 struct nvkm_bios *bios = init->subdev->device->bios;
1597 u32 strap;
1598
1599 trace("CONFIGURE_PREINIT\n");
1600 init->offset += 1;
1601
1602 if (bios->version.major > 2) {
1603 init_done(init);
1604 return;
1605 }
1606 init_exec_force(init, true);
1607
1608 strap = init_rd32(init, 0x101000);
1609 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1610 init_wrvgai(init, 0x03d4, 0x3c, strap);
1611
1612 init_exec_force(init, false);
1613 }
1614
1615 /**
1616 * INIT_IO - opcode 0x69
1617 *
1618 */
1619 static void
1620 init_io(struct nvbios_init *init)
1621 {
1622 struct nvkm_bios *bios = init->subdev->device->bios;
1623 u16 port = nvbios_rd16(bios, init->offset + 1);
1624 u8 mask = nvbios_rd16(bios, init->offset + 3);
1625 u8 data = nvbios_rd16(bios, init->offset + 4);
1626 u8 value;
1627
1628 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1629 init->offset += 5;
1630
1631 /* ummm.. yes.. should really figure out wtf this is and why it's
1632 * needed some day.. it's almost certainly wrong, but, it also
1633 * somehow makes things work...
1634 */
1635 if (bios->subdev.device->card_type >= NV_50 &&
1636 port == 0x03c3 && data == 0x01) {
1637 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1638 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1639 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1640 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1641 mdelay(10);
1642 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1643 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1644 init_wr32(init, 0x614100, 0x00800018);
1645 init_wr32(init, 0x614900, 0x00800018);
1646 mdelay(10);
1647 init_wr32(init, 0x614100, 0x10000018);
1648 init_wr32(init, 0x614900, 0x10000018);
1649 }
1650
1651 value = init_rdport(init, port) & mask;
1652 init_wrport(init, port, data | value);
1653 }
1654
1655 /**
1656 * INIT_SUB - opcode 0x6b
1657 *
1658 */
1659 static void
1660 init_sub(struct nvbios_init *init)
1661 {
1662 struct nvkm_bios *bios = init->subdev->device->bios;
1663 u8 index = nvbios_rd08(bios, init->offset + 1);
1664 u16 addr, save;
1665
1666 trace("SUB\t0x%02x\n", index);
1667
1668 addr = init_script(bios, index);
1669 if (addr && init_exec(init)) {
1670 save = init->offset;
1671 init->offset = addr;
1672 if (nvbios_exec(init)) {
1673 error("error parsing sub-table\n");
1674 return;
1675 }
1676 init->offset = save;
1677 }
1678
1679 init->offset += 2;
1680 }
1681
1682 /**
1683 * INIT_RAM_CONDITION - opcode 0x6d
1684 *
1685 */
1686 static void
1687 init_ram_condition(struct nvbios_init *init)
1688 {
1689 struct nvkm_bios *bios = init->subdev->device->bios;
1690 u8 mask = nvbios_rd08(bios, init->offset + 1);
1691 u8 value = nvbios_rd08(bios, init->offset + 2);
1692
1693 trace("RAM_CONDITION\t"
1694 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1695 init->offset += 3;
1696
1697 if ((init_rd32(init, 0x100000) & mask) != value)
1698 init_exec_set(init, false);
1699 }
1700
1701 /**
1702 * INIT_NV_REG - opcode 0x6e
1703 *
1704 */
1705 static void
1706 init_nv_reg(struct nvbios_init *init)
1707 {
1708 struct nvkm_bios *bios = init->subdev->device->bios;
1709 u32 reg = nvbios_rd32(bios, init->offset + 1);
1710 u32 mask = nvbios_rd32(bios, init->offset + 5);
1711 u32 data = nvbios_rd32(bios, init->offset + 9);
1712
1713 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1714 init->offset += 13;
1715
1716 init_mask(init, reg, ~mask, data);
1717 }
1718
1719 /**
1720 * INIT_MACRO - opcode 0x6f
1721 *
1722 */
1723 static void
1724 init_macro(struct nvbios_init *init)
1725 {
1726 struct nvkm_bios *bios = init->subdev->device->bios;
1727 u8 macro = nvbios_rd08(bios, init->offset + 1);
1728 u16 table;
1729
1730 trace("MACRO\t0x%02x\n", macro);
1731
1732 table = init_macro_table(init);
1733 if (table) {
1734 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0);
1735 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4);
1736 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1737 init_wr32(init, addr, data);
1738 }
1739
1740 init->offset += 2;
1741 }
1742
1743 /**
1744 * INIT_RESUME - opcode 0x72
1745 *
1746 */
1747 static void
1748 init_resume(struct nvbios_init *init)
1749 {
1750 trace("RESUME\n");
1751 init->offset += 1;
1752 init_exec_set(init, true);
1753 }
1754
1755 /**
1756 * INIT_STRAP_CONDITION - opcode 0x73
1757 *
1758 */
1759 static void
1760 init_strap_condition(struct nvbios_init *init)
1761 {
1762 struct nvkm_bios *bios = init->subdev->device->bios;
1763 u32 mask = nvbios_rd32(bios, init->offset + 1);
1764 u32 value = nvbios_rd32(bios, init->offset + 5);
1765
1766 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value);
1767 init->offset += 9;
1768
1769 if ((init_rd32(init, 0x101000) & mask) != value)
1770 init_exec_set(init, false);
1771 }
1772
1773 /**
1774 * INIT_TIME - opcode 0x74
1775 *
1776 */
1777 static void
1778 init_time(struct nvbios_init *init)
1779 {
1780 struct nvkm_bios *bios = init->subdev->device->bios;
1781 u16 usec = nvbios_rd16(bios, init->offset + 1);
1782
1783 trace("TIME\t0x%04x\n", usec);
1784 init->offset += 3;
1785
1786 if (init_exec(init)) {
1787 if (usec < 1000)
1788 udelay(usec);
1789 else
1790 mdelay((usec + 900) / 1000);
1791 }
1792 }
1793
1794 /**
1795 * INIT_CONDITION - opcode 0x75
1796 *
1797 */
1798 static void
1799 init_condition(struct nvbios_init *init)
1800 {
1801 struct nvkm_bios *bios = init->subdev->device->bios;
1802 u8 cond = nvbios_rd08(bios, init->offset + 1);
1803
1804 trace("CONDITION\t0x%02x\n", cond);
1805 init->offset += 2;
1806
1807 if (!init_condition_met(init, cond))
1808 init_exec_set(init, false);
1809 }
1810
1811 /**
1812 * INIT_IO_CONDITION - opcode 0x76
1813 *
1814 */
1815 static void
1816 init_io_condition(struct nvbios_init *init)
1817 {
1818 struct nvkm_bios *bios = init->subdev->device->bios;
1819 u8 cond = nvbios_rd08(bios, init->offset + 1);
1820
1821 trace("IO_CONDITION\t0x%02x\n", cond);
1822 init->offset += 2;
1823
1824 if (!init_io_condition_met(init, cond))
1825 init_exec_set(init, false);
1826 }
1827
1828 /**
1829 * INIT_ZM_REG16 - opcode 0x77
1830 *
1831 */
1832 static void
1833 init_zm_reg16(struct nvbios_init *init)
1834 {
1835 struct nvkm_bios *bios = init->subdev->device->bios;
1836 u32 addr = nvbios_rd32(bios, init->offset + 1);
1837 u16 data = nvbios_rd16(bios, init->offset + 5);
1838
1839 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data);
1840 init->offset += 7;
1841
1842 init_wr32(init, addr, data);
1843 }
1844
1845 /**
1846 * INIT_INDEX_IO - opcode 0x78
1847 *
1848 */
1849 static void
1850 init_index_io(struct nvbios_init *init)
1851 {
1852 struct nvkm_bios *bios = init->subdev->device->bios;
1853 u16 port = nvbios_rd16(bios, init->offset + 1);
1854 u8 index = nvbios_rd16(bios, init->offset + 3);
1855 u8 mask = nvbios_rd08(bios, init->offset + 4);
1856 u8 data = nvbios_rd08(bios, init->offset + 5);
1857 u8 value;
1858
1859 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1860 port, index, mask, data);
1861 init->offset += 6;
1862
1863 value = init_rdvgai(init, port, index) & mask;
1864 init_wrvgai(init, port, index, data | value);
1865 }
1866
1867 /**
1868 * INIT_PLL - opcode 0x79
1869 *
1870 */
1871 static void
1872 init_pll(struct nvbios_init *init)
1873 {
1874 struct nvkm_bios *bios = init->subdev->device->bios;
1875 u32 reg = nvbios_rd32(bios, init->offset + 1);
1876 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10;
1877
1878 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1879 init->offset += 7;
1880
1881 init_prog_pll(init, reg, freq);
1882 }
1883
1884 /**
1885 * INIT_ZM_REG - opcode 0x7a
1886 *
1887 */
1888 static void
1889 init_zm_reg(struct nvbios_init *init)
1890 {
1891 struct nvkm_bios *bios = init->subdev->device->bios;
1892 u32 addr = nvbios_rd32(bios, init->offset + 1);
1893 u32 data = nvbios_rd32(bios, init->offset + 5);
1894
1895 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1896 init->offset += 9;
1897
1898 if (addr == 0x000200)
1899 data |= 0x00000001;
1900
1901 init_wr32(init, addr, data);
1902 }
1903
1904 /**
1905 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1906 *
1907 */
1908 static void
1909 init_ram_restrict_pll(struct nvbios_init *init)
1910 {
1911 struct nvkm_bios *bios = init->subdev->device->bios;
1912 u8 type = nvbios_rd08(bios, init->offset + 1);
1913 u8 count = init_ram_restrict_group_count(init);
1914 u8 strap = init_ram_restrict(init);
1915 u8 cconf;
1916
1917 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1918 init->offset += 2;
1919
1920 for (cconf = 0; cconf < count; cconf++) {
1921 u32 freq = nvbios_rd32(bios, init->offset);
1922
1923 if (cconf == strap) {
1924 trace("%dkHz *\n", freq);
1925 init_prog_pll(init, type, freq);
1926 } else {
1927 trace("%dkHz\n", freq);
1928 }
1929
1930 init->offset += 4;
1931 }
1932 }
1933
1934 /**
1935 * INIT_GPIO - opcode 0x8e
1936 *
1937 */
1938 static void
1939 init_gpio(struct nvbios_init *init)
1940 {
1941 struct nvkm_gpio *gpio = init->subdev->device->gpio;
1942
1943 trace("GPIO\n");
1944 init->offset += 1;
1945
1946 if (init_exec(init))
1947 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED);
1948 }
1949
1950 /**
1951 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1952 *
1953 */
1954 static void
1955 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1956 {
1957 struct nvkm_bios *bios = init->subdev->device->bios;
1958 u32 addr = nvbios_rd32(bios, init->offset + 1);
1959 u8 incr = nvbios_rd08(bios, init->offset + 5);
1960 u8 num = nvbios_rd08(bios, init->offset + 6);
1961 u8 count = init_ram_restrict_group_count(init);
1962 u8 index = init_ram_restrict(init);
1963 u8 i, j;
1964
1965 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1966 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1967 init->offset += 7;
1968
1969 for (i = 0; i < num; i++) {
1970 trace("\tR[0x%06x] = {\n", addr);
1971 for (j = 0; j < count; j++) {
1972 u32 data = nvbios_rd32(bios, init->offset);
1973
1974 if (j == index) {
1975 trace("\t\t0x%08x *\n", data);
1976 init_wr32(init, addr, data);
1977 } else {
1978 trace("\t\t0x%08x\n", data);
1979 }
1980
1981 init->offset += 4;
1982 }
1983 trace("\t}\n");
1984 addr += incr;
1985 }
1986 }
1987
1988 /**
1989 * INIT_COPY_ZM_REG - opcode 0x90
1990 *
1991 */
1992 static void
1993 init_copy_zm_reg(struct nvbios_init *init)
1994 {
1995 struct nvkm_bios *bios = init->subdev->device->bios;
1996 u32 sreg = nvbios_rd32(bios, init->offset + 1);
1997 u32 dreg = nvbios_rd32(bios, init->offset + 5);
1998
1999 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
2000 init->offset += 9;
2001
2002 init_wr32(init, dreg, init_rd32(init, sreg));
2003 }
2004
2005 /**
2006 * INIT_ZM_REG_GROUP - opcode 0x91
2007 *
2008 */
2009 static void
2010 init_zm_reg_group(struct nvbios_init *init)
2011 {
2012 struct nvkm_bios *bios = init->subdev->device->bios;
2013 u32 addr = nvbios_rd32(bios, init->offset + 1);
2014 u8 count = nvbios_rd08(bios, init->offset + 5);
2015
2016 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
2017 init->offset += 6;
2018
2019 while (count--) {
2020 u32 data = nvbios_rd32(bios, init->offset);
2021 trace("\t0x%08x\n", data);
2022 init_wr32(init, addr, data);
2023 init->offset += 4;
2024 }
2025 }
2026
2027 /**
2028 * INIT_XLAT - opcode 0x96
2029 *
2030 */
2031 static void
2032 init_xlat(struct nvbios_init *init)
2033 {
2034 struct nvkm_bios *bios = init->subdev->device->bios;
2035 u32 saddr = nvbios_rd32(bios, init->offset + 1);
2036 u8 sshift = nvbios_rd08(bios, init->offset + 5);
2037 u8 smask = nvbios_rd08(bios, init->offset + 6);
2038 u8 index = nvbios_rd08(bios, init->offset + 7);
2039 u32 daddr = nvbios_rd32(bios, init->offset + 8);
2040 u32 dmask = nvbios_rd32(bios, init->offset + 12);
2041 u8 shift = nvbios_rd08(bios, init->offset + 16);
2042 u32 data;
2043
2044 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
2045 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2046 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2047 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2048 init->offset += 17;
2049
2050 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2051 data = init_xlat_(init, index, data) << shift;
2052 init_mask(init, daddr, ~dmask, data);
2053 }
2054
2055 /**
2056 * INIT_ZM_MASK_ADD - opcode 0x97
2057 *
2058 */
2059 static void
2060 init_zm_mask_add(struct nvbios_init *init)
2061 {
2062 struct nvkm_bios *bios = init->subdev->device->bios;
2063 u32 addr = nvbios_rd32(bios, init->offset + 1);
2064 u32 mask = nvbios_rd32(bios, init->offset + 5);
2065 u32 add = nvbios_rd32(bios, init->offset + 9);
2066 u32 data;
2067
2068 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2069 init->offset += 13;
2070
2071 data = init_rd32(init, addr);
2072 data = (data & mask) | ((data + add) & ~mask);
2073 init_wr32(init, addr, data);
2074 }
2075
2076 /**
2077 * INIT_AUXCH - opcode 0x98
2078 *
2079 */
2080 static void
2081 init_auxch(struct nvbios_init *init)
2082 {
2083 struct nvkm_bios *bios = init->subdev->device->bios;
2084 u32 addr = nvbios_rd32(bios, init->offset + 1);
2085 u8 count = nvbios_rd08(bios, init->offset + 5);
2086
2087 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2088 init->offset += 6;
2089
2090 while (count--) {
2091 u8 mask = nvbios_rd08(bios, init->offset + 0);
2092 u8 data = nvbios_rd08(bios, init->offset + 1);
2093 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2094 mask = init_rdauxr(init, addr) & mask;
2095 init_wrauxr(init, addr, mask | data);
2096 init->offset += 2;
2097 }
2098 }
2099
2100 /**
2101 * INIT_AUXCH - opcode 0x99
2102 *
2103 */
2104 static void
2105 init_zm_auxch(struct nvbios_init *init)
2106 {
2107 struct nvkm_bios *bios = init->subdev->device->bios;
2108 u32 addr = nvbios_rd32(bios, init->offset + 1);
2109 u8 count = nvbios_rd08(bios, init->offset + 5);
2110
2111 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2112 init->offset += 6;
2113
2114 while (count--) {
2115 u8 data = nvbios_rd08(bios, init->offset + 0);
2116 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2117 init_wrauxr(init, addr, data);
2118 init->offset += 1;
2119 }
2120 }
2121
2122 /**
2123 * INIT_I2C_LONG_IF - opcode 0x9a
2124 *
2125 */
2126 static void
2127 init_i2c_long_if(struct nvbios_init *init)
2128 {
2129 struct nvkm_bios *bios = init->subdev->device->bios;
2130 u8 index = nvbios_rd08(bios, init->offset + 1);
2131 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1;
2132 u8 reglo = nvbios_rd08(bios, init->offset + 3);
2133 u8 reghi = nvbios_rd08(bios, init->offset + 4);
2134 u8 mask = nvbios_rd08(bios, init->offset + 5);
2135 u8 data = nvbios_rd08(bios, init->offset + 6);
2136 struct i2c_adapter *adap;
2137
2138 trace("I2C_LONG_IF\t"
2139 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2140 index, addr, reglo, reghi, mask, data);
2141 init->offset += 7;
2142
2143 adap = init_i2c(init, index);
2144 if (adap) {
2145 u8 i[2] = { reghi, reglo };
2146 u8 o[1] = {};
2147 struct i2c_msg msg[] = {
2148 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2149 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2150 };
2151 int ret;
2152
2153 ret = i2c_transfer(adap, msg, 2);
2154 if (ret == 2 && ((o[0] & mask) == data))
2155 return;
2156 }
2157
2158 init_exec_set(init, false);
2159 }
2160
2161 /**
2162 * INIT_GPIO_NE - opcode 0xa9
2163 *
2164 */
2165 static void
2166 init_gpio_ne(struct nvbios_init *init)
2167 {
2168 struct nvkm_bios *bios = init->subdev->device->bios;
2169 struct nvkm_gpio *gpio = bios->subdev.device->gpio;
2170 struct dcb_gpio_func func;
2171 u8 count = nvbios_rd08(bios, init->offset + 1);
2172 u8 idx = 0, ver, len;
2173 u16 data, i;
2174
2175 trace("GPIO_NE\t");
2176 init->offset += 2;
2177
2178 for (i = init->offset; i < init->offset + count; i++)
2179 cont("0x%02x ", nvbios_rd08(bios, i));
2180 cont("\n");
2181
2182 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2183 if (func.func != DCB_GPIO_UNUSED) {
2184 for (i = init->offset; i < init->offset + count; i++) {
2185 if (func.func == nvbios_rd08(bios, i))
2186 break;
2187 }
2188
2189 trace("\tFUNC[0x%02x]", func.func);
2190 if (i == (init->offset + count)) {
2191 cont(" *");
2192 if (init_exec(init))
2193 nvkm_gpio_reset(gpio, func.func);
2194 }
2195 cont("\n");
2196 }
2197 }
2198
2199 init->offset += count;
2200 }
2201
2202 static struct nvbios_init_opcode {
2203 void (*exec)(struct nvbios_init *);
2204 } init_opcode[] = {
2205 [0x32] = { init_io_restrict_prog },
2206 [0x33] = { init_repeat },
2207 [0x34] = { init_io_restrict_pll },
2208 [0x36] = { init_end_repeat },
2209 [0x37] = { init_copy },
2210 [0x38] = { init_not },
2211 [0x39] = { init_io_flag_condition },
2212 [0x3a] = { init_generic_condition },
2213 [0x3b] = { init_io_mask_or },
2214 [0x3c] = { init_io_or },
2215 [0x47] = { init_andn_reg },
2216 [0x48] = { init_or_reg },
2217 [0x49] = { init_idx_addr_latched },
2218 [0x4a] = { init_io_restrict_pll2 },
2219 [0x4b] = { init_pll2 },
2220 [0x4c] = { init_i2c_byte },
2221 [0x4d] = { init_zm_i2c_byte },
2222 [0x4e] = { init_zm_i2c },
2223 [0x4f] = { init_tmds },
2224 [0x50] = { init_zm_tmds_group },
2225 [0x51] = { init_cr_idx_adr_latch },
2226 [0x52] = { init_cr },
2227 [0x53] = { init_zm_cr },
2228 [0x54] = { init_zm_cr_group },
2229 [0x56] = { init_condition_time },
2230 [0x57] = { init_ltime },
2231 [0x58] = { init_zm_reg_sequence },
2232 [0x59] = { init_pll_indirect },
2233 [0x5a] = { init_zm_reg_indirect },
2234 [0x5b] = { init_sub_direct },
2235 [0x5c] = { init_jump },
2236 [0x5e] = { init_i2c_if },
2237 [0x5f] = { init_copy_nv_reg },
2238 [0x62] = { init_zm_index_io },
2239 [0x63] = { init_compute_mem },
2240 [0x65] = { init_reset },
2241 [0x66] = { init_configure_mem },
2242 [0x67] = { init_configure_clk },
2243 [0x68] = { init_configure_preinit },
2244 [0x69] = { init_io },
2245 [0x6b] = { init_sub },
2246 [0x6d] = { init_ram_condition },
2247 [0x6e] = { init_nv_reg },
2248 [0x6f] = { init_macro },
2249 [0x71] = { init_done },
2250 [0x72] = { init_resume },
2251 [0x73] = { init_strap_condition },
2252 [0x74] = { init_time },
2253 [0x75] = { init_condition },
2254 [0x76] = { init_io_condition },
2255 [0x77] = { init_zm_reg16 },
2256 [0x78] = { init_index_io },
2257 [0x79] = { init_pll },
2258 [0x7a] = { init_zm_reg },
2259 [0x87] = { init_ram_restrict_pll },
2260 [0x8c] = { init_reserved },
2261 [0x8d] = { init_reserved },
2262 [0x8e] = { init_gpio },
2263 [0x8f] = { init_ram_restrict_zm_reg_group },
2264 [0x90] = { init_copy_zm_reg },
2265 [0x91] = { init_zm_reg_group },
2266 [0x92] = { init_reserved },
2267 [0x96] = { init_xlat },
2268 [0x97] = { init_zm_mask_add },
2269 [0x98] = { init_auxch },
2270 [0x99] = { init_zm_auxch },
2271 [0x9a] = { init_i2c_long_if },
2272 [0xa9] = { init_gpio_ne },
2273 [0xaa] = { init_reserved },
2274 };
2275
2276 int
2277 nvbios_exec(struct nvbios_init *init)
2278 {
2279 struct nvkm_bios *bios = init->subdev->device->bios;
2280
2281 init->nested++;
2282 while (init->offset) {
2283 u8 opcode = nvbios_rd08(bios, init->offset);
2284 if (opcode >= ARRAY_SIZE(init_opcode) ||
2285 !init_opcode[opcode].exec) {
2286 error("unknown opcode 0x%02x\n", opcode);
2287 return -EINVAL;
2288 }
2289
2290 init_opcode[opcode].exec(init);
2291 }
2292 init->nested--;
2293 return 0;
2294 }
2295
2296 int
2297 nvbios_post(struct nvkm_subdev *subdev, bool execute)
2298 {
2299 struct nvkm_bios *bios = subdev->device->bios;
2300 int ret = 0;
2301 int i = -1;
2302 u16 data;
2303
2304 if (execute)
2305 nvkm_debug(subdev, "running init tables\n");
2306 while (!ret && (data = (init_script(bios, ++i)))) {
2307 ret = nvbios_init(subdev, data,
2308 init.execute = execute ? 1 : 0;
2309 );
2310 }
2311
2312 /* the vbios parser will run this right after the normal init
2313 * tables, whereas the binary driver appears to run it later.
2314 */
2315 if (!ret && (data = init_unknown_script(bios))) {
2316 ret = nvbios_init(subdev, data,
2317 init.execute = execute ? 1 : 0;
2318 );
2319 }
2320
2321 return ret;
2322 }
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