drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <subdev/bios.h>
  25 #include <subdev/bios/bit.h>
  26 #include <subdev/bios/bmp.h>
  27 #include <subdev/bios/conn.h>
  28 #include <subdev/bios/dcb.h>
  29 #include <subdev/bios/dp.h>
  30 #include <subdev/bios/gpio.h>
  31 #include <subdev/bios/init.h>
  32 #include <subdev/bios/ramcfg.h>
  33
  34 #include <core/device.h>
  35 #include <subdev/devinit.h>
  36 #include <subdev/gpio.h>
  37 #include <subdev/i2c.h>
  38 #include <subdev/vga.h>
  39
  40 #define bioslog(lvl, fmt, args...) do {                                        \
  41         nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset,            \
  42                   init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args);   \
  43 } while(0)
  44 #define cont(fmt, args...) do {                                                \
  45         if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE)                      \
  46                 printk(fmt, ##args);                                           \
  47 } while(0)
  48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
  49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
  50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
  51
  52 /******************************************************************************
  53  * init parser control flow helpers
  54  *****************************************************************************/
  55
  56 static inline bool
  57 init_exec(struct nvbios_init *init)
  58 {
  59         return (init->execute == 1) || ((init->execute & 5) == 5);
  60 }
  61
  62 static inline void
  63 init_exec_set(struct nvbios_init *init, bool exec)
  64 {
  65         if (exec) init->execute &= 0xfd;
  66         else      init->execute |= 0x02;
  67 }
  68
  69 static inline void
  70 init_exec_inv(struct nvbios_init *init)
  71 {
  72         init->execute ^= 0x02;
  73 }
  74
  75 static inline void
  76 init_exec_force(struct nvbios_init *init, bool exec)
  77 {
  78         if (exec) init->execute |= 0x04;
  79         else      init->execute &= 0xfb;
  80 }
  81
  82 /******************************************************************************
  83  * init parser wrappers for normal register/i2c/whatever accessors
  84  *****************************************************************************/
  85
  86 static inline int
  87 init_or(struct nvbios_init *init)
  88 {
  89         if (init_exec(init)) {
  90                 if (init->outp)
  91                         return ffs(init->outp->or) - 1;
  92                 error("script needs OR!!\n");
  93         }
  94         return 0;
  95 }
  96
  97 static inline int
  98 init_link(struct nvbios_init *init)
  99 {
 100         if (init_exec(init)) {
 101                 if (init->outp)
 102                         return !(init->outp->sorconf.link & 1);
 103                 error("script needs OR link\n");
 104         }
 105         return 0;
 106 }
 107
 108 static inline int
 109 init_crtc(struct nvbios_init *init)
 110 {
 111         if (init_exec(init)) {
 112                 if (init->crtc >= 0)
 113                         return init->crtc;
 114                 error("script needs crtc\n");
 115         }
 116         return 0;
 117 }
 118
 119 static u8
 120 init_conn(struct nvbios_init *init)
 121 {
 122         struct nvkm_bios *bios = init->bios;
 123         struct nvbios_connE connE;
 124         u8  ver, hdr;
 125         u32 conn;
 126
 127         if (init_exec(init)) {
 128                 if (init->outp) {
 129                         conn = init->outp->connector;
 130                         conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
 131                         if (conn)
 132                                 return connE.type;
 133                 }
 134
 135                 error("script needs connector type\n");
 136         }
 137
 138         return 0xff;
 139 }
 140
 141 static inline u32
 142 init_nvreg(struct nvbios_init *init, u32 reg)
 143 {
 144         struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
 145
 146         /* C51 (at least) sometimes has the lower bits set which the VBIOS
 147          * interprets to mean that access needs to go through certain IO
 148          * ports instead.  The NVIDIA binary driver has been seen to access
 149          * these through the NV register address, so lets assume we can
 150          * do the same
 151          */
 152         reg &= ~0x00000003;
 153
 154         /* GF8+ display scripts need register addresses mangled a bit to
 155          * select a specific CRTC/OR
 156          */
 157         if (nv_device(init->bios)->card_type >= NV_50) {
 158                 if (reg & 0x80000000) {
 159                         reg += init_crtc(init) * 0x800;
 160                         reg &= ~0x80000000;
 161                 }
 162
 163                 if (reg & 0x40000000) {
 164                         reg += init_or(init) * 0x800;
 165                         reg &= ~0x40000000;
 166                         if (reg & 0x20000000) {
 167                                 reg += init_link(init) * 0x80;
 168                                 reg &= ~0x20000000;
 169                         }
 170                 }
 171         }
 172
 173         if (reg & ~0x00fffffc)
 174                 warn("unknown bits in register 0x%08x\n", reg);
 175
 176         if (devinit->mmio)
 177                 reg = devinit->mmio(devinit, reg);
 178         return reg;
 179 }
 180
 181 static u32
 182 init_rd32(struct nvbios_init *init, u32 reg)
 183 {
 184         reg = init_nvreg(init, reg);
 185         if (reg != ~0 && init_exec(init))
 186                 return nv_rd32(init->subdev, reg);
 187         return 0x00000000;
 188 }
 189
 190 static void
 191 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
 192 {
 193         reg = init_nvreg(init, reg);
 194         if (reg != ~0 && init_exec(init))
 195                 nv_wr32(init->subdev, reg, val);
 196 }
 197
 198 static u32
 199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
 200 {
 201         reg = init_nvreg(init, reg);
 202         if (reg != ~0 && init_exec(init)) {
 203                 u32 tmp = nv_rd32(init->subdev, reg);
 204                 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
 205                 return tmp;
 206         }
 207         return 0x00000000;
 208 }
 209
 210 static u8
 211 init_rdport(struct nvbios_init *init, u16 port)
 212 {
 213         if (init_exec(init))
 214                 return nv_rdport(init->subdev, init->crtc, port);
 215         return 0x00;
 216 }
 217
 218 static void
 219 init_wrport(struct nvbios_init *init, u16 port, u8 value)
 220 {
 221         if (init_exec(init))
 222                 nv_wrport(init->subdev, init->crtc, port, value);
 223 }
 224
 225 static u8
 226 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
 227 {
 228         struct nvkm_subdev *subdev = init->subdev;
 229         if (init_exec(init)) {
 230                 int head = init->crtc < 0 ? 0 : init->crtc;
 231                 return nv_rdvgai(subdev, head, port, index);
 232         }
 233         return 0x00;
 234 }
 235
 236 static void
 237 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
 238 {
 239         /* force head 0 for updates to cr44, it only exists on first head */
 240         if (nv_device(init->subdev)->card_type < NV_50) {
 241                 if (port == 0x03d4 && index == 0x44)
 242                         init->crtc = 0;
 243         }
 244
 245         if (init_exec(init)) {
 246                 int head = init->crtc < 0 ? 0 : init->crtc;
 247                 nv_wrvgai(init->subdev, head, port, index, value);
 248         }
 249
 250         /* select head 1 if cr44 write selected it */
 251         if (nv_device(init->subdev)->card_type < NV_50) {
 252                 if (port == 0x03d4 && index == 0x44 && value == 3)
 253                         init->crtc = 1;
 254         }
 255 }
 256
 257 static struct nvkm_i2c_port *
 258 init_i2c(struct nvbios_init *init, int index)
 259 {
 260         struct nvkm_i2c *i2c = nvkm_i2c(init->bios);
 261
 262         if (index == 0xff) {
 263                 index = NV_I2C_DEFAULT(0);
 264                 if (init->outp && init->outp->i2c_upper_default)
 265                         index = NV_I2C_DEFAULT(1);
 266         } else
 267         if (index < 0) {
 268                 if (!init->outp) {
 269                         if (init_exec(init))
 270                                 error("script needs output for i2c\n");
 271                         return NULL;
 272                 }
 273
 274                 if (index == -2 && init->outp->location) {
 275                         index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
 276                         return i2c->find_type(i2c, index);
 277                 }
 278
 279                 index = init->outp->i2c_index;
 280                 if (init->outp->type == DCB_OUTPUT_DP)
 281                         index += NV_I2C_AUX(0);
 282         }
 283
 284         return i2c->find(i2c, index);
 285 }
 286
 287 static int
 288 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
 289 {
 290         struct nvkm_i2c_port *port = init_i2c(init, index);
 291         if (port && init_exec(init))
 292                 return nv_rdi2cr(port, addr, reg);
 293         return -ENODEV;
 294 }
 295
 296 static int
 297 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
 298 {
 299         struct nvkm_i2c_port *port = init_i2c(init, index);
 300         if (port && init_exec(init))
 301                 return nv_wri2cr(port, addr, reg, val);
 302         return -ENODEV;
 303 }
 304
 305 static u8
 306 init_rdauxr(struct nvbios_init *init, u32 addr)
 307 {
 308         struct nvkm_i2c_port *port = init_i2c(init, -2);
 309         u8 data;
 310
 311         if (port && init_exec(init)) {
 312                 int ret = nv_rdaux(port, addr, &data, 1);
 313                 if (ret == 0)
 314                         return data;
 315                 trace("auxch read failed with %d\n", ret);
 316         }
 317
 318         return 0x00;
 319 }
 320
 321 static int
 322 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
 323 {
 324         struct nvkm_i2c_port *port = init_i2c(init, -2);
 325         if (port && init_exec(init)) {
 326                 int ret = nv_wraux(port, addr, &data, 1);
 327                 if (ret)
 328                         trace("auxch write failed with %d\n", ret);
 329                 return ret;
 330         }
 331         return -ENODEV;
 332 }
 333
 334 static void
 335 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
 336 {
 337         struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
 338         if (devinit->pll_set && init_exec(init)) {
 339                 int ret = devinit->pll_set(devinit, id, freq);
 340                 if (ret)
 341                         warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
 342         }
 343 }
 344
 345 /******************************************************************************
 346  * parsing of bios structures that are required to execute init tables
 347  *****************************************************************************/
 348
 349 static u16
 350 init_table(struct nvkm_bios *bios, u16 *len)
 351 {
 352         struct bit_entry bit_I;
 353
 354         if (!bit_entry(bios, 'I', &bit_I)) {
 355                 *len = bit_I.length;
 356                 return bit_I.offset;
 357         }
 358
 359         if (bmp_version(bios) >= 0x0510) {
 360                 *len = 14;
 361                 return bios->bmp_offset + 75;
 362         }
 363
 364         return 0x0000;
 365 }
 366
 367 static u16
 368 init_table_(struct nvbios_init *init, u16 offset, const char *name)
 369 {
 370         struct nvkm_bios *bios = init->bios;
 371         u16 len, data = init_table(bios, &len);
 372         if (data) {
 373                 if (len >= offset + 2) {
 374                         data = nv_ro16(bios, data + offset);
 375                         if (data)
 376                                 return data;
 377
 378                         warn("%s pointer invalid\n", name);
 379                         return 0x0000;
 380                 }
 381
 382                 warn("init data too short for %s pointer", name);
 383                 return 0x0000;
 384         }
 385
 386         warn("init data not found\n");
 387         return 0x0000;
 388 }
 389
 390 #define init_script_table(b) init_table_((b), 0x00, "script table")
 391 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
 392 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
 393 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
 394 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
 395 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
 396 #define init_function_table(b) init_table_((b), 0x0c, "function table")
 397 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
 398
 399 static u16
 400 init_script(struct nvkm_bios *bios, int index)
 401 {
 402         struct nvbios_init init = { .bios = bios };
 403         u16 bmp_ver = bmp_version(bios), data;
 404
 405         if (bmp_ver && bmp_ver < 0x0510) {
 406                 if (index > 1 || bmp_ver < 0x0100)
 407                         return 0x0000;
 408
 409                 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
 410                 return nv_ro16(bios, data + (index * 2));
 411         }
 412
 413         data = init_script_table(&init);
 414         if (data)
 415                 return nv_ro16(bios, data + (index * 2));
 416
 417         return 0x0000;
 418 }
 419
 420 static u16
 421 init_unknown_script(struct nvkm_bios *bios)
 422 {
 423         u16 len, data = init_table(bios, &len);
 424         if (data && len >= 16)
 425                 return nv_ro16(bios, data + 14);
 426         return 0x0000;
 427 }
 428
 429 static u8
 430 init_ram_restrict_group_count(struct nvbios_init *init)
 431 {
 432         return nvbios_ramcfg_count(init->bios);
 433 }
 434
 435 static u8
 436 init_ram_restrict(struct nvbios_init *init)
 437 {
 438         /* This appears to be the behaviour of the VBIOS parser, and *is*
 439          * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
 440          * avoid fucking up the memory controller (somehow) by reading it
 441          * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
 442          *
 443          * Preserving the non-caching behaviour on earlier chipsets just
 444          * in case *not* re-reading the strap causes similar breakage.
 445          */
 446         if (!init->ramcfg || init->bios->version.major < 0x70)
 447                 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
 448         return (init->ramcfg & 0x7fffffff);
 449 }
 450
 451 static u8
 452 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
 453 {
 454         struct nvkm_bios *bios = init->bios;
 455         u16 table = init_xlat_table(init);
 456         if (table) {
 457                 u16 data = nv_ro16(bios, table + (index * 2));
 458                 if (data)
 459                         return nv_ro08(bios, data + offset);
 460                 warn("xlat table pointer %d invalid\n", index);
 461         }
 462         return 0x00;
 463 }
 464
 465 /******************************************************************************
 466  * utility functions used by various init opcode handlers
 467  *****************************************************************************/
 468
 469 static bool
 470 init_condition_met(struct nvbios_init *init, u8 cond)
 471 {
 472         struct nvkm_bios *bios = init->bios;
 473         u16 table = init_condition_table(init);
 474         if (table) {
 475                 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
 476                 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
 477                 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
 478                 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
 479                       cond, reg, msk, val);
 480                 return (init_rd32(init, reg) & msk) == val;
 481         }
 482         return false;
 483 }
 484
 485 static bool
 486 init_io_condition_met(struct nvbios_init *init, u8 cond)
 487 {
 488         struct nvkm_bios *bios = init->bios;
 489         u16 table = init_io_condition_table(init);
 490         if (table) {
 491                 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
 492                 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
 493                 u8  mask = nv_ro08(bios, table + (cond * 5) + 3);
 494                 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
 495                 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
 496                       cond, port, index, mask, value);
 497                 return (init_rdvgai(init, port, index) & mask) == value;
 498         }
 499         return false;
 500 }
 501
 502 static bool
 503 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
 504 {
 505         struct nvkm_bios *bios = init->bios;
 506         u16 table = init_io_flag_condition_table(init);
 507         if (table) {
 508                 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
 509                 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
 510                 u8  mask = nv_ro08(bios, table + (cond * 9) + 3);
 511                 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
 512                 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
 513                 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
 514                 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
 515                 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
 516                 return (nv_ro08(bios, data + ioval) & dmask) == value;
 517         }
 518         return false;
 519 }
 520
 521 static inline u32
 522 init_shift(u32 data, u8 shift)
 523 {
 524         if (shift < 0x80)
 525                 return data >> shift;
 526         return data << (0x100 - shift);
 527 }
 528
 529 static u32
 530 init_tmds_reg(struct nvbios_init *init, u8 tmds)
 531 {
 532         /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
 533          * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
 534          * CR58 for CR57 = 0 to index a table of offsets to the basic
 535          * 0x6808b0 address.
 536          * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
 537          * CR58 for CR57 = 0 to index a table of offsets to the basic
 538          * 0x6808b0 address, and then flip the offset by 8.
 539          */
 540         const int pramdac_offset[13] = {
 541                 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
 542         const u32 pramdac_table[4] = {
 543                 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
 544
 545         if (tmds >= 0x80) {
 546                 if (init->outp) {
 547                         u32 dacoffset = pramdac_offset[init->outp->or];
 548                         if (tmds == 0x81)
 549                                 dacoffset ^= 8;
 550                         return 0x6808b0 + dacoffset;
 551                 }
 552
 553                 if (init_exec(init))
 554                         error("tmds opcodes need dcb\n");
 555         } else {
 556                 if (tmds < ARRAY_SIZE(pramdac_table))
 557                         return pramdac_table[tmds];
 558
 559                 error("tmds selector 0x%02x unknown\n", tmds);
 560         }
 561
 562         return 0;
 563 }
 564
 565 /******************************************************************************
 566  * init opcode handlers
 567  *****************************************************************************/
 568
 569 /**
 570  * init_reserved - stub for various unknown/unused single-byte opcodes
 571  *
 572  */
 573 static void
 574 init_reserved(struct nvbios_init *init)
 575 {
 576         u8 opcode = nv_ro08(init->bios, init->offset);
 577         u8 length, i;
 578
 579         switch (opcode) {
 580         case 0xaa:
 581                 length = 4;
 582                 break;
 583         default:
 584                 length = 1;
 585                 break;
 586         }
 587
 588         trace("RESERVED 0x%02x\t", opcode);
 589         for (i = 1; i < length; i++)
 590                 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
 591         cont("\n");
 592         init->offset += length;
 593 }
 594
 595 /**
 596  * INIT_DONE - opcode 0x71
 597  *
 598  */
 599 static void
 600 init_done(struct nvbios_init *init)
 601 {
 602         trace("DONE\n");
 603         init->offset = 0x0000;
 604 }
 605
 606 /**
 607  * INIT_IO_RESTRICT_PROG - opcode 0x32
 608  *
 609  */
 610 static void
 611 init_io_restrict_prog(struct nvbios_init *init)
 612 {
 613         struct nvkm_bios *bios = init->bios;
 614         u16 port = nv_ro16(bios, init->offset + 1);
 615         u8 index = nv_ro08(bios, init->offset + 3);
 616         u8  mask = nv_ro08(bios, init->offset + 4);
 617         u8 shift = nv_ro08(bios, init->offset + 5);
 618         u8 count = nv_ro08(bios, init->offset + 6);
 619         u32  reg = nv_ro32(bios, init->offset + 7);
 620         u8 conf, i;
 621
 622         trace("IO_RESTRICT_PROG\tR[0x%06x] = "
 623               "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
 624               reg, port, index, mask, shift);
 625         init->offset += 11;
 626
 627         conf = (init_rdvgai(init, port, index) & mask) >> shift;
 628         for (i = 0; i < count; i++) {
 629                 u32 data = nv_ro32(bios, init->offset);
 630
 631                 if (i == conf) {
 632                         trace("\t0x%08x *\n", data);
 633                         init_wr32(init, reg, data);
 634                 } else {
 635                         trace("\t0x%08x\n", data);
 636                 }
 637
 638                 init->offset += 4;
 639         }
 640         trace("}]\n");
 641 }
 642
 643 /**
 644  * INIT_REPEAT - opcode 0x33
 645  *
 646  */
 647 static void
 648 init_repeat(struct nvbios_init *init)
 649 {
 650         struct nvkm_bios *bios = init->bios;
 651         u8 count = nv_ro08(bios, init->offset + 1);
 652         u16 repeat = init->repeat;
 653
 654         trace("REPEAT\t0x%02x\n", count);
 655         init->offset += 2;
 656
 657         init->repeat = init->offset;
 658         init->repend = init->offset;
 659         while (count--) {
 660                 init->offset = init->repeat;
 661                 nvbios_exec(init);
 662                 if (count)
 663                         trace("REPEAT\t0x%02x\n", count);
 664         }
 665         init->offset = init->repend;
 666         init->repeat = repeat;
 667 }
 668
 669 /**
 670  * INIT_IO_RESTRICT_PLL - opcode 0x34
 671  *
 672  */
 673 static void
 674 init_io_restrict_pll(struct nvbios_init *init)
 675 {
 676         struct nvkm_bios *bios = init->bios;
 677         u16 port = nv_ro16(bios, init->offset + 1);
 678         u8 index = nv_ro08(bios, init->offset + 3);
 679         u8  mask = nv_ro08(bios, init->offset + 4);
 680         u8 shift = nv_ro08(bios, init->offset + 5);
 681         s8  iofc = nv_ro08(bios, init->offset + 6);
 682         u8 count = nv_ro08(bios, init->offset + 7);
 683         u32  reg = nv_ro32(bios, init->offset + 8);
 684         u8 conf, i;
 685
 686         trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
 687               "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
 688               reg, port, index, mask, shift, iofc);
 689         init->offset += 12;
 690
 691         conf = (init_rdvgai(init, port, index) & mask) >> shift;
 692         for (i = 0; i < count; i++) {
 693                 u32 freq = nv_ro16(bios, init->offset) * 10;
 694
 695                 if (i == conf) {
 696                         trace("\t%dkHz *\n", freq);
 697                         if (iofc > 0 && init_io_flag_condition_met(init, iofc))
 698                                 freq *= 2;
 699                         init_prog_pll(init, reg, freq);
 700                 } else {
 701                         trace("\t%dkHz\n", freq);
 702                 }
 703
 704                 init->offset += 2;
 705         }
 706         trace("}]\n");
 707 }
 708
 709 /**
 710  * INIT_END_REPEAT - opcode 0x36
 711  *
 712  */
 713 static void
 714 init_end_repeat(struct nvbios_init *init)
 715 {
 716         trace("END_REPEAT\n");
 717         init->offset += 1;
 718
 719         if (init->repeat) {
 720                 init->repend = init->offset;
 721                 init->offset = 0;
 722         }
 723 }
 724
 725 /**
 726  * INIT_COPY - opcode 0x37
 727  *
 728  */
 729 static void
 730 init_copy(struct nvbios_init *init)
 731 {
 732         struct nvkm_bios *bios = init->bios;
 733         u32  reg = nv_ro32(bios, init->offset + 1);
 734         u8 shift = nv_ro08(bios, init->offset + 5);
 735         u8 smask = nv_ro08(bios, init->offset + 6);
 736         u16 port = nv_ro16(bios, init->offset + 7);
 737         u8 index = nv_ro08(bios, init->offset + 9);
 738         u8  mask = nv_ro08(bios, init->offset + 10);
 739         u8  data;
 740
 741         trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
 742               "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
 743               port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
 744               (shift & 0x80) ? (0x100 - shift) : shift, smask);
 745         init->offset += 11;
 746
 747         data  = init_rdvgai(init, port, index) & mask;
 748         data |= init_shift(init_rd32(init, reg), shift) & smask;
 749         init_wrvgai(init, port, index, data);
 750 }
 751
 752 /**
 753  * INIT_NOT - opcode 0x38
 754  *
 755  */
 756 static void
 757 init_not(struct nvbios_init *init)
 758 {
 759         trace("NOT\n");
 760         init->offset += 1;
 761         init_exec_inv(init);
 762 }
 763
 764 /**
 765  * INIT_IO_FLAG_CONDITION - opcode 0x39
 766  *
 767  */
 768 static void
 769 init_io_flag_condition(struct nvbios_init *init)
 770 {
 771         struct nvkm_bios *bios = init->bios;
 772         u8 cond = nv_ro08(bios, init->offset + 1);
 773
 774         trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
 775         init->offset += 2;
 776
 777         if (!init_io_flag_condition_met(init, cond))
 778                 init_exec_set(init, false);
 779 }
 780
 781 /**
 782  * INIT_DP_CONDITION - opcode 0x3a
 783  *
 784  */
 785 static void
 786 init_dp_condition(struct nvbios_init *init)
 787 {
 788         struct nvkm_bios *bios = init->bios;
 789         struct nvbios_dpout info;
 790         u8  cond = nv_ro08(bios, init->offset + 1);
 791         u8  unkn = nv_ro08(bios, init->offset + 2);
 792         u8  ver, hdr, cnt, len;
 793         u16 data;
 794
 795         trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
 796         init->offset += 3;
 797
 798         switch (cond) {
 799         case 0:
 800                 if (init_conn(init) != DCB_CONNECTOR_eDP)
 801                         init_exec_set(init, false);
 802                 break;
 803         case 1:
 804         case 2:
 805                 if ( init->outp &&
 806                     (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
 807                                                (init->outp->or << 0) |
 808                                                (init->outp->sorconf.link << 6),
 809                                                &ver, &hdr, &cnt, &len, &info)))
 810                 {
 811                         if (!(info.flags & cond))
 812                                 init_exec_set(init, false);
 813                         break;
 814                 }
 815
 816                 if (init_exec(init))
 817                         warn("script needs dp output table data\n");
 818                 break;
 819         case 5:
 820                 if (!(init_rdauxr(init, 0x0d) & 1))
 821                         init_exec_set(init, false);
 822                 break;
 823         default:
 824                 warn("unknown dp condition 0x%02x\n", cond);
 825                 break;
 826         }
 827 }
 828
 829 /**
 830  * INIT_IO_MASK_OR - opcode 0x3b
 831  *
 832  */
 833 static void
 834 init_io_mask_or(struct nvbios_init *init)
 835 {
 836         struct nvkm_bios *bios = init->bios;
 837         u8 index = nv_ro08(bios, init->offset + 1);
 838         u8    or = init_or(init);
 839         u8  data;
 840
 841         trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
 842         init->offset += 2;
 843
 844         data = init_rdvgai(init, 0x03d4, index);
 845         init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
 846 }
 847
 848 /**
 849  * INIT_IO_OR - opcode 0x3c
 850  *
 851  */
 852 static void
 853 init_io_or(struct nvbios_init *init)
 854 {
 855         struct nvkm_bios *bios = init->bios;
 856         u8 index = nv_ro08(bios, init->offset + 1);
 857         u8    or = init_or(init);
 858         u8  data;
 859
 860         trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
 861         init->offset += 2;
 862
 863         data = init_rdvgai(init, 0x03d4, index);
 864         init_wrvgai(init, 0x03d4, index, data | (1 << or));
 865 }
 866
 867 /**
 868  * INIT_ANDN_REG - opcode 0x47
 869  *
 870  */
 871 static void
 872 init_andn_reg(struct nvbios_init *init)
 873 {
 874         struct nvkm_bios *bios = init->bios;
 875         u32  reg = nv_ro32(bios, init->offset + 1);
 876         u32 mask = nv_ro32(bios, init->offset + 5);
 877
 878         trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
 879         init->offset += 9;
 880
 881         init_mask(init, reg, mask, 0);
 882 }
 883
 884 /**
 885  * INIT_OR_REG - opcode 0x48
 886  *
 887  */
 888 static void
 889 init_or_reg(struct nvbios_init *init)
 890 {
 891         struct nvkm_bios *bios = init->bios;
 892         u32  reg = nv_ro32(bios, init->offset + 1);
 893         u32 mask = nv_ro32(bios, init->offset + 5);
 894
 895         trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
 896         init->offset += 9;
 897
 898         init_mask(init, reg, 0, mask);
 899 }
 900
 901 /**
 902  * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
 903  *
 904  */
 905 static void
 906 init_idx_addr_latched(struct nvbios_init *init)
 907 {
 908         struct nvkm_bios *bios = init->bios;
 909         u32 creg = nv_ro32(bios, init->offset + 1);
 910         u32 dreg = nv_ro32(bios, init->offset + 5);
 911         u32 mask = nv_ro32(bios, init->offset + 9);
 912         u32 data = nv_ro32(bios, init->offset + 13);
 913         u8 count = nv_ro08(bios, init->offset + 17);
 914
 915         trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
 916         trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
 917         init->offset += 18;
 918
 919         while (count--) {
 920                 u8 iaddr = nv_ro08(bios, init->offset + 0);
 921                 u8 idata = nv_ro08(bios, init->offset + 1);
 922
 923                 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
 924                 init->offset += 2;
 925
 926                 init_wr32(init, dreg, idata);
 927                 init_mask(init, creg, ~mask, data | iaddr);
 928         }
 929 }
 930
 931 /**
 932  * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
 933  *
 934  */
 935 static void
 936 init_io_restrict_pll2(struct nvbios_init *init)
 937 {
 938         struct nvkm_bios *bios = init->bios;
 939         u16 port = nv_ro16(bios, init->offset + 1);
 940         u8 index = nv_ro08(bios, init->offset + 3);
 941         u8  mask = nv_ro08(bios, init->offset + 4);
 942         u8 shift = nv_ro08(bios, init->offset + 5);
 943         u8 count = nv_ro08(bios, init->offset + 6);
 944         u32  reg = nv_ro32(bios, init->offset + 7);
 945         u8  conf, i;
 946
 947         trace("IO_RESTRICT_PLL2\t"
 948               "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
 949               reg, port, index, mask, shift);
 950         init->offset += 11;
 951
 952         conf = (init_rdvgai(init, port, index) & mask) >> shift;
 953         for (i = 0; i < count; i++) {
 954                 u32 freq = nv_ro32(bios, init->offset);
 955                 if (i == conf) {
 956                         trace("\t%dkHz *\n", freq);
 957                         init_prog_pll(init, reg, freq);
 958                 } else {
 959                         trace("\t%dkHz\n", freq);
 960                 }
 961                 init->offset += 4;
 962         }
 963         trace("}]\n");
 964 }
 965
 966 /**
 967  * INIT_PLL2 - opcode 0x4b
 968  *
 969  */
 970 static void
 971 init_pll2(struct nvbios_init *init)
 972 {
 973         struct nvkm_bios *bios = init->bios;
 974         u32  reg = nv_ro32(bios, init->offset + 1);
 975         u32 freq = nv_ro32(bios, init->offset + 5);
 976
 977         trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
 978         init->offset += 9;
 979
 980         init_prog_pll(init, reg, freq);
 981 }
 982
 983 /**
 984  * INIT_I2C_BYTE - opcode 0x4c
 985  *
 986  */
 987 static void
 988 init_i2c_byte(struct nvbios_init *init)
 989 {
 990         struct nvkm_bios *bios = init->bios;
 991         u8 index = nv_ro08(bios, init->offset + 1);
 992         u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
 993         u8 count = nv_ro08(bios, init->offset + 3);
 994
 995         trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
 996         init->offset += 4;
 997
 998         while (count--) {
 999                 u8  reg = nv_ro08(bios, init->offset + 0);
1000                 u8 mask = nv_ro08(bios, init->offset + 1);
1001                 u8 data = nv_ro08(bios, init->offset + 2);
1002                 int val;
1003
1004                 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1005                 init->offset += 3;
1006
1007                 val = init_rdi2cr(init, index, addr, reg);
1008                 if (val < 0)
1009                         continue;
1010                 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1011         }
1012 }
1013
1014 /**
1015  * INIT_ZM_I2C_BYTE - opcode 0x4d
1016  *
1017  */
1018 static void
1019 init_zm_i2c_byte(struct nvbios_init *init)
1020 {
1021         struct nvkm_bios *bios = init->bios;
1022         u8 index = nv_ro08(bios, init->offset + 1);
1023         u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
1024         u8 count = nv_ro08(bios, init->offset + 3);
1025
1026         trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1027         init->offset += 4;
1028
1029         while (count--) {
1030                 u8  reg = nv_ro08(bios, init->offset + 0);
1031                 u8 data = nv_ro08(bios, init->offset + 1);
1032
1033                 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1034                 init->offset += 2;
1035
1036                 init_wri2cr(init, index, addr, reg, data);
1037         }
1038 }
1039
1040 /**
1041  * INIT_ZM_I2C - opcode 0x4e
1042  *
1043  */
1044 static void
1045 init_zm_i2c(struct nvbios_init *init)
1046 {
1047         struct nvkm_bios *bios = init->bios;
1048         u8 index = nv_ro08(bios, init->offset + 1);
1049         u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
1050         u8 count = nv_ro08(bios, init->offset + 3);
1051         u8 data[256], i;
1052
1053         trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1054         init->offset += 4;
1055
1056         for (i = 0; i < count; i++) {
1057                 data[i] = nv_ro08(bios, init->offset);
1058                 trace("\t0x%02x\n", data[i]);
1059                 init->offset++;
1060         }
1061
1062         if (init_exec(init)) {
1063                 struct nvkm_i2c_port *port = init_i2c(init, index);
1064                 struct i2c_msg msg = {
1065                         .addr = addr, .flags = 0, .len = count, .buf = data,
1066                 };
1067                 int ret;
1068
1069                 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1070                         warn("i2c wr failed, %d\n", ret);
1071         }
1072 }
1073
1074 /**
1075  * INIT_TMDS - opcode 0x4f
1076  *
1077  */
1078 static void
1079 init_tmds(struct nvbios_init *init)
1080 {
1081         struct nvkm_bios *bios = init->bios;
1082         u8 tmds = nv_ro08(bios, init->offset + 1);
1083         u8 addr = nv_ro08(bios, init->offset + 2);
1084         u8 mask = nv_ro08(bios, init->offset + 3);
1085         u8 data = nv_ro08(bios, init->offset + 4);
1086         u32 reg = init_tmds_reg(init, tmds);
1087
1088         trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1089               tmds, addr, mask, data);
1090         init->offset += 5;
1091
1092         if (reg == 0)
1093                 return;
1094
1095         init_wr32(init, reg + 0, addr | 0x00010000);
1096         init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1097         init_wr32(init, reg + 0, addr);
1098 }
1099
1100 /**
1101  * INIT_ZM_TMDS_GROUP - opcode 0x50
1102  *
1103  */
1104 static void
1105 init_zm_tmds_group(struct nvbios_init *init)
1106 {
1107         struct nvkm_bios *bios = init->bios;
1108         u8  tmds = nv_ro08(bios, init->offset + 1);
1109         u8 count = nv_ro08(bios, init->offset + 2);
1110         u32  reg = init_tmds_reg(init, tmds);
1111
1112         trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1113         init->offset += 3;
1114
1115         while (count--) {
1116                 u8 addr = nv_ro08(bios, init->offset + 0);
1117                 u8 data = nv_ro08(bios, init->offset + 1);
1118
1119                 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1120                 init->offset += 2;
1121
1122                 init_wr32(init, reg + 4, data);
1123                 init_wr32(init, reg + 0, addr);
1124         }
1125 }
1126
1127 /**
1128  * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1129  *
1130  */
1131 static void
1132 init_cr_idx_adr_latch(struct nvbios_init *init)
1133 {
1134         struct nvkm_bios *bios = init->bios;
1135         u8 addr0 = nv_ro08(bios, init->offset + 1);
1136         u8 addr1 = nv_ro08(bios, init->offset + 2);
1137         u8  base = nv_ro08(bios, init->offset + 3);
1138         u8 count = nv_ro08(bios, init->offset + 4);
1139         u8 save0;
1140
1141         trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1142         init->offset += 5;
1143
1144         save0 = init_rdvgai(init, 0x03d4, addr0);
1145         while (count--) {
1146                 u8 data = nv_ro08(bios, init->offset);
1147
1148                 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1149                 init->offset += 1;
1150
1151                 init_wrvgai(init, 0x03d4, addr0, base++);
1152                 init_wrvgai(init, 0x03d4, addr1, data);
1153         }
1154         init_wrvgai(init, 0x03d4, addr0, save0);
1155 }
1156
1157 /**
1158  * INIT_CR - opcode 0x52
1159  *
1160  */
1161 static void
1162 init_cr(struct nvbios_init *init)
1163 {
1164         struct nvkm_bios *bios = init->bios;
1165         u8 addr = nv_ro08(bios, init->offset + 1);
1166         u8 mask = nv_ro08(bios, init->offset + 2);
1167         u8 data = nv_ro08(bios, init->offset + 3);
1168         u8 val;
1169
1170         trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1171         init->offset += 4;
1172
1173         val = init_rdvgai(init, 0x03d4, addr) & mask;
1174         init_wrvgai(init, 0x03d4, addr, val | data);
1175 }
1176
1177 /**
1178  * INIT_ZM_CR - opcode 0x53
1179  *
1180  */
1181 static void
1182 init_zm_cr(struct nvbios_init *init)
1183 {
1184         struct nvkm_bios *bios = init->bios;
1185         u8 addr = nv_ro08(bios, init->offset + 1);
1186         u8 data = nv_ro08(bios, init->offset + 2);
1187
1188         trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr,  data);
1189         init->offset += 3;
1190
1191         init_wrvgai(init, 0x03d4, addr, data);
1192 }
1193
1194 /**
1195  * INIT_ZM_CR_GROUP - opcode 0x54
1196  *
1197  */
1198 static void
1199 init_zm_cr_group(struct nvbios_init *init)
1200 {
1201         struct nvkm_bios *bios = init->bios;
1202         u8 count = nv_ro08(bios, init->offset + 1);
1203
1204         trace("ZM_CR_GROUP\n");
1205         init->offset += 2;
1206
1207         while (count--) {
1208                 u8 addr = nv_ro08(bios, init->offset + 0);
1209                 u8 data = nv_ro08(bios, init->offset + 1);
1210
1211                 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1212                 init->offset += 2;
1213
1214                 init_wrvgai(init, 0x03d4, addr, data);
1215         }
1216 }
1217
1218 /**
1219  * INIT_CONDITION_TIME - opcode 0x56
1220  *
1221  */
1222 static void
1223 init_condition_time(struct nvbios_init *init)
1224 {
1225         struct nvkm_bios *bios = init->bios;
1226         u8  cond = nv_ro08(bios, init->offset + 1);
1227         u8 retry = nv_ro08(bios, init->offset + 2);
1228         u8  wait = min((u16)retry * 50, 100);
1229
1230         trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1231         init->offset += 3;
1232
1233         if (!init_exec(init))
1234                 return;
1235
1236         while (wait--) {
1237                 if (init_condition_met(init, cond))
1238                         return;
1239                 mdelay(20);
1240         }
1241
1242         init_exec_set(init, false);
1243 }
1244
1245 /**
1246  * INIT_LTIME - opcode 0x57
1247  *
1248  */
1249 static void
1250 init_ltime(struct nvbios_init *init)
1251 {
1252         struct nvkm_bios *bios = init->bios;
1253         u16 msec = nv_ro16(bios, init->offset + 1);
1254
1255         trace("LTIME\t0x%04x\n", msec);
1256         init->offset += 3;
1257
1258         if (init_exec(init))
1259                 mdelay(msec);
1260 }
1261
1262 /**
1263  * INIT_ZM_REG_SEQUENCE - opcode 0x58
1264  *
1265  */
1266 static void
1267 init_zm_reg_sequence(struct nvbios_init *init)
1268 {
1269         struct nvkm_bios *bios = init->bios;
1270         u32 base = nv_ro32(bios, init->offset + 1);
1271         u8 count = nv_ro08(bios, init->offset + 5);
1272
1273         trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1274         init->offset += 6;
1275
1276         while (count--) {
1277                 u32 data = nv_ro32(bios, init->offset);
1278
1279                 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1280                 init->offset += 4;
1281
1282                 init_wr32(init, base, data);
1283                 base += 4;
1284         }
1285 }
1286
1287 /**
1288  * INIT_SUB_DIRECT - opcode 0x5b
1289  *
1290  */
1291 static void
1292 init_sub_direct(struct nvbios_init *init)
1293 {
1294         struct nvkm_bios *bios = init->bios;
1295         u16 addr = nv_ro16(bios, init->offset + 1);
1296         u16 save;
1297
1298         trace("SUB_DIRECT\t0x%04x\n", addr);
1299
1300         if (init_exec(init)) {
1301                 save = init->offset;
1302                 init->offset = addr;
1303                 if (nvbios_exec(init)) {
1304                         error("error parsing sub-table\n");
1305                         return;
1306                 }
1307                 init->offset = save;
1308         }
1309
1310         init->offset += 3;
1311 }
1312
1313 /**
1314  * INIT_JUMP - opcode 0x5c
1315  *
1316  */
1317 static void
1318 init_jump(struct nvbios_init *init)
1319 {
1320         struct nvkm_bios *bios = init->bios;
1321         u16 offset = nv_ro16(bios, init->offset + 1);
1322
1323         trace("JUMP\t0x%04x\n", offset);
1324
1325         if (init_exec(init))
1326                 init->offset = offset;
1327         else
1328                 init->offset += 3;
1329 }
1330
1331 /**
1332  * INIT_I2C_IF - opcode 0x5e
1333  *
1334  */
1335 static void
1336 init_i2c_if(struct nvbios_init *init)
1337 {
1338         struct nvkm_bios *bios = init->bios;
1339         u8 index = nv_ro08(bios, init->offset + 1);
1340         u8  addr = nv_ro08(bios, init->offset + 2);
1341         u8   reg = nv_ro08(bios, init->offset + 3);
1342         u8  mask = nv_ro08(bios, init->offset + 4);
1343         u8  data = nv_ro08(bios, init->offset + 5);
1344         u8 value;
1345
1346         trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1347               index, addr, reg, mask, data);
1348         init->offset += 6;
1349         init_exec_force(init, true);
1350
1351         value = init_rdi2cr(init, index, addr, reg);
1352         if ((value & mask) != data)
1353                 init_exec_set(init, false);
1354
1355         init_exec_force(init, false);
1356 }
1357
1358 /**
1359  * INIT_COPY_NV_REG - opcode 0x5f
1360  *
1361  */
1362 static void
1363 init_copy_nv_reg(struct nvbios_init *init)
1364 {
1365         struct nvkm_bios *bios = init->bios;
1366         u32  sreg = nv_ro32(bios, init->offset + 1);
1367         u8  shift = nv_ro08(bios, init->offset + 5);
1368         u32 smask = nv_ro32(bios, init->offset + 6);
1369         u32  sxor = nv_ro32(bios, init->offset + 10);
1370         u32  dreg = nv_ro32(bios, init->offset + 14);
1371         u32 dmask = nv_ro32(bios, init->offset + 18);
1372         u32 data;
1373
1374         trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1375               "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1376               dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1377               (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1378         init->offset += 22;
1379
1380         data = init_shift(init_rd32(init, sreg), shift);
1381         init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1382 }
1383
1384 /**
1385  * INIT_ZM_INDEX_IO - opcode 0x62
1386  *
1387  */
1388 static void
1389 init_zm_index_io(struct nvbios_init *init)
1390 {
1391         struct nvkm_bios *bios = init->bios;
1392         u16 port = nv_ro16(bios, init->offset + 1);
1393         u8 index = nv_ro08(bios, init->offset + 3);
1394         u8  data = nv_ro08(bios, init->offset + 4);
1395
1396         trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1397         init->offset += 5;
1398
1399         init_wrvgai(init, port, index, data);
1400 }
1401
1402 /**
1403  * INIT_COMPUTE_MEM - opcode 0x63
1404  *
1405  */
1406 static void
1407 init_compute_mem(struct nvbios_init *init)
1408 {
1409         struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
1410
1411         trace("COMPUTE_MEM\n");
1412         init->offset += 1;
1413
1414         init_exec_force(init, true);
1415         if (init_exec(init) && devinit->meminit)
1416                 devinit->meminit(devinit);
1417         init_exec_force(init, false);
1418 }
1419
1420 /**
1421  * INIT_RESET - opcode 0x65
1422  *
1423  */
1424 static void
1425 init_reset(struct nvbios_init *init)
1426 {
1427         struct nvkm_bios *bios = init->bios;
1428         u32   reg = nv_ro32(bios, init->offset + 1);
1429         u32 data1 = nv_ro32(bios, init->offset + 5);
1430         u32 data2 = nv_ro32(bios, init->offset + 9);
1431         u32 savepci19;
1432
1433         trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1434         init->offset += 13;
1435         init_exec_force(init, true);
1436
1437         savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1438         init_wr32(init, reg, data1);
1439         udelay(10);
1440         init_wr32(init, reg, data2);
1441         init_wr32(init, 0x00184c, savepci19);
1442         init_mask(init, 0x001850, 0x00000001, 0x00000000);
1443
1444         init_exec_force(init, false);
1445 }
1446
1447 /**
1448  * INIT_CONFIGURE_MEM - opcode 0x66
1449  *
1450  */
1451 static u16
1452 init_configure_mem_clk(struct nvbios_init *init)
1453 {
1454         u16 mdata = bmp_mem_init_table(init->bios);
1455         if (mdata)
1456                 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1457         return mdata;
1458 }
1459
1460 static void
1461 init_configure_mem(struct nvbios_init *init)
1462 {
1463         struct nvkm_bios *bios = init->bios;
1464         u16 mdata, sdata;
1465         u32 addr, data;
1466
1467         trace("CONFIGURE_MEM\n");
1468         init->offset += 1;
1469
1470         if (bios->version.major > 2) {
1471                 init_done(init);
1472                 return;
1473         }
1474         init_exec_force(init, true);
1475
1476         mdata = init_configure_mem_clk(init);
1477         sdata = bmp_sdr_seq_table(bios);
1478         if (nv_ro08(bios, mdata) & 0x01)
1479                 sdata = bmp_ddr_seq_table(bios);
1480         mdata += 6; /* skip to data */
1481
1482         data = init_rdvgai(init, 0x03c4, 0x01);
1483         init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1484
1485         for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1486                 switch (addr) {
1487                 case 0x10021c: /* CKE_NORMAL */
1488                 case 0x1002d0: /* CMD_REFRESH */
1489                 case 0x1002d4: /* CMD_PRECHARGE */
1490                         data = 0x00000001;
1491                         break;
1492                 default:
1493                         data = nv_ro32(bios, mdata);
1494                         mdata += 4;
1495                         if (data == 0xffffffff)
1496                                 continue;
1497                         break;
1498                 }
1499
1500                 init_wr32(init, addr, data);
1501         }
1502
1503         init_exec_force(init, false);
1504 }
1505
1506 /**
1507  * INIT_CONFIGURE_CLK - opcode 0x67
1508  *
1509  */
1510 static void
1511 init_configure_clk(struct nvbios_init *init)
1512 {
1513         struct nvkm_bios *bios = init->bios;
1514         u16 mdata, clock;
1515
1516         trace("CONFIGURE_CLK\n");
1517         init->offset += 1;
1518
1519         if (bios->version.major > 2) {
1520                 init_done(init);
1521                 return;
1522         }
1523         init_exec_force(init, true);
1524
1525         mdata = init_configure_mem_clk(init);
1526
1527         /* NVPLL */
1528         clock = nv_ro16(bios, mdata + 4) * 10;
1529         init_prog_pll(init, 0x680500, clock);
1530
1531         /* MPLL */
1532         clock = nv_ro16(bios, mdata + 2) * 10;
1533         if (nv_ro08(bios, mdata) & 0x01)
1534                 clock *= 2;
1535         init_prog_pll(init, 0x680504, clock);
1536
1537         init_exec_force(init, false);
1538 }
1539
1540 /**
1541  * INIT_CONFIGURE_PREINIT - opcode 0x68
1542  *
1543  */
1544 static void
1545 init_configure_preinit(struct nvbios_init *init)
1546 {
1547         struct nvkm_bios *bios = init->bios;
1548         u32 strap;
1549
1550         trace("CONFIGURE_PREINIT\n");
1551         init->offset += 1;
1552
1553         if (bios->version.major > 2) {
1554                 init_done(init);
1555                 return;
1556         }
1557         init_exec_force(init, true);
1558
1559         strap = init_rd32(init, 0x101000);
1560         strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1561         init_wrvgai(init, 0x03d4, 0x3c, strap);
1562
1563         init_exec_force(init, false);
1564 }
1565
1566 /**
1567  * INIT_IO - opcode 0x69
1568  *
1569  */
1570 static void
1571 init_io(struct nvbios_init *init)
1572 {
1573         struct nvkm_bios *bios = init->bios;
1574         u16 port = nv_ro16(bios, init->offset + 1);
1575         u8  mask = nv_ro16(bios, init->offset + 3);
1576         u8  data = nv_ro16(bios, init->offset + 4);
1577         u8 value;
1578
1579         trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1580         init->offset += 5;
1581
1582         /* ummm.. yes.. should really figure out wtf this is and why it's
1583          * needed some day..  it's almost certainly wrong, but, it also
1584          * somehow makes things work...
1585          */
1586         if (nv_device(init->bios)->card_type >= NV_50 &&
1587             port == 0x03c3 && data == 0x01) {
1588                 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1589                 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1590                 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1591                 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1592                 mdelay(10);
1593                 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1594                 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1595                 init_wr32(init, 0x614100, 0x00800018);
1596                 init_wr32(init, 0x614900, 0x00800018);
1597                 mdelay(10);
1598                 init_wr32(init, 0x614100, 0x10000018);
1599                 init_wr32(init, 0x614900, 0x10000018);
1600         }
1601
1602         value = init_rdport(init, port) & mask;
1603         init_wrport(init, port, data | value);
1604 }
1605
1606 /**
1607  * INIT_SUB - opcode 0x6b
1608  *
1609  */
1610 static void
1611 init_sub(struct nvbios_init *init)
1612 {
1613         struct nvkm_bios *bios = init->bios;
1614         u8 index = nv_ro08(bios, init->offset + 1);
1615         u16 addr, save;
1616
1617         trace("SUB\t0x%02x\n", index);
1618
1619         addr = init_script(bios, index);
1620         if (addr && init_exec(init)) {
1621                 save = init->offset;
1622                 init->offset = addr;
1623                 if (nvbios_exec(init)) {
1624                         error("error parsing sub-table\n");
1625                         return;
1626                 }
1627                 init->offset = save;
1628         }
1629
1630         init->offset += 2;
1631 }
1632
1633 /**
1634  * INIT_RAM_CONDITION - opcode 0x6d
1635  *
1636  */
1637 static void
1638 init_ram_condition(struct nvbios_init *init)
1639 {
1640         struct nvkm_bios *bios = init->bios;
1641         u8  mask = nv_ro08(bios, init->offset + 1);
1642         u8 value = nv_ro08(bios, init->offset + 2);
1643
1644         trace("RAM_CONDITION\t"
1645               "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1646         init->offset += 3;
1647
1648         if ((init_rd32(init, 0x100000) & mask) != value)
1649                 init_exec_set(init, false);
1650 }
1651
1652 /**
1653  * INIT_NV_REG - opcode 0x6e
1654  *
1655  */
1656 static void
1657 init_nv_reg(struct nvbios_init *init)
1658 {
1659         struct nvkm_bios *bios = init->bios;
1660         u32  reg = nv_ro32(bios, init->offset + 1);
1661         u32 mask = nv_ro32(bios, init->offset + 5);
1662         u32 data = nv_ro32(bios, init->offset + 9);
1663
1664         trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1665         init->offset += 13;
1666
1667         init_mask(init, reg, ~mask, data);
1668 }
1669
1670 /**
1671  * INIT_MACRO - opcode 0x6f
1672  *
1673  */
1674 static void
1675 init_macro(struct nvbios_init *init)
1676 {
1677         struct nvkm_bios *bios = init->bios;
1678         u8  macro = nv_ro08(bios, init->offset + 1);
1679         u16 table;
1680
1681         trace("MACRO\t0x%02x\n", macro);
1682
1683         table = init_macro_table(init);
1684         if (table) {
1685                 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1686                 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1687                 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1688                 init_wr32(init, addr, data);
1689         }
1690
1691         init->offset += 2;
1692 }
1693
1694 /**
1695  * INIT_RESUME - opcode 0x72
1696  *
1697  */
1698 static void
1699 init_resume(struct nvbios_init *init)
1700 {
1701         trace("RESUME\n");
1702         init->offset += 1;
1703         init_exec_set(init, true);
1704 }
1705
1706 /**
1707  * INIT_TIME - opcode 0x74
1708  *
1709  */
1710 static void
1711 init_time(struct nvbios_init *init)
1712 {
1713         struct nvkm_bios *bios = init->bios;
1714         u16 usec = nv_ro16(bios, init->offset + 1);
1715
1716         trace("TIME\t0x%04x\n", usec);
1717         init->offset += 3;
1718
1719         if (init_exec(init)) {
1720                 if (usec < 1000)
1721                         udelay(usec);
1722                 else
1723                         mdelay((usec + 900) / 1000);
1724         }
1725 }
1726
1727 /**
1728  * INIT_CONDITION - opcode 0x75
1729  *
1730  */
1731 static void
1732 init_condition(struct nvbios_init *init)
1733 {
1734         struct nvkm_bios *bios = init->bios;
1735         u8 cond = nv_ro08(bios, init->offset + 1);
1736
1737         trace("CONDITION\t0x%02x\n", cond);
1738         init->offset += 2;
1739
1740         if (!init_condition_met(init, cond))
1741                 init_exec_set(init, false);
1742 }
1743
1744 /**
1745  * INIT_IO_CONDITION - opcode 0x76
1746  *
1747  */
1748 static void
1749 init_io_condition(struct nvbios_init *init)
1750 {
1751         struct nvkm_bios *bios = init->bios;
1752         u8 cond = nv_ro08(bios, init->offset + 1);
1753
1754         trace("IO_CONDITION\t0x%02x\n", cond);
1755         init->offset += 2;
1756
1757         if (!init_io_condition_met(init, cond))
1758                 init_exec_set(init, false);
1759 }
1760
1761 /**
1762  * INIT_INDEX_IO - opcode 0x78
1763  *
1764  */
1765 static void
1766 init_index_io(struct nvbios_init *init)
1767 {
1768         struct nvkm_bios *bios = init->bios;
1769         u16 port = nv_ro16(bios, init->offset + 1);
1770         u8 index = nv_ro16(bios, init->offset + 3);
1771         u8  mask = nv_ro08(bios, init->offset + 4);
1772         u8  data = nv_ro08(bios, init->offset + 5);
1773         u8 value;
1774
1775         trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1776               port, index, mask, data);
1777         init->offset += 6;
1778
1779         value = init_rdvgai(init, port, index) & mask;
1780         init_wrvgai(init, port, index, data | value);
1781 }
1782
1783 /**
1784  * INIT_PLL - opcode 0x79
1785  *
1786  */
1787 static void
1788 init_pll(struct nvbios_init *init)
1789 {
1790         struct nvkm_bios *bios = init->bios;
1791         u32  reg = nv_ro32(bios, init->offset + 1);
1792         u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1793
1794         trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1795         init->offset += 7;
1796
1797         init_prog_pll(init, reg, freq);
1798 }
1799
1800 /**
1801  * INIT_ZM_REG - opcode 0x7a
1802  *
1803  */
1804 static void
1805 init_zm_reg(struct nvbios_init *init)
1806 {
1807         struct nvkm_bios *bios = init->bios;
1808         u32 addr = nv_ro32(bios, init->offset + 1);
1809         u32 data = nv_ro32(bios, init->offset + 5);
1810
1811         trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1812         init->offset += 9;
1813
1814         if (addr == 0x000200)
1815                 data |= 0x00000001;
1816
1817         init_wr32(init, addr, data);
1818 }
1819
1820 /**
1821  * INIT_RAM_RESTRICT_PLL - opcde 0x87
1822  *
1823  */
1824 static void
1825 init_ram_restrict_pll(struct nvbios_init *init)
1826 {
1827         struct nvkm_bios *bios = init->bios;
1828         u8  type = nv_ro08(bios, init->offset + 1);
1829         u8 count = init_ram_restrict_group_count(init);
1830         u8 strap = init_ram_restrict(init);
1831         u8 cconf;
1832
1833         trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1834         init->offset += 2;
1835
1836         for (cconf = 0; cconf < count; cconf++) {
1837                 u32 freq = nv_ro32(bios, init->offset);
1838
1839                 if (cconf == strap) {
1840                         trace("%dkHz *\n", freq);
1841                         init_prog_pll(init, type, freq);
1842                 } else {
1843                         trace("%dkHz\n", freq);
1844                 }
1845
1846                 init->offset += 4;
1847         }
1848 }
1849
1850 /**
1851  * INIT_GPIO - opcode 0x8e
1852  *
1853  */
1854 static void
1855 init_gpio(struct nvbios_init *init)
1856 {
1857         struct nvkm_gpio *gpio = nvkm_gpio(init->bios);
1858
1859         trace("GPIO\n");
1860         init->offset += 1;
1861
1862         if (init_exec(init) && gpio && gpio->reset)
1863                 gpio->reset(gpio, DCB_GPIO_UNUSED);
1864 }
1865
1866 /**
1867  * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1868  *
1869  */
1870 static void
1871 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1872 {
1873         struct nvkm_bios *bios = init->bios;
1874         u32 addr = nv_ro32(bios, init->offset + 1);
1875         u8  incr = nv_ro08(bios, init->offset + 5);
1876         u8   num = nv_ro08(bios, init->offset + 6);
1877         u8 count = init_ram_restrict_group_count(init);
1878         u8 index = init_ram_restrict(init);
1879         u8 i, j;
1880
1881         trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1882               "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1883         init->offset += 7;
1884
1885         for (i = 0; i < num; i++) {
1886                 trace("\tR[0x%06x] = {\n", addr);
1887                 for (j = 0; j < count; j++) {
1888                         u32 data = nv_ro32(bios, init->offset);
1889
1890                         if (j == index) {
1891                                 trace("\t\t0x%08x *\n", data);
1892                                 init_wr32(init, addr, data);
1893                         } else {
1894                                 trace("\t\t0x%08x\n", data);
1895                         }
1896
1897                         init->offset += 4;
1898                 }
1899                 trace("\t}\n");
1900                 addr += incr;
1901         }
1902 }
1903
1904 /**
1905  * INIT_COPY_ZM_REG - opcode 0x90
1906  *
1907  */
1908 static void
1909 init_copy_zm_reg(struct nvbios_init *init)
1910 {
1911         struct nvkm_bios *bios = init->bios;
1912         u32 sreg = nv_ro32(bios, init->offset + 1);
1913         u32 dreg = nv_ro32(bios, init->offset + 5);
1914
1915         trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1916         init->offset += 9;
1917
1918         init_wr32(init, dreg, init_rd32(init, sreg));
1919 }
1920
1921 /**
1922  * INIT_ZM_REG_GROUP - opcode 0x91
1923  *
1924  */
1925 static void
1926 init_zm_reg_group(struct nvbios_init *init)
1927 {
1928         struct nvkm_bios *bios = init->bios;
1929         u32 addr = nv_ro32(bios, init->offset + 1);
1930         u8 count = nv_ro08(bios, init->offset + 5);
1931
1932         trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1933         init->offset += 6;
1934
1935         while (count--) {
1936                 u32 data = nv_ro32(bios, init->offset);
1937                 trace("\t0x%08x\n", data);
1938                 init_wr32(init, addr, data);
1939                 init->offset += 4;
1940         }
1941 }
1942
1943 /**
1944  * INIT_XLAT - opcode 0x96
1945  *
1946  */
1947 static void
1948 init_xlat(struct nvbios_init *init)
1949 {
1950         struct nvkm_bios *bios = init->bios;
1951         u32 saddr = nv_ro32(bios, init->offset + 1);
1952         u8 sshift = nv_ro08(bios, init->offset + 5);
1953         u8  smask = nv_ro08(bios, init->offset + 6);
1954         u8  index = nv_ro08(bios, init->offset + 7);
1955         u32 daddr = nv_ro32(bios, init->offset + 8);
1956         u32 dmask = nv_ro32(bios, init->offset + 12);
1957         u8  shift = nv_ro08(bios, init->offset + 16);
1958         u32 data;
1959
1960         trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1961               "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1962               daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1963               (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1964         init->offset += 17;
1965
1966         data = init_shift(init_rd32(init, saddr), sshift) & smask;
1967         data = init_xlat_(init, index, data) << shift;
1968         init_mask(init, daddr, ~dmask, data);
1969 }
1970
1971 /**
1972  * INIT_ZM_MASK_ADD - opcode 0x97
1973  *
1974  */
1975 static void
1976 init_zm_mask_add(struct nvbios_init *init)
1977 {
1978         struct nvkm_bios *bios = init->bios;
1979         u32 addr = nv_ro32(bios, init->offset + 1);
1980         u32 mask = nv_ro32(bios, init->offset + 5);
1981         u32  add = nv_ro32(bios, init->offset + 9);
1982         u32 data;
1983
1984         trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1985         init->offset += 13;
1986
1987         data =  init_rd32(init, addr);
1988         data = (data & mask) | ((data + add) & ~mask);
1989         init_wr32(init, addr, data);
1990 }
1991
1992 /**
1993  * INIT_AUXCH - opcode 0x98
1994  *
1995  */
1996 static void
1997 init_auxch(struct nvbios_init *init)
1998 {
1999         struct nvkm_bios *bios = init->bios;
2000         u32 addr = nv_ro32(bios, init->offset + 1);
2001         u8 count = nv_ro08(bios, init->offset + 5);
2002
2003         trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2004         init->offset += 6;
2005
2006         while (count--) {
2007                 u8 mask = nv_ro08(bios, init->offset + 0);
2008                 u8 data = nv_ro08(bios, init->offset + 1);
2009                 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2010                 mask = init_rdauxr(init, addr) & mask;
2011                 init_wrauxr(init, addr, mask | data);
2012                 init->offset += 2;
2013         }
2014 }
2015
2016 /**
2017  * INIT_AUXCH - opcode 0x99
2018  *
2019  */
2020 static void
2021 init_zm_auxch(struct nvbios_init *init)
2022 {
2023         struct nvkm_bios *bios = init->bios;
2024         u32 addr = nv_ro32(bios, init->offset + 1);
2025         u8 count = nv_ro08(bios, init->offset + 5);
2026
2027         trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2028         init->offset += 6;
2029
2030         while (count--) {
2031                 u8 data = nv_ro08(bios, init->offset + 0);
2032                 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2033                 init_wrauxr(init, addr, data);
2034                 init->offset += 1;
2035         }
2036 }
2037
2038 /**
2039  * INIT_I2C_LONG_IF - opcode 0x9a
2040  *
2041  */
2042 static void
2043 init_i2c_long_if(struct nvbios_init *init)
2044 {
2045         struct nvkm_bios *bios = init->bios;
2046         u8 index = nv_ro08(bios, init->offset + 1);
2047         u8  addr = nv_ro08(bios, init->offset + 2) >> 1;
2048         u8 reglo = nv_ro08(bios, init->offset + 3);
2049         u8 reghi = nv_ro08(bios, init->offset + 4);
2050         u8  mask = nv_ro08(bios, init->offset + 5);
2051         u8  data = nv_ro08(bios, init->offset + 6);
2052         struct nvkm_i2c_port *port;
2053
2054         trace("I2C_LONG_IF\t"
2055               "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2056               index, addr, reglo, reghi, mask, data);
2057         init->offset += 7;
2058
2059         port = init_i2c(init, index);
2060         if (port) {
2061                 u8 i[2] = { reghi, reglo };
2062                 u8 o[1] = {};
2063                 struct i2c_msg msg[] = {
2064                         { .addr = addr, .flags = 0, .len = 2, .buf = i },
2065                         { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2066                 };
2067                 int ret;
2068
2069                 ret = i2c_transfer(&port->adapter, msg, 2);
2070                 if (ret == 2 && ((o[0] & mask) == data))
2071                         return;
2072         }
2073
2074         init_exec_set(init, false);
2075 }
2076
2077 /**
2078  * INIT_GPIO_NE - opcode 0xa9
2079  *
2080  */
2081 static void
2082 init_gpio_ne(struct nvbios_init *init)
2083 {
2084         struct nvkm_bios *bios = init->bios;
2085         struct nvkm_gpio *gpio = nvkm_gpio(bios);
2086         struct dcb_gpio_func func;
2087         u8 count = nv_ro08(bios, init->offset + 1);
2088         u8 idx = 0, ver, len;
2089         u16 data, i;
2090
2091         trace("GPIO_NE\t");
2092         init->offset += 2;
2093
2094         for (i = init->offset; i < init->offset + count; i++)
2095                 cont("0x%02x ", nv_ro08(bios, i));
2096         cont("\n");
2097
2098         while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2099                 if (func.func != DCB_GPIO_UNUSED) {
2100                         for (i = init->offset; i < init->offset + count; i++) {
2101                                 if (func.func == nv_ro08(bios, i))
2102                                         break;
2103                         }
2104
2105                         trace("\tFUNC[0x%02x]", func.func);
2106                         if (i == (init->offset + count)) {
2107                                 cont(" *");
2108                                 if (init_exec(init) && gpio && gpio->reset)
2109                                         gpio->reset(gpio, func.func);
2110                         }
2111                         cont("\n");
2112                 }
2113         }
2114
2115         init->offset += count;
2116 }
2117
2118 static struct nvbios_init_opcode {
2119         void (*exec)(struct nvbios_init *);
2120 } init_opcode[] = {
2121         [0x32] = { init_io_restrict_prog },
2122         [0x33] = { init_repeat },
2123         [0x34] = { init_io_restrict_pll },
2124         [0x36] = { init_end_repeat },
2125         [0x37] = { init_copy },
2126         [0x38] = { init_not },
2127         [0x39] = { init_io_flag_condition },
2128         [0x3a] = { init_dp_condition },
2129         [0x3b] = { init_io_mask_or },
2130         [0x3c] = { init_io_or },
2131         [0x47] = { init_andn_reg },
2132         [0x48] = { init_or_reg },
2133         [0x49] = { init_idx_addr_latched },
2134         [0x4a] = { init_io_restrict_pll2 },
2135         [0x4b] = { init_pll2 },
2136         [0x4c] = { init_i2c_byte },
2137         [0x4d] = { init_zm_i2c_byte },
2138         [0x4e] = { init_zm_i2c },
2139         [0x4f] = { init_tmds },
2140         [0x50] = { init_zm_tmds_group },
2141         [0x51] = { init_cr_idx_adr_latch },
2142         [0x52] = { init_cr },
2143         [0x53] = { init_zm_cr },
2144         [0x54] = { init_zm_cr_group },
2145         [0x56] = { init_condition_time },
2146         [0x57] = { init_ltime },
2147         [0x58] = { init_zm_reg_sequence },
2148         [0x5b] = { init_sub_direct },
2149         [0x5c] = { init_jump },
2150         [0x5e] = { init_i2c_if },
2151         [0x5f] = { init_copy_nv_reg },
2152         [0x62] = { init_zm_index_io },
2153         [0x63] = { init_compute_mem },
2154         [0x65] = { init_reset },
2155         [0x66] = { init_configure_mem },
2156         [0x67] = { init_configure_clk },
2157         [0x68] = { init_configure_preinit },
2158         [0x69] = { init_io },
2159         [0x6b] = { init_sub },
2160         [0x6d] = { init_ram_condition },
2161         [0x6e] = { init_nv_reg },
2162         [0x6f] = { init_macro },
2163         [0x71] = { init_done },
2164         [0x72] = { init_resume },
2165         [0x74] = { init_time },
2166         [0x75] = { init_condition },
2167         [0x76] = { init_io_condition },
2168         [0x78] = { init_index_io },
2169         [0x79] = { init_pll },
2170         [0x7a] = { init_zm_reg },
2171         [0x87] = { init_ram_restrict_pll },
2172         [0x8c] = { init_reserved },
2173         [0x8d] = { init_reserved },
2174         [0x8e] = { init_gpio },
2175         [0x8f] = { init_ram_restrict_zm_reg_group },
2176         [0x90] = { init_copy_zm_reg },
2177         [0x91] = { init_zm_reg_group },
2178         [0x92] = { init_reserved },
2179         [0x96] = { init_xlat },
2180         [0x97] = { init_zm_mask_add },
2181         [0x98] = { init_auxch },
2182         [0x99] = { init_zm_auxch },
2183         [0x9a] = { init_i2c_long_if },
2184         [0xa9] = { init_gpio_ne },
2185         [0xaa] = { init_reserved },
2186 };
2187
2188 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2189
2190 int
2191 nvbios_exec(struct nvbios_init *init)
2192 {
2193         init->nested++;
2194         while (init->offset) {
2195                 u8 opcode = nv_ro08(init->bios, init->offset);
2196                 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2197                         error("unknown opcode 0x%02x\n", opcode);
2198                         return -EINVAL;
2199                 }
2200
2201                 init_opcode[opcode].exec(init);
2202         }
2203         init->nested--;
2204         return 0;
2205 }
2206
2207 int
2208 nvbios_init(struct nvkm_subdev *subdev, bool execute)
2209 {
2210         struct nvkm_bios *bios = nvkm_bios(subdev);
2211         int ret = 0;
2212         int i = -1;
2213         u16 data;
2214
2215         if (execute)
2216                 nv_info(bios, "running init tables\n");
2217         while (!ret && (data = (init_script(bios, ++i)))) {
2218                 struct nvbios_init init = {
2219                         .subdev = subdev,
2220                         .bios = bios,
2221                         .offset = data,
2222                         .outp = NULL,
2223                         .crtc = -1,
2224                         .execute = execute ? 1 : 0,
2225                 };
2226
2227                 ret = nvbios_exec(&init);
2228         }
2229
2230         /* the vbios parser will run this right after the normal init
2231          * tables, whereas the binary driver appears to run it later.
2232          */
2233         if (!ret && (data = init_unknown_script(bios))) {
2234                 struct nvbios_init init = {
2235                         .subdev = subdev,
2236                         .bios = bios,
2237                         .offset = data,
2238                         .outp = NULL,
2239                         .crtc = -1,
2240                         .execute = execute ? 1 : 0,
2241                 };
2242
2243                 ret = nvbios_exec(&init);
2244         }
2245
2246         return ret;
2247 }