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drm/nouveau/clk/gk20a: only restore divider to 1:1 if needed
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / gk20a.c
1 /*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 *
22 * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
23 *
24 */
25 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
26 #include "priv.h"
27
28 #include <core/tegra.h>
29 #include <subdev/timer.h>
30
31 #define KHZ (1000)
32 #define MHZ (KHZ * 1000)
33
34 #define MASK(w) ((1 << w) - 1)
35
36 #define SYS_GPCPLL_CFG_BASE 0x00137000
37 #define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800
38
39 #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
40 #define GPCPLL_CFG_ENABLE BIT(0)
41 #define GPCPLL_CFG_IDDQ BIT(1)
42 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4)
43 #define GPCPLL_CFG_LOCK BIT(17)
44
45 #define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4)
46 #define GPCPLL_COEFF_M_SHIFT 0
47 #define GPCPLL_COEFF_M_WIDTH 8
48 #define GPCPLL_COEFF_N_SHIFT 8
49 #define GPCPLL_COEFF_N_WIDTH 8
50 #define GPCPLL_COEFF_P_SHIFT 16
51 #define GPCPLL_COEFF_P_WIDTH 6
52
53 #define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc)
54 #define GPCPLL_CFG2_SETUP2_SHIFT 16
55 #define GPCPLL_CFG2_PLL_STEPA_SHIFT 24
56
57 #define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)
58 #define GPCPLL_CFG3_PLL_STEPB_SHIFT 16
59
60 #define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)
61 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0
62 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8
63 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16
64 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22
65 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31
66
67 #define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100)
68 #define SEL_VCO_GPC2CLK_OUT_SHIFT 0
69
70 #define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)
71 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1
72 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31
73 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1
74 #define GPC2CLK_OUT_VCODIV_WIDTH 6
75 #define GPC2CLK_OUT_VCODIV_SHIFT 8
76 #define GPC2CLK_OUT_VCODIV1 0
77 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
78 GPC2CLK_OUT_VCODIV_SHIFT)
79 #define GPC2CLK_OUT_BYPDIV_WIDTH 6
80 #define GPC2CLK_OUT_BYPDIV_SHIFT 0
81 #define GPC2CLK_OUT_BYPDIV31 0x3c
82 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
83 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
84 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
85 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
86 #define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
87 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
88 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
89 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
90
91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0)
92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24
93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
94 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
95
96 static const u8 pl_to_div[] = {
97 /* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
98 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
99 };
100
101 /* All frequencies in Khz */
102 struct gk20a_clk_pllg_params {
103 u32 min_vco, max_vco;
104 u32 min_u, max_u;
105 u32 min_m, max_m;
106 u32 min_n, max_n;
107 u32 min_pl, max_pl;
108 };
109
110 static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
111 .min_vco = 1000000, .max_vco = 2064000,
112 .min_u = 12000, .max_u = 38000,
113 .min_m = 1, .max_m = 255,
114 .min_n = 8, .max_n = 255,
115 .min_pl = 1, .max_pl = 32,
116 };
117
118 struct gk20a_clk {
119 struct nvkm_clk base;
120 const struct gk20a_clk_pllg_params *params;
121 u32 m, n, pl;
122 u32 parent_rate;
123 };
124
125 static void
126 gk20a_pllg_read_mnp(struct gk20a_clk *clk)
127 {
128 struct nvkm_device *device = clk->base.subdev.device;
129 u32 val;
130
131 val = nvkm_rd32(device, GPCPLL_COEFF);
132 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
133 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
134 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
135 }
136
137 static u32
138 gk20a_pllg_calc_rate(struct gk20a_clk *clk)
139 {
140 u32 rate;
141 u32 divider;
142
143 rate = clk->parent_rate * clk->n;
144 divider = clk->m * pl_to_div[clk->pl];
145
146 return rate / divider / 2;
147 }
148
149 static int
150 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
151 {
152 struct nvkm_subdev *subdev = &clk->base.subdev;
153 u32 target_clk_f, ref_clk_f, target_freq;
154 u32 min_vco_f, max_vco_f;
155 u32 low_pl, high_pl, best_pl;
156 u32 target_vco_f;
157 u32 best_m, best_n;
158 u32 best_delta = ~0;
159 u32 pl;
160
161 target_clk_f = rate * 2 / KHZ;
162 ref_clk_f = clk->parent_rate / KHZ;
163
164 max_vco_f = clk->params->max_vco;
165 min_vco_f = clk->params->min_vco;
166 best_m = clk->params->max_m;
167 best_n = clk->params->min_n;
168 best_pl = clk->params->min_pl;
169
170 target_vco_f = target_clk_f + target_clk_f / 50;
171 if (max_vco_f < target_vco_f)
172 max_vco_f = target_vco_f;
173
174 /* min_pl <= high_pl <= max_pl */
175 high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
176 high_pl = min(high_pl, clk->params->max_pl);
177 high_pl = max(high_pl, clk->params->min_pl);
178
179 /* min_pl <= low_pl <= max_pl */
180 low_pl = min_vco_f / target_vco_f;
181 low_pl = min(low_pl, clk->params->max_pl);
182 low_pl = max(low_pl, clk->params->min_pl);
183
184 /* Find Indices of high_pl and low_pl */
185 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
186 if (pl_to_div[pl] >= low_pl) {
187 low_pl = pl;
188 break;
189 }
190 }
191 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
192 if (pl_to_div[pl] >= high_pl) {
193 high_pl = pl;
194 break;
195 }
196 }
197
198 nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
199 pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
200
201 /* Select lowest possible VCO */
202 for (pl = low_pl; pl <= high_pl; pl++) {
203 u32 m, n, n2;
204
205 target_vco_f = target_clk_f * pl_to_div[pl];
206 for (m = clk->params->min_m; m <= clk->params->max_m; m++) {
207 u32 u_f, vco_f;
208
209 u_f = ref_clk_f / m;
210
211 if (u_f < clk->params->min_u)
212 break;
213 if (u_f > clk->params->max_u)
214 continue;
215
216 n = (target_vco_f * m) / ref_clk_f;
217 n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
218
219 if (n > clk->params->max_n)
220 break;
221
222 for (; n <= n2; n++) {
223 if (n < clk->params->min_n)
224 continue;
225 if (n > clk->params->max_n)
226 break;
227
228 vco_f = ref_clk_f * n / m;
229
230 if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
231 u32 delta, lwv;
232
233 lwv = (vco_f + (pl_to_div[pl] / 2))
234 / pl_to_div[pl];
235 delta = abs(lwv - target_clk_f);
236
237 if (delta < best_delta) {
238 best_delta = delta;
239 best_m = m;
240 best_n = n;
241 best_pl = pl;
242
243 if (best_delta == 0)
244 goto found_match;
245 }
246 }
247 }
248 }
249 }
250
251 found_match:
252 WARN_ON(best_delta == ~0);
253
254 if (best_delta != 0)
255 nvkm_debug(subdev,
256 "no best match for target @ %dMHz on gpc_pll",
257 target_clk_f / KHZ);
258
259 clk->m = best_m;
260 clk->n = best_n;
261 clk->pl = best_pl;
262
263 target_freq = gk20a_pllg_calc_rate(clk);
264
265 nvkm_debug(subdev,
266 "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
267 target_freq / MHZ, clk->m, clk->n, clk->pl,
268 pl_to_div[clk->pl]);
269 return 0;
270 }
271
272 static int
273 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
274 {
275 struct nvkm_subdev *subdev = &clk->base.subdev;
276 struct nvkm_device *device = subdev->device;
277 u32 val;
278 int ramp_timeout;
279
280 /* get old coefficients */
281 val = nvkm_rd32(device, GPCPLL_COEFF);
282 /* do nothing if NDIV is the same */
283 if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH)))
284 return 0;
285
286 /* setup */
287 nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
288 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT);
289 nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
290 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT);
291
292 /* pll slowdown mode */
293 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
294 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
295 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
296
297 /* new ndiv ready for ramp */
298 val = nvkm_rd32(device, GPCPLL_COEFF);
299 val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT);
300 val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
301 udelay(1);
302 nvkm_wr32(device, GPCPLL_COEFF, val);
303
304 /* dynamic ramp to new ndiv */
305 val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
306 val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT;
307 udelay(1);
308 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val);
309
310 for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) {
311 udelay(1);
312 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG);
313 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK)
314 break;
315 }
316
317 /* exit slowdown mode */
318 nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
319 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
320 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
321 nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
322
323 if (ramp_timeout <= 0) {
324 nvkm_error(subdev, "gpcpll dynamic ramp timeout\n");
325 return -ETIMEDOUT;
326 }
327
328 return 0;
329 }
330
331 static void
332 gk20a_pllg_enable(struct gk20a_clk *clk)
333 {
334 struct nvkm_device *device = clk->base.subdev.device;
335
336 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
337 nvkm_rd32(device, GPCPLL_CFG);
338 }
339
340 static void
341 gk20a_pllg_disable(struct gk20a_clk *clk)
342 {
343 struct nvkm_device *device = clk->base.subdev.device;
344
345 nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
346 nvkm_rd32(device, GPCPLL_CFG);
347 }
348
349 static int
350 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
351 {
352 struct nvkm_subdev *subdev = &clk->base.subdev;
353 struct nvkm_device *device = subdev->device;
354 u32 val, cfg;
355 u32 m_old, pl_old, n_lo;
356
357 /* get old coefficients */
358 val = nvkm_rd32(device, GPCPLL_COEFF);
359 m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
360 pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
361
362 /* do NDIV slide if there is no change in M and PL */
363 cfg = nvkm_rd32(device, GPCPLL_CFG);
364 if (allow_slide && clk->m == m_old && clk->pl == pl_old &&
365 (cfg & GPCPLL_CFG_ENABLE)) {
366 return gk20a_pllg_slide(clk, clk->n);
367 }
368
369 /* slide down to NDIV_LO */
370 if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) {
371 int ret;
372
373 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco,
374 clk->parent_rate / KHZ);
375 ret = gk20a_pllg_slide(clk, n_lo);
376
377 if (ret)
378 return ret;
379 }
380
381 /* split FO-to-bypass jump in halfs by setting out divider 1:2 */
382 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
383 0x2 << GPC2CLK_OUT_VCODIV_SHIFT);
384
385 /* put PLL in bypass before programming it */
386 val = nvkm_rd32(device, SEL_VCO);
387 val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
388 udelay(2);
389 nvkm_wr32(device, SEL_VCO, val);
390
391 /* get out from IDDQ */
392 val = nvkm_rd32(device, GPCPLL_CFG);
393 if (val & GPCPLL_CFG_IDDQ) {
394 val &= ~GPCPLL_CFG_IDDQ;
395 nvkm_wr32(device, GPCPLL_CFG, val);
396 nvkm_rd32(device, GPCPLL_CFG);
397 udelay(2);
398 }
399
400 gk20a_pllg_disable(clk);
401
402 nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
403 clk->m, clk->n, clk->pl);
404
405 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco,
406 clk->parent_rate / KHZ);
407 val = clk->m << GPCPLL_COEFF_M_SHIFT;
408 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT;
409 val |= clk->pl << GPCPLL_COEFF_P_SHIFT;
410 nvkm_wr32(device, GPCPLL_COEFF, val);
411
412 gk20a_pllg_enable(clk);
413
414 val = nvkm_rd32(device, GPCPLL_CFG);
415 if (val & GPCPLL_CFG_LOCK_DET_OFF) {
416 val &= ~GPCPLL_CFG_LOCK_DET_OFF;
417 nvkm_wr32(device, GPCPLL_CFG, val);
418 }
419
420 if (nvkm_usec(device, 300,
421 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK)
422 break;
423 ) < 0)
424 return -ETIMEDOUT;
425
426 /* switch to VCO mode */
427 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),
428 BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
429
430 /* restore out divider 1:1 */
431 val = nvkm_rd32(device, GPC2CLK_OUT);
432 if ((val & GPC2CLK_OUT_VCODIV_MASK) !=
433 (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT)) {
434 val &= ~GPC2CLK_OUT_VCODIV_MASK;
435 val |= GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT;
436 udelay(2);
437 nvkm_wr32(device, GPC2CLK_OUT, val);
438 /* Intentional 2nd write to assure linear divider operation */
439 nvkm_wr32(device, GPC2CLK_OUT, val);
440 nvkm_rd32(device, GPC2CLK_OUT);
441 }
442
443 /* slide up to new NDIV */
444 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0;
445 }
446
447 static int
448 gk20a_pllg_program_mnp(struct gk20a_clk *clk)
449 {
450 int err;
451
452 err = _gk20a_pllg_program_mnp(clk, true);
453 if (err)
454 err = _gk20a_pllg_program_mnp(clk, false);
455
456 return err;
457 }
458
459 #define GK20A_CLK_GPC_MDIV 1000
460
461 static struct nvkm_pstate
462 gk20a_pstates[] = {
463 {
464 .base = {
465 .domain[nv_clk_src_gpc] = 72000,
466 .voltage = 0,
467 },
468 },
469 {
470 .base = {
471 .domain[nv_clk_src_gpc] = 108000,
472 .voltage = 1,
473 },
474 },
475 {
476 .base = {
477 .domain[nv_clk_src_gpc] = 180000,
478 .voltage = 2,
479 },
480 },
481 {
482 .base = {
483 .domain[nv_clk_src_gpc] = 252000,
484 .voltage = 3,
485 },
486 },
487 {
488 .base = {
489 .domain[nv_clk_src_gpc] = 324000,
490 .voltage = 4,
491 },
492 },
493 {
494 .base = {
495 .domain[nv_clk_src_gpc] = 396000,
496 .voltage = 5,
497 },
498 },
499 {
500 .base = {
501 .domain[nv_clk_src_gpc] = 468000,
502 .voltage = 6,
503 },
504 },
505 {
506 .base = {
507 .domain[nv_clk_src_gpc] = 540000,
508 .voltage = 7,
509 },
510 },
511 {
512 .base = {
513 .domain[nv_clk_src_gpc] = 612000,
514 .voltage = 8,
515 },
516 },
517 {
518 .base = {
519 .domain[nv_clk_src_gpc] = 648000,
520 .voltage = 9,
521 },
522 },
523 {
524 .base = {
525 .domain[nv_clk_src_gpc] = 684000,
526 .voltage = 10,
527 },
528 },
529 {
530 .base = {
531 .domain[nv_clk_src_gpc] = 708000,
532 .voltage = 11,
533 },
534 },
535 {
536 .base = {
537 .domain[nv_clk_src_gpc] = 756000,
538 .voltage = 12,
539 },
540 },
541 {
542 .base = {
543 .domain[nv_clk_src_gpc] = 804000,
544 .voltage = 13,
545 },
546 },
547 {
548 .base = {
549 .domain[nv_clk_src_gpc] = 852000,
550 .voltage = 14,
551 },
552 },
553 };
554
555 static int
556 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
557 {
558 struct gk20a_clk *clk = gk20a_clk(base);
559 struct nvkm_subdev *subdev = &clk->base.subdev;
560 struct nvkm_device *device = subdev->device;
561
562 switch (src) {
563 case nv_clk_src_crystal:
564 return device->crystal;
565 case nv_clk_src_gpc:
566 gk20a_pllg_read_mnp(clk);
567 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
568 default:
569 nvkm_error(subdev, "invalid clock source %d\n", src);
570 return -EINVAL;
571 }
572 }
573
574 static int
575 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
576 {
577 struct gk20a_clk *clk = gk20a_clk(base);
578
579 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
580 GK20A_CLK_GPC_MDIV);
581 }
582
583 static int
584 gk20a_clk_prog(struct nvkm_clk *base)
585 {
586 struct gk20a_clk *clk = gk20a_clk(base);
587
588 return gk20a_pllg_program_mnp(clk);
589 }
590
591 static void
592 gk20a_clk_tidy(struct nvkm_clk *base)
593 {
594 }
595
596 static void
597 gk20a_clk_fini(struct nvkm_clk *base)
598 {
599 struct nvkm_device *device = base->subdev.device;
600 struct gk20a_clk *clk = gk20a_clk(base);
601 u32 val;
602
603 /* slide to VCO min */
604 val = nvkm_rd32(device, GPCPLL_CFG);
605 if (val & GPCPLL_CFG_ENABLE) {
606 u32 coef, m, n_lo;
607
608 coef = nvkm_rd32(device, GPCPLL_COEFF);
609 m = (coef >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
610 n_lo = DIV_ROUND_UP(m * clk->params->min_vco,
611 clk->parent_rate / KHZ);
612 gk20a_pllg_slide(clk, n_lo);
613 }
614
615 /* put PLL in bypass before disabling it */
616 nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
617
618 gk20a_pllg_disable(clk);
619 }
620
621 static int
622 gk20a_clk_init(struct nvkm_clk *base)
623 {
624 struct gk20a_clk *clk = gk20a_clk(base);
625 struct nvkm_subdev *subdev = &clk->base.subdev;
626 struct nvkm_device *device = subdev->device;
627 int ret;
628
629 nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
630
631 ret = gk20a_clk_prog(&clk->base);
632 if (ret) {
633 nvkm_error(subdev, "cannot initialize clock\n");
634 return ret;
635 }
636
637 return 0;
638 }
639
640 static const struct nvkm_clk_func
641 gk20a_clk = {
642 .init = gk20a_clk_init,
643 .fini = gk20a_clk_fini,
644 .read = gk20a_clk_read,
645 .calc = gk20a_clk_calc,
646 .prog = gk20a_clk_prog,
647 .tidy = gk20a_clk_tidy,
648 .pstates = gk20a_pstates,
649 .nr_pstates = ARRAY_SIZE(gk20a_pstates),
650 .domains = {
651 { nv_clk_src_crystal, 0xff },
652 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
653 { nv_clk_src_max }
654 }
655 };
656
657 int
658 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
659 {
660 struct nvkm_device_tegra *tdev = device->func->tegra(device);
661 struct gk20a_clk *clk;
662 int ret, i;
663
664 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
665 return -ENOMEM;
666 *pclk = &clk->base;
667
668 /* Finish initializing the pstates */
669 for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) {
670 INIT_LIST_HEAD(&gk20a_pstates[i].list);
671 gk20a_pstates[i].pstate = i + 1;
672 }
673
674 clk->params = &gk20a_pllg_params;
675 clk->parent_rate = clk_get_rate(tdev->clk);
676
677 ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base);
678 nvkm_info(&clk->base.subdev, "parent clock rate: %d Khz\n",
679 clk->parent_rate / KHZ);
680 return ret;
681 }
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