drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/clk.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/pll.h>
  28 #include <subdev/timer.h>
  29
  30 #include "pll.h"
  31
  32 struct nvc0_clk_info {
  33         u32 freq;
  34         u32 ssel;
  35         u32 mdiv;
  36         u32 dsrc;
  37         u32 ddiv;
  38         u32 coef;
  39 };
  40
  41 struct nvc0_clk_priv {
  42         struct nouveau_clk base;
  43         struct nvc0_clk_info eng[16];
  44 };
  45
  46 static u32 read_div(struct nvc0_clk_priv *, int, u32, u32);
  47
  48 static u32
  49 read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
  50 {
  51         struct nouveau_clk *clk = &priv->base;
  52         u32 ssrc = nv_rd32(priv, dsrc);
  53         if (!(ssrc & 0x00000100))
  54                 return clk->read(clk, nv_clk_src_sppll0);
  55         return clk->read(clk, nv_clk_src_sppll1);
  56 }
  57
  58 static u32
  59 read_pll(struct nvc0_clk_priv *priv, u32 pll)
  60 {
  61         struct nouveau_clk *clk = &priv->base;
  62         u32 ctrl = nv_rd32(priv, pll + 0x00);
  63         u32 coef = nv_rd32(priv, pll + 0x04);
  64         u32 P = (coef & 0x003f0000) >> 16;
  65         u32 N = (coef & 0x0000ff00) >> 8;
  66         u32 M = (coef & 0x000000ff) >> 0;
  67         u32 sclk;
  68
  69         if (!(ctrl & 0x00000001))
  70                 return 0;
  71
  72         switch (pll) {
  73         case 0x00e800:
  74         case 0x00e820:
  75                 sclk = nv_device(priv)->crystal;
  76                 P = 1;
  77                 break;
  78         case 0x132000:
  79                 sclk = clk->read(clk, nv_clk_src_mpllsrc);
  80                 break;
  81         case 0x132020:
  82                 sclk = clk->read(clk, nv_clk_src_mpllsrcref);
  83                 break;
  84         case 0x137000:
  85         case 0x137020:
  86         case 0x137040:
  87         case 0x1370e0:
  88                 sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
  89                 break;
  90         default:
  91                 return 0;
  92         }
  93
  94         return sclk * N / M / P;
  95 }
  96
  97 static u32
  98 read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
  99 {
 100         u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
 101         u32 sctl = nv_rd32(priv, dctl + (doff * 4));
 102
 103         switch (ssrc & 0x00000003) {
 104         case 0:
 105                 if ((ssrc & 0x00030000) != 0x00030000)
 106                         return nv_device(priv)->crystal;
 107                 return 108000;
 108         case 2:
 109                 return 100000;
 110         case 3:
 111                 if (sctl & 0x80000000) {
 112                         u32 sclk = read_vco(priv, dsrc + (doff * 4));
 113                         u32 sdiv = (sctl & 0x0000003f) + 2;
 114                         return (sclk * 2) / sdiv;
 115                 }
 116
 117                 return read_vco(priv, dsrc + (doff * 4));
 118         default:
 119                 return 0;
 120         }
 121 }
 122
 123 static u32
 124 read_clk(struct nvc0_clk_priv *priv, int clk)
 125 {
 126         u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
 127         u32 ssel = nv_rd32(priv, 0x137100);
 128         u32 sclk, sdiv;
 129
 130         if (ssel & (1 << clk)) {
 131                 if (clk < 7)
 132                         sclk = read_pll(priv, 0x137000 + (clk * 0x20));
 133                 else
 134                         sclk = read_pll(priv, 0x1370e0);
 135                 sdiv = ((sctl & 0x00003f00) >> 8) + 2;
 136         } else {
 137                 sclk = read_div(priv, clk, 0x137160, 0x1371d0);
 138                 sdiv = ((sctl & 0x0000003f) >> 0) + 2;
 139         }
 140
 141         if (sctl & 0x80000000)
 142                 return (sclk * 2) / sdiv;
 143
 144         return sclk;
 145 }
 146
 147 static int
 148 nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
 149 {
 150         struct nouveau_device *device = nv_device(clk);
 151         struct nvc0_clk_priv *priv = (void *)clk;
 152
 153         switch (src) {
 154         case nv_clk_src_crystal:
 155                 return device->crystal;
 156         case nv_clk_src_href:
 157                 return 100000;
 158         case nv_clk_src_sppll0:
 159                 return read_pll(priv, 0x00e800);
 160         case nv_clk_src_sppll1:
 161                 return read_pll(priv, 0x00e820);
 162
 163         case nv_clk_src_mpllsrcref:
 164                 return read_div(priv, 0, 0x137320, 0x137330);
 165         case nv_clk_src_mpllsrc:
 166                 return read_pll(priv, 0x132020);
 167         case nv_clk_src_mpll:
 168                 return read_pll(priv, 0x132000);
 169         case nv_clk_src_mdiv:
 170                 return read_div(priv, 0, 0x137300, 0x137310);
 171         case nv_clk_src_mem:
 172                 if (nv_rd32(priv, 0x1373f0) & 0x00000002)
 173                         return clk->read(clk, nv_clk_src_mpll);
 174                 return clk->read(clk, nv_clk_src_mdiv);
 175
 176         case nv_clk_src_gpc:
 177                 return read_clk(priv, 0x00);
 178         case nv_clk_src_rop:
 179                 return read_clk(priv, 0x01);
 180         case nv_clk_src_hubk07:
 181                 return read_clk(priv, 0x02);
 182         case nv_clk_src_hubk06:
 183                 return read_clk(priv, 0x07);
 184         case nv_clk_src_hubk01:
 185                 return read_clk(priv, 0x08);
 186         case nv_clk_src_copy:
 187                 return read_clk(priv, 0x09);
 188         case nv_clk_src_daemon:
 189                 return read_clk(priv, 0x0c);
 190         case nv_clk_src_vdec:
 191                 return read_clk(priv, 0x0e);
 192         default:
 193                 nv_error(clk, "invalid clock source %d\n", src);
 194                 return -EINVAL;
 195         }
 196 }
 197
 198 static u32
 199 calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
 200 {
 201         u32 div = min((ref * 2) / freq, (u32)65);
 202         if (div < 2)
 203                 div = 2;
 204
 205         *ddiv = div - 2;
 206         return (ref * 2) / div;
 207 }
 208
 209 static u32
 210 calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
 211 {
 212         u32 sclk;
 213
 214         /* use one of the fixed frequencies if possible */
 215         *ddiv = 0x00000000;
 216         switch (freq) {
 217         case  27000:
 218         case 108000:
 219                 *dsrc = 0x00000000;
 220                 if (freq == 108000)
 221                         *dsrc |= 0x00030000;
 222                 return freq;
 223         case 100000:
 224                 *dsrc = 0x00000002;
 225                 return freq;
 226         default:
 227                 *dsrc = 0x00000003;
 228                 break;
 229         }
 230
 231         /* otherwise, calculate the closest divider */
 232         sclk = read_vco(priv, 0x137160 + (clk * 4));
 233         if (clk < 7)
 234                 sclk = calc_div(priv, clk, sclk, freq, ddiv);
 235         return sclk;
 236 }
 237
 238 static u32
 239 calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
 240 {
 241         struct nouveau_bios *bios = nouveau_bios(priv);
 242         struct nvbios_pll limits;
 243         int N, M, P, ret;
 244
 245         ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
 246         if (ret)
 247                 return 0;
 248
 249         limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
 250         if (!limits.refclk)
 251                 return 0;
 252
 253         ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
 254         if (ret <= 0)
 255                 return 0;
 256
 257         *coef = (P << 16) | (N << 8) | M;
 258         return ret;
 259 }
 260
 261 static int
 262 calc_clk(struct nvc0_clk_priv *priv,
 263          struct nouveau_cstate *cstate, int clk, int dom)
 264 {
 265         struct nvc0_clk_info *info = &priv->eng[clk];
 266         u32 freq = cstate->domain[dom];
 267         u32 src0, div0, div1D, div1P = 0;
 268         u32 clk0, clk1 = 0;
 269
 270         /* invalid clock domain */
 271         if (!freq)
 272                 return 0;
 273
 274         /* first possible path, using only dividers */
 275         clk0 = calc_src(priv, clk, freq, &src0, &div0);
 276         clk0 = calc_div(priv, clk, clk0, freq, &div1D);
 277
 278         /* see if we can get any closer using PLLs */
 279         if (clk0 != freq && (0x00004387 & (1 << clk))) {
 280                 if (clk <= 7)
 281                         clk1 = calc_pll(priv, clk, freq, &info->coef);
 282                 else
 283                         clk1 = cstate->domain[nv_clk_src_hubk06];
 284                 clk1 = calc_div(priv, clk, clk1, freq, &div1P);
 285         }
 286
 287         /* select the method which gets closest to target freq */
 288         if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
 289                 info->dsrc = src0;
 290                 if (div0) {
 291                         info->ddiv |= 0x80000000;
 292                         info->ddiv |= div0 << 8;
 293                         info->ddiv |= div0;
 294                 }
 295                 if (div1D) {
 296                         info->mdiv |= 0x80000000;
 297                         info->mdiv |= div1D;
 298                 }
 299                 info->ssel = info->coef = 0;
 300                 info->freq = clk0;
 301         } else {
 302                 if (div1P) {
 303                         info->mdiv |= 0x80000000;
 304                         info->mdiv |= div1P << 8;
 305                 }
 306                 info->ssel = (1 << clk);
 307                 info->freq = clk1;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static int
 314 nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
 315 {
 316         struct nvc0_clk_priv *priv = (void *)clk;
 317         int ret;
 318
 319         if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
 320             (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
 321             (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
 322             (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
 323             (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
 324             (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) ||
 325             (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
 326             (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
 327                 return ret;
 328
 329         return 0;
 330 }
 331
 332 static void
 333 nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
 334 {
 335         struct nvc0_clk_info *info = &priv->eng[clk];
 336         if (clk < 7 && !info->ssel) {
 337                 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
 338                 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
 339         }
 340 }
 341
 342 static void
 343 nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk)
 344 {
 345         nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
 346         nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
 347 }
 348
 349 static void
 350 nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
 351 {
 352         struct nvc0_clk_info *info = &priv->eng[clk];
 353         const u32 addr = 0x137000 + (clk * 0x20);
 354         if (clk <= 7) {
 355                 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
 356                 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
 357                 if (info->coef) {
 358                         nv_wr32(priv, addr + 0x04, info->coef);
 359                         nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
 360                         nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
 361                         nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
 362                 }
 363         }
 364 }
 365
 366 static void
 367 nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
 368 {
 369         struct nvc0_clk_info *info = &priv->eng[clk];
 370         if (info->ssel) {
 371                 nv_mask(priv, 0x137100, (1 << clk), info->ssel);
 372                 nv_wait(priv, 0x137100, (1 << clk), info->ssel);
 373         }
 374 }
 375
 376 static void
 377 nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk)
 378 {
 379         struct nvc0_clk_info *info = &priv->eng[clk];
 380         nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
 381 }
 382
 383 static int
 384 nvc0_clk_prog(struct nouveau_clk *clk)
 385 {
 386         struct nvc0_clk_priv *priv = (void *)clk;
 387         struct {
 388                 void (*exec)(struct nvc0_clk_priv *, int);
 389         } stage[] = {
 390                 { nvc0_clk_prog_0 }, /* div programming */
 391                 { nvc0_clk_prog_1 }, /* select div mode */
 392                 { nvc0_clk_prog_2 }, /* (maybe) program pll */
 393                 { nvc0_clk_prog_3 }, /* (maybe) select pll mode */
 394                 { nvc0_clk_prog_4 }, /* final divider */
 395         };
 396         int i, j;
 397
 398         for (i = 0; i < ARRAY_SIZE(stage); i++) {
 399                 for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
 400                         if (!priv->eng[j].freq)
 401                                 continue;
 402                         stage[i].exec(priv, j);
 403                 }
 404         }
 405
 406         return 0;
 407 }
 408
 409 static void
 410 nvc0_clk_tidy(struct nouveau_clk *clk)
 411 {
 412         struct nvc0_clk_priv *priv = (void *)clk;
 413         memset(priv->eng, 0x00, sizeof(priv->eng));
 414 }
 415
 416 static struct nouveau_domain
 417 nvc0_domain[] = {
 418         { nv_clk_src_crystal, 0xff },
 419         { nv_clk_src_href   , 0xff },
 420         { nv_clk_src_hubk06 , 0x00 },
 421         { nv_clk_src_hubk01 , 0x01 },
 422         { nv_clk_src_copy   , 0x02 },
 423         { nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
 424         { nv_clk_src_rop    , 0x04 },
 425         { nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
 426         { nv_clk_src_vdec   , 0x06 },
 427         { nv_clk_src_daemon , 0x0a },
 428         { nv_clk_src_hubk07 , 0x0b },
 429         { nv_clk_src_max }
 430 };
 431
 432 static int
 433 nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 434                 struct nouveau_oclass *oclass, void *data, u32 size,
 435                 struct nouveau_object **pobject)
 436 {
 437         struct nvc0_clk_priv *priv;
 438         int ret;
 439
 440         ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0,
 441                                    false, &priv);
 442         *pobject = nv_object(priv);
 443         if (ret)
 444                 return ret;
 445
 446         priv->base.read = nvc0_clk_read;
 447         priv->base.calc = nvc0_clk_calc;
 448         priv->base.prog = nvc0_clk_prog;
 449         priv->base.tidy = nvc0_clk_tidy;
 450         return 0;
 451 }
 452
 453 struct nouveau_oclass
 454 nvc0_clk_oclass = {
 455         .handle = NV_SUBDEV(CLK, 0xc0),
 456         .ofuncs = &(struct nouveau_ofuncs) {
 457                 .ctor = nvc0_clk_ctor,
 458                 .dtor = _nouveau_clk_dtor,
 459                 .init = _nouveau_clk_init,
 460                 .fini = _nouveau_clk_fini,
 461         },
 462 };