drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv40.h"
  25
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/bit.h>
  28 #include <subdev/bios/init.h>
  29 #include <subdev/bios/pll.h>
  30 #include <subdev/clk/pll.h>
  31 #include <subdev/timer.h>
  32
  33 int
  34 nv40_ram_calc(struct nvkm_fb *fb, u32 freq)
  35 {
  36         struct nvkm_bios *bios = nvkm_bios(fb);
  37         struct nv40_ram *ram = (void *)fb->ram;
  38         struct nvbios_pll pll;
  39         int N1, M1, N2, M2;
  40         int log2P, ret;
  41
  42         ret = nvbios_pll_parse(bios, 0x04, &pll);
  43         if (ret) {
  44                 nv_error(fb, "mclk pll data not found\n");
  45                 return ret;
  46         }
  47
  48         ret = nv04_pll_calc(nv_subdev(fb), &pll, freq,
  49                             &N1, &M1, &N2, &M2, &log2P);
  50         if (ret < 0)
  51                 return ret;
  52
  53         ram->ctrl  = 0x80000000 | (log2P << 16);
  54         ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
  55         if (N2 == M2) {
  56                 ram->ctrl |= 0x00000100;
  57                 ram->coef  = (N1 << 8) | M1;
  58         } else {
  59                 ram->ctrl |= 0x40000000;
  60                 ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
  61         }
  62
  63         return 0;
  64 }
  65
  66 int
  67 nv40_ram_prog(struct nvkm_fb *fb)
  68 {
  69         struct nvkm_bios *bios = nvkm_bios(fb);
  70         struct nv40_ram *ram = (void *)fb->ram;
  71         struct bit_entry M;
  72         u32 crtc_mask = 0;
  73         u8  sr1[2];
  74         int i;
  75
  76         /* determine which CRTCs are active, fetch VGA_SR1 for each */
  77         for (i = 0; i < 2; i++) {
  78                 u32 vbl = nv_rd32(fb, 0x600808 + (i * 0x2000));
  79                 u32 cnt = 0;
  80                 do {
  81                         if (vbl != nv_rd32(fb, 0x600808 + (i * 0x2000))) {
  82                                 nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
  83                                 sr1[i] = nv_rd08(fb, 0x0c03c5 + (i * 0x2000));
  84                                 if (!(sr1[i] & 0x20))
  85                                         crtc_mask |= (1 << i);
  86                                 break;
  87                         }
  88                         udelay(1);
  89                 } while (cnt++ < 32);
  90         }
  91
  92         /* wait for vblank start on active crtcs, disable memory access */
  93         for (i = 0; i < 2; i++) {
  94                 if (!(crtc_mask & (1 << i)))
  95                         continue;
  96                 nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
  97                 nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
  98                 nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
  99                 nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
 100         }
 101
 102         /* prepare ram for reclocking */
 103         nv_wr32(fb, 0x1002d4, 0x00000001); /* precharge */
 104         nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */
 105         nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */
 106         nv_mask(fb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
 107         nv_wr32(fb, 0x1002dc, 0x00000001); /* enable self-refresh */
 108
 109         /* change the PLL of each memory partition */
 110         nv_mask(fb, 0x00c040, 0x0000c000, 0x00000000);
 111         switch (nv_device(fb)->chipset) {
 112         case 0x40:
 113         case 0x45:
 114         case 0x41:
 115         case 0x42:
 116         case 0x47:
 117                 nv_mask(fb, 0x004044, 0xc0771100, ram->ctrl);
 118                 nv_mask(fb, 0x00402c, 0xc0771100, ram->ctrl);
 119                 nv_wr32(fb, 0x004048, ram->coef);
 120                 nv_wr32(fb, 0x004030, ram->coef);
 121         case 0x43:
 122         case 0x49:
 123         case 0x4b:
 124                 nv_mask(fb, 0x004038, 0xc0771100, ram->ctrl);
 125                 nv_wr32(fb, 0x00403c, ram->coef);
 126         default:
 127                 nv_mask(fb, 0x004020, 0xc0771100, ram->ctrl);
 128                 nv_wr32(fb, 0x004024, ram->coef);
 129                 break;
 130         }
 131         udelay(100);
 132         nv_mask(fb, 0x00c040, 0x0000c000, 0x0000c000);
 133
 134         /* re-enable normal operation of memory controller */
 135         nv_wr32(fb, 0x1002dc, 0x00000000);
 136         nv_mask(fb, 0x100210, 0x80000000, 0x80000000);
 137         udelay(100);
 138
 139         /* execute memory reset script from vbios */
 140         if (!bit_entry(bios, 'M', &M)) {
 141                 struct nvbios_init init = {
 142                         .subdev = nv_subdev(fb),
 143                         .bios = bios,
 144                         .offset = nv_ro16(bios, M.offset + 0x00),
 145                         .execute = 1,
 146                 };
 147
 148                 nvbios_exec(&init);
 149         }
 150
 151         /* make sure we're in vblank (hopefully the same one as before), and
 152          * then re-enable crtc memory access
 153          */
 154         for (i = 0; i < 2; i++) {
 155                 if (!(crtc_mask & (1 << i)))
 156                         continue;
 157                 nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
 158                 nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
 159                 nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i]);
 160         }
 161
 162         return 0;
 163 }
 164
 165 void
 166 nv40_ram_tidy(struct nvkm_fb *fb)
 167 {
 168 }
 169
 170 static int
 171 nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 172                 struct nvkm_oclass *oclass, void *data, u32 size,
 173                 struct nvkm_object **pobject)
 174 {
 175         struct nvkm_fb *fb = nvkm_fb(parent);
 176         struct nv40_ram *ram;
 177         u32 pbus1218 = nv_rd32(fb, 0x001218);
 178         int ret;
 179
 180         ret = nvkm_ram_create(parent, engine, oclass, &ram);
 181         *pobject = nv_object(ram);
 182         if (ret)
 183                 return ret;
 184
 185         switch (pbus1218 & 0x00000300) {
 186         case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break;
 187         case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break;
 188         case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break;
 189         case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;
 190         }
 191
 192         ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
 193         ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
 194         ram->base.tags  =  nv_rd32(fb, 0x100320);
 195         ram->base.calc = nv40_ram_calc;
 196         ram->base.prog = nv40_ram_prog;
 197         ram->base.tidy = nv40_ram_tidy;
 198         return 0;
 199 }
 200
 201
 202 struct nvkm_oclass
 203 nv40_ram_oclass = {
 204         .handle = 0,
 205         .ofuncs = &(struct nvkm_ofuncs) {
 206                 .ctor = nv40_ram_create,
 207                 .dtor = _nvkm_ram_dtor,
 208                 .init = _nvkm_ram_init,
 209                 .fini = _nvkm_ram_fini,
 210         }
 211 };