drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Roy Spliet <rspliet@eclipso.eu>
  24  */
  25
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/bit.h>
  28 #include <subdev/bios/pll.h>
  29 #include <subdev/bios/rammap.h>
  30 #include <subdev/bios/M0205.h>
  31 #include <subdev/bios/timing.h>
  32
  33 #include <subdev/clk/nva3.h>
  34 #include <subdev/clk/pll.h>
  35
  36 #include <subdev/gpio.h>
  37
  38 #include <subdev/timer.h>
  39
  40 #include <engine/fifo.h>
  41
  42 #include <core/option.h>
  43
  44 #include "ramfuc.h"
  45
  46 #include "nv50.h"
  47
  48 /* XXX: Remove when memx gains GPIO support */
  49 extern int nv50_gpio_location(int line, u32 *reg, u32 *shift);
  50
  51 struct nva3_ramfuc {
  52         struct ramfuc base;
  53         struct ramfuc_reg r_0x001610;
  54         struct ramfuc_reg r_0x001700;
  55         struct ramfuc_reg r_0x002504;
  56         struct ramfuc_reg r_0x004000;
  57         struct ramfuc_reg r_0x004004;
  58         struct ramfuc_reg r_0x004018;
  59         struct ramfuc_reg r_0x004128;
  60         struct ramfuc_reg r_0x004168;
  61         struct ramfuc_reg r_0x100080;
  62         struct ramfuc_reg r_0x100200;
  63         struct ramfuc_reg r_0x100210;
  64         struct ramfuc_reg r_0x100220[9];
  65         struct ramfuc_reg r_0x100264;
  66         struct ramfuc_reg r_0x1002d0;
  67         struct ramfuc_reg r_0x1002d4;
  68         struct ramfuc_reg r_0x1002dc;
  69         struct ramfuc_reg r_0x10053c;
  70         struct ramfuc_reg r_0x1005a0;
  71         struct ramfuc_reg r_0x1005a4;
  72         struct ramfuc_reg r_0x100700;
  73         struct ramfuc_reg r_0x100714;
  74         struct ramfuc_reg r_0x100718;
  75         struct ramfuc_reg r_0x10071c;
  76         struct ramfuc_reg r_0x100720;
  77         struct ramfuc_reg r_0x100760;
  78         struct ramfuc_reg r_0x1007a0;
  79         struct ramfuc_reg r_0x1007e0;
  80         struct ramfuc_reg r_0x100da0;
  81         struct ramfuc_reg r_0x10f804;
  82         struct ramfuc_reg r_0x1110e0;
  83         struct ramfuc_reg r_0x111100;
  84         struct ramfuc_reg r_0x111104;
  85         struct ramfuc_reg r_0x1111e0;
  86         struct ramfuc_reg r_0x111400;
  87         struct ramfuc_reg r_0x611200;
  88         struct ramfuc_reg r_mr[4];
  89         struct ramfuc_reg r_gpioFBVREF;
  90 };
  91
  92 struct nva3_ltrain {
  93         enum {
  94                 NVA3_TRAIN_UNKNOWN,
  95                 NVA3_TRAIN_UNSUPPORTED,
  96                 NVA3_TRAIN_ONCE,
  97                 NVA3_TRAIN_EXEC,
  98                 NVA3_TRAIN_DONE
  99         } state;
 100         u32 r_100720;
 101         u32 r_1111e0;
 102         u32 r_111400;
 103         struct nouveau_mem *mem;
 104 };
 105
 106 struct nva3_ram {
 107         struct nouveau_ram base;
 108         struct nva3_ramfuc fuc;
 109         struct nva3_ltrain ltrain;
 110 };
 111
 112 void
 113 nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train)
 114 {
 115         int i, lo, hi;
 116         u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
 117
 118         for (i = 0; i < 8; i++) {
 119                 for (lo = 0; lo < 0x40; lo++) {
 120                         if (!(vals[lo] & 0x80000000))
 121                                 continue;
 122                         if (vals[lo] & (0x101 << i))
 123                                 break;
 124                 }
 125
 126                 if (lo == 0x40)
 127                         return;
 128
 129                 for (hi = lo + 1; hi < 0x40; hi++) {
 130                         if (!(vals[lo] & 0x80000000))
 131                                 continue;
 132                         if (!(vals[hi] & (0x101 << i))) {
 133                                 hi--;
 134                                 break;
 135                         }
 136                 }
 137
 138                 median[i] = ((hi - lo) >> 1) + lo;
 139                 bins[(median[i] & 0xf0) >> 4]++;
 140                 median[i] += 0x30;
 141         }
 142
 143         /* Find the best value for 0x1111e0 */
 144         for (i = 0; i < 4; i++) {
 145                 if (bins[i] > qty) {
 146                         bin = i + 3;
 147                         qty = bins[i];
 148                 }
 149         }
 150
 151         train->r_100720 = 0;
 152         for (i = 0; i < 8; i++) {
 153                 median[i] = max(median[i], (u8) (bin << 4));
 154                 median[i] = min(median[i], (u8) ((bin << 4) | 0xf));
 155
 156                 train->r_100720 |= ((median[i] & 0x0f) << (i << 2));
 157         }
 158
 159         train->r_1111e0 = 0x02000000 | (bin * 0x101);
 160         train->r_111400 = 0x0;
 161 }
 162
 163 /*
 164  * Link training for (at least) DDR3
 165  */
 166 int
 167 nva3_link_train(struct nouveau_fb *pfb)
 168 {
 169         struct nouveau_bios *bios = nouveau_bios(pfb);
 170         struct nva3_ram *ram = (void *)pfb->ram;
 171         struct nouveau_clk *clk = nouveau_clk(pfb);
 172         struct nva3_ltrain *train = &ram->ltrain;
 173         struct nouveau_device *device = nv_device(pfb);
 174         struct nva3_ramfuc *fuc = &ram->fuc;
 175         u32 *result, r1700;
 176         int ret, i;
 177         struct nvbios_M0205T M0205T = { 0 };
 178         u8 ver, hdr, cnt, len, snr, ssz;
 179         unsigned int clk_current;
 180         unsigned long flags;
 181         unsigned long *f = &flags;
 182
 183         if (nouveau_boolopt(device->cfgopt, "NvMemExec", true) != true)
 184                 return -ENOSYS;
 185
 186         /* XXX: Multiple partitions? */
 187         result = kmalloc(64 * sizeof(u32), GFP_KERNEL);
 188         if (!result)
 189                 return -ENOMEM;
 190
 191         train->state = NVA3_TRAIN_EXEC;
 192
 193         /* Clock speeds for training and back */
 194         nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T);
 195         if (M0205T.freq == 0)
 196                 return -ENOENT;
 197
 198         clk_current = clk->read(clk, nv_clk_src_mem);
 199
 200         ret = nva3_clk_pre(clk, f);
 201         if (ret)
 202                 goto out;
 203
 204         /* First: clock up/down */
 205         ret = ram->base.calc(pfb, (u32) M0205T.freq * 1000);
 206         if (ret)
 207                 goto out;
 208
 209         /* Do this *after* calc, eliminates write in script */
 210         nv_wr32(pfb, 0x111400, 0x00000000);
 211         /* XXX: Magic writes that improve train reliability? */
 212         nv_mask(pfb, 0x100674, 0x0000ffff, 0x00000000);
 213         nv_mask(pfb, 0x1005e4, 0x0000ffff, 0x00000000);
 214         nv_mask(pfb, 0x100b0c, 0x000000ff, 0x00000000);
 215         nv_wr32(pfb, 0x100c04, 0x00000400);
 216
 217         /* Now the training script */
 218         r1700 = ram_rd32(fuc, 0x001700);
 219
 220         ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
 221         ram_wr32(fuc, 0x611200, 0x3300);
 222         ram_wait_vblank(fuc);
 223         ram_wait(fuc, 0x611200, 0x00000003, 0x00000000, 500000);
 224         ram_mask(fuc, 0x001610, 0x00000083, 0x00000003);
 225         ram_mask(fuc, 0x100080, 0x00000020, 0x00000000);
 226         ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
 227         ram_wr32(fuc, 0x001700, 0x00000000);
 228
 229         ram_train(fuc);
 230
 231         /* Reset */
 232         ram_mask(fuc, 0x10f804, 0x80000000, 0x80000000);
 233         ram_wr32(fuc, 0x10053c, 0x0);
 234         ram_wr32(fuc, 0x100720, train->r_100720);
 235         ram_wr32(fuc, 0x1111e0, train->r_1111e0);
 236         ram_wr32(fuc, 0x111400, train->r_111400);
 237         ram_nuke(fuc, 0x100080);
 238         ram_mask(fuc, 0x100080, 0x00000020, 0x00000020);
 239         ram_nsec(fuc, 1000);
 240
 241         ram_wr32(fuc, 0x001700, r1700);
 242         ram_mask(fuc, 0x001610, 0x00000083, 0x00000080);
 243         ram_wr32(fuc, 0x611200, 0x3330);
 244         ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
 245
 246         ram_exec(fuc, true);
 247
 248         ram->base.calc(pfb, clk_current);
 249         ram_exec(fuc, true);
 250
 251         /* Post-processing, avoids flicker */
 252         nv_mask(pfb, 0x616308, 0x10, 0x10);
 253         nv_mask(pfb, 0x616b08, 0x10, 0x10);
 254
 255         nva3_clk_post(clk, f);
 256
 257         ram_train_result(pfb, result, 64);
 258         for (i = 0; i < 64; i++)
 259                 nv_debug(pfb, "Train: %08x", result[i]);
 260         nva3_link_train_calc(result, train);
 261
 262         nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720,
 263                         train->r_1111e0, train->r_111400);
 264
 265         kfree(result);
 266
 267         train->state = NVA3_TRAIN_DONE;
 268
 269         return ret;
 270
 271 out:
 272         if(ret == -EBUSY)
 273                 f = NULL;
 274
 275         train->state = NVA3_TRAIN_UNSUPPORTED;
 276
 277         nva3_clk_post(clk, f);
 278         return ret;
 279 }
 280
 281 int
 282 nva3_link_train_init(struct nouveau_fb *pfb)
 283 {
 284         static const u32 pattern[16] = {
 285                 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
 286                 0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
 287                 0x33333333, 0x55555555, 0x77777777, 0x66666666,
 288                 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
 289         };
 290         struct nouveau_bios *bios = nouveau_bios(pfb);
 291         struct nva3_ram *ram = (void *)pfb->ram;
 292         struct nva3_ltrain *train = &ram->ltrain;
 293         struct nouveau_mem *mem;
 294         struct nvbios_M0205E M0205E;
 295         u8 ver, hdr, cnt, len;
 296         u32 r001700;
 297         int ret, i = 0;
 298
 299         train->state = NVA3_TRAIN_UNSUPPORTED;
 300
 301         /* We support type "5"
 302          * XXX: training pattern table appears to be unused for this routine */
 303         if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))
 304                 return -ENOENT;
 305
 306         if (M0205E.type != 5)
 307                 return 0;
 308
 309         train->state = NVA3_TRAIN_ONCE;
 310
 311         ret = pfb->ram->get(pfb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem);
 312         if (ret)
 313                 return ret;
 314
 315         mem = ram->ltrain.mem;
 316
 317         nv_wr32(pfb, 0x100538, 0x10000000 | (mem->offset >> 16));
 318         nv_wr32(pfb, 0x1005a8, 0x0000ffff);
 319         nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001);
 320
 321         for (i = 0; i < 0x30; i++) {
 322                 nv_wr32(pfb, 0x10f8c0, (i << 8) | i);
 323                 nv_wr32(pfb, 0x10f900, pattern[i % 16]);
 324         }
 325
 326         for (i = 0; i < 0x30; i++) {
 327                 nv_wr32(pfb, 0x10f8e0, (i << 8) | i);
 328                 nv_wr32(pfb, 0x10f920, pattern[i % 16]);
 329         }
 330
 331         /* And upload the pattern */
 332         r001700 = nv_rd32(pfb, 0x1700);
 333         nv_wr32(pfb, 0x1700, mem->offset >> 16);
 334         for (i = 0; i < 16; i++)
 335                 nv_wr32(pfb, 0x700000 + (i << 2), pattern[i]);
 336         for (i = 0; i < 16; i++)
 337                 nv_wr32(pfb, 0x700100 + (i << 2), pattern[i]);
 338         nv_wr32(pfb, 0x1700, r001700);
 339
 340         train->r_100720 = nv_rd32(pfb, 0x100720);
 341         train->r_1111e0 = nv_rd32(pfb, 0x1111e0);
 342         train->r_111400 = nv_rd32(pfb, 0x111400);
 343
 344         return 0;
 345 }
 346
 347 void
 348 nva3_link_train_fini(struct nouveau_fb *pfb)
 349 {
 350         struct nva3_ram *ram = (void *)pfb->ram;
 351
 352         if (ram->ltrain.mem)
 353                 pfb->ram->put(pfb, &ram->ltrain.mem);
 354 }
 355
 356 /*
 357  * RAM reclocking
 358  */
 359 #define T(t) cfg->timing_10_##t
 360 static int
 361 nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing)
 362 {
 363         struct nva3_ram *ram = (void *)pfb->ram;
 364         struct nvbios_ramcfg *cfg = &ram->base.target.bios;
 365         int tUNK_base, tUNK_40_0, prevCL;
 366         u32 cur2, cur3, cur7, cur8;
 367
 368         cur2 = nv_rd32(pfb, 0x100228);
 369         cur3 = nv_rd32(pfb, 0x10022c);
 370         cur7 = nv_rd32(pfb, 0x10023c);
 371         cur8 = nv_rd32(pfb, 0x100240);
 372
 373
 374         switch ((!T(CWL)) * ram->base.type) {
 375         case NV_MEM_TYPE_DDR2:
 376                 T(CWL) = T(CL) - 1;
 377                 break;
 378         case NV_MEM_TYPE_GDDR3:
 379                 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
 380                 break;
 381         }
 382
 383         prevCL = (cur3 & 0x000000ff) + 1;
 384         tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL;
 385
 386         timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
 387         timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
 388                     max_t(u8,T(18), 1) << 16 |
 389                     (T(WTR) + 1 + T(CWL)) << 8 |
 390                     (5 + T(CL) - T(CWL));
 391         timing[2] = (T(CWL) - 1) << 24 |
 392                     (T(RRD) << 16) |
 393                     (T(RCDWR) << 8) |
 394                     T(RCDRD);
 395         timing[3] = (cur3 & 0x00ff0000) |
 396                     (0x30 + T(CL)) << 24 |
 397                     (0xb + T(CL)) << 8 |
 398                     (T(CL) - 1);
 399         timing[4] = T(20) << 24 |
 400                     T(21) << 16 |
 401                     T(13) << 8 |
 402                     T(13);
 403         timing[5] = T(RFC) << 24 |
 404                     max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
 405                     max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
 406                     T(RP);
 407         timing[6] = (0x5a + T(CL)) << 16 |
 408                     max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
 409                     (0x50 + T(CL) - T(CWL));
 410         timing[7] = (cur7 & 0xff000000) |
 411                     ((tUNK_base + T(CL)) << 16) |
 412                     0x202;
 413         timing[8] = cur8 & 0xffffff00;
 414
 415         switch (ram->base.type) {
 416         case NV_MEM_TYPE_DDR2:
 417         case NV_MEM_TYPE_GDDR3:
 418                 tUNK_40_0 = prevCL - (cur8 & 0xff);
 419                 if (tUNK_40_0 > 0)
 420                         timing[8] |= T(CL);
 421                 break;
 422         default:
 423                 break;
 424         }
 425
 426         nv_debug(pfb, "Entry: 220: %08x %08x %08x %08x\n",
 427                         timing[0], timing[1], timing[2], timing[3]);
 428         nv_debug(pfb, "  230: %08x %08x %08x %08x\n",
 429                         timing[4], timing[5], timing[6], timing[7]);
 430         nv_debug(pfb, "  240: %08x\n", timing[8]);
 431         return 0;
 432 }
 433 #undef T
 434
 435 static void
 436 nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc)
 437 {
 438         ram_mask(fuc, mr[0], 0x100, 0x100);
 439         ram_nsec(fuc, 1000);
 440         ram_mask(fuc, mr[0], 0x100, 0x000);
 441         ram_nsec(fuc, 1000);
 442 }
 443
 444 static void
 445 nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
 446 {
 447         u32 mr1_old = ram_rd32(fuc, mr[1]);
 448
 449         if (!(mr1_old & 0x1)) {
 450                 ram_wr32(fuc, 0x1002d4, 0x00000001);
 451                 ram_wr32(fuc, mr[1], mr[1]);
 452                 ram_nsec(fuc, 1000);
 453         }
 454 }
 455
 456 static void
 457 nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr)
 458 {
 459         u32 mr1_old = ram_rd32(fuc, mr[1]);
 460
 461         if (!(mr1_old & 0x40)) {
 462                 ram_wr32(fuc, mr[1], mr[1]);
 463                 ram_nsec(fuc, 1000);
 464         }
 465 }
 466
 467 static void
 468 nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk)
 469 {
 470         ram_wr32(fuc, 0x004004, mclk->pll);
 471         ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
 472         ram_mask(fuc, 0x004000, 0x00000010, 0x00000000);
 473         ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
 474         ram_mask(fuc, 0x004000, 0x00000010, 0x00000010);
 475 }
 476
 477 static void
 478 nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val)
 479 {
 480         struct nouveau_gpio *gpio = nouveau_gpio(fuc->base.pfb);
 481         struct dcb_gpio_func func;
 482         u32 reg, sh, gpio_val;
 483         int ret;
 484
 485         if (gpio->get(gpio, 0, 0x2e, DCB_GPIO_UNUSED) != val) {
 486                 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
 487                 if (ret)
 488                         return;
 489
 490                 nv50_gpio_location(func.line, &reg, &sh);
 491                 gpio_val = ram_rd32(fuc, gpioFBVREF);
 492                 if (gpio_val & (8 << sh))
 493                         val = !val;
 494
 495                 ram_mask(fuc, gpioFBVREF, (0x3 << sh), ((val | 0x2) << sh));
 496                 ram_nsec(fuc, 20000);
 497         }
 498 }
 499
 500 static int
 501 nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
 502 {
 503         struct nouveau_bios *bios = nouveau_bios(pfb);
 504         struct nva3_ram *ram = (void *)pfb->ram;
 505         struct nva3_ramfuc *fuc = &ram->fuc;
 506         struct nva3_ltrain *train = &ram->ltrain;
 507         struct nva3_clk_info mclk;
 508         struct nouveau_ram_data *next;
 509         u8  ver, hdr, cnt, len, strap;
 510         u32 data;
 511         u32 r004018, r100760, r100da0, r111100, ctrl;
 512         u32 unk714, unk718, unk71c;
 513         int ret, i;
 514         u32 timing[9];
 515         bool pll2pll;
 516
 517         next = &ram->base.target;
 518         next->freq = freq;
 519         ram->base.next = next;
 520
 521         if (ram->ltrain.state == NVA3_TRAIN_ONCE)
 522                 nva3_link_train(pfb);
 523
 524         /* lookup memory config data relevant to the target frequency */
 525         i = 0;
 526         data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len,
 527                                       &next->bios);
 528         if (!data || ver != 0x10 || hdr < 0x05) {
 529                 nv_error(pfb, "invalid/missing rammap entry\n");
 530                 return -EINVAL;
 531         }
 532
 533         /* locate specific data set for the attached memory */
 534         strap = nvbios_ramcfg_index(nv_subdev(pfb));
 535         if (strap >= cnt) {
 536                 nv_error(pfb, "invalid ramcfg strap\n");
 537                 return -EINVAL;
 538         }
 539
 540         data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
 541                                &ver, &hdr, &next->bios);
 542         if (!data || ver != 0x10 || hdr < 0x09) {
 543                 nv_error(pfb, "invalid/missing ramcfg entry\n");
 544                 return -EINVAL;
 545         }
 546
 547         /* lookup memory timings, if bios says they're present */
 548         if (next->bios.ramcfg_timing != 0xff) {
 549                 data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
 550                                        &ver, &hdr, &cnt, &len,
 551                                        &next->bios);
 552                 if (!data || ver != 0x10 || hdr < 0x17) {
 553                         nv_error(pfb, "invalid/missing timing entry\n");
 554                         return -EINVAL;
 555                 }
 556         }
 557
 558         ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk);
 559         if (ret < 0) {
 560                 nv_error(pfb, "failed mclk calculation\n");
 561                 return ret;
 562         }
 563
 564         nva3_ram_timing_calc(pfb, timing);
 565
 566         ret = ram_init(fuc, pfb);
 567         if (ret)
 568                 return ret;
 569
 570         /* Determine ram-specific MR values */
 571         ram->base.mr[0] = ram_rd32(fuc, mr[0]);
 572         ram->base.mr[1] = ram_rd32(fuc, mr[1]);
 573         ram->base.mr[2] = ram_rd32(fuc, mr[2]);
 574
 575         switch (ram->base.type) {
 576         case NV_MEM_TYPE_DDR2:
 577                 ret = nouveau_sddr2_calc(&ram->base);
 578                 break;
 579         case NV_MEM_TYPE_DDR3:
 580                 ret = nouveau_sddr3_calc(&ram->base);
 581                 break;
 582         case NV_MEM_TYPE_GDDR3:
 583                 ret = nouveau_gddr3_calc(&ram->base);
 584                 break;
 585         default:
 586                 ret = -ENOSYS;
 587                 break;
 588         }
 589
 590         if (ret)
 591                 return ret;
 592
 593         /* XXX: where the fuck does 750MHz come from? */
 594         if (freq <= 750000) {
 595                 r004018 = 0x10000000;
 596                 r100760 = 0x22222222;
 597                 r100da0 = 0x00000010;
 598         } else {
 599                 r004018 = 0x00000000;
 600                 r100760 = 0x00000000;
 601                 r100da0 = 0x00000000;
 602         }
 603
 604         if (!next->bios.ramcfg_10_DLLoff)
 605                 r004018 |= 0x00004000;
 606
 607         /* pll2pll requires to switch to a safe clock first */
 608         ctrl = ram_rd32(fuc, 0x004000);
 609         pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
 610
 611         /* Pre, NVIDIA does this outside the script */
 612         if (next->bios.ramcfg_10_02_10) {
 613                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
 614         } else {
 615                 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
 616                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
 617         }
 618         /* Always disable this bit during reclock */
 619         ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
 620
 621         /* If switching from non-pll to pll, lock before disabling FB */
 622         if (mclk.pll && !pll2pll) {
 623                 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
 624                 nva3_ram_lock_pll(fuc, &mclk);
 625         }
 626
 627         /* Start with disabling some CRTCs and PFIFO? */
 628         ram_wait_vblank(fuc);
 629         ram_wr32(fuc, 0x611200, 0x3300);
 630         ram_mask(fuc, 0x002504, 0x1, 0x1);
 631         ram_nsec(fuc, 10000);
 632         ram_wait(fuc, 0x002504, 0x10, 0x10, 20000); /* XXX: or longer? */
 633         ram_block(fuc);
 634         ram_nsec(fuc, 2000);
 635
 636         if (!next->bios.ramcfg_10_02_10) {
 637                 if (ram->base.type == NV_MEM_TYPE_GDDR3)
 638                         ram_mask(fuc, 0x111100, 0x04020000, 0x00020000);
 639                 else
 640                         ram_mask(fuc, 0x111100, 0x04020000, 0x04020000);
 641         }
 642
 643         /* If we're disabling the DLL, do it now */
 644         switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {
 645         case NV_MEM_TYPE_DDR3:
 646                 nouveau_sddr3_dll_disable(fuc, ram->base.mr);
 647                 break;
 648         case NV_MEM_TYPE_GDDR3:
 649                 nouveau_gddr3_dll_disable(fuc, ram->base.mr);
 650                 break;
 651         }
 652
 653         if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT)
 654                 nva3_ram_fbvref(fuc, 0);
 655
 656         /* Brace RAM for impact */
 657         ram_wr32(fuc, 0x1002d4, 0x00000001);
 658         ram_wr32(fuc, 0x1002d0, 0x00000001);
 659         ram_wr32(fuc, 0x1002d0, 0x00000001);
 660         ram_wr32(fuc, 0x100210, 0x00000000);
 661         ram_wr32(fuc, 0x1002dc, 0x00000001);
 662         ram_nsec(fuc, 2000);
 663
 664         if (nv_device(pfb)->chipset == 0xa3 && freq <= 500000)
 665                 ram_mask(fuc, 0x100700, 0x00000006, 0x00000006);
 666
 667         /* Fiddle with clocks */
 668         /* There's 4 scenario's
 669          * pll->pll: first switch to a 324MHz clock, set up new PLL, switch
 670          * clk->pll: Set up new PLL, switch
 671          * pll->clk: Set up clock, switch
 672          * clk->clk: Overwrite ctrl and other bits, switch */
 673
 674         /* Switch to regular clock - 324MHz */
 675         if (pll2pll) {
 676                 ram_mask(fuc, 0x004000, 0x00000004, 0x00000004);
 677                 ram_mask(fuc, 0x004168, 0x003f3141, 0x00083101);
 678                 ram_mask(fuc, 0x004000, 0x00000008, 0x00000008);
 679                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 680                 ram_wr32(fuc, 0x004018, 0x00001000);
 681                 nva3_ram_lock_pll(fuc, &mclk);
 682         }
 683
 684         if (mclk.pll) {
 685                 ram_mask(fuc, 0x004000, 0x00000105, 0x00000105);
 686                 ram_wr32(fuc, 0x004018, 0x00001000 | r004018);
 687                 ram_wr32(fuc, 0x100da0, r100da0);
 688         } else {
 689                 ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101);
 690                 ram_mask(fuc, 0x004000, 0x00000108, 0x00000008);
 691                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 692                 ram_wr32(fuc, 0x004018, 0x00009000 | r004018);
 693                 ram_wr32(fuc, 0x100da0, r100da0);
 694         }
 695         ram_nsec(fuc, 20000);
 696
 697         if (next->bios.rammap_10_04_08) {
 698                 ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
 699                                         next->bios.ramcfg_10_05 << 8 |
 700                                         next->bios.ramcfg_10_05);
 701                 ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
 702                                         next->bios.ramcfg_10_07);
 703                 ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
 704                                         next->bios.ramcfg_10_03_0f << 16 |
 705                                         next->bios.ramcfg_10_09_0f |
 706                                         0x80000000);
 707                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
 708         } else {
 709                 if (train->state == NVA3_TRAIN_DONE) {
 710                         ram_wr32(fuc, 0x100080, 0x1020);
 711                         ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400);
 712                         ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0);
 713                         ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720);
 714                 }
 715                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
 716                 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
 717                 ram_mask(fuc, 0x100760, 0x22222222, r100760);
 718                 ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
 719                 ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
 720         }
 721
 722         if (nv_device(pfb)->chipset == 0xa3 && freq > 500000) {
 723                 ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
 724         }
 725
 726         /* Final switch */
 727         if (mclk.pll) {
 728                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
 729                 ram_mask(fuc, 0x004000, 0x00000008, 0x00000000);
 730         }
 731
 732         ram_wr32(fuc, 0x1002dc, 0x00000000);
 733         ram_wr32(fuc, 0x1002d4, 0x00000001);
 734         ram_wr32(fuc, 0x100210, 0x80000000);
 735         ram_nsec(fuc, 2000);
 736
 737         /* Set RAM MR parameters and timings */
 738         for (i = 2; i >= 0; i--) {
 739                 if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) {
 740                         ram_wr32(fuc, mr[i], ram->base.mr[i]);
 741                         ram_nsec(fuc, 1000);
 742                 }
 743         }
 744
 745         ram_wr32(fuc, 0x100220[3], timing[3]);
 746         ram_wr32(fuc, 0x100220[1], timing[1]);
 747         ram_wr32(fuc, 0x100220[6], timing[6]);
 748         ram_wr32(fuc, 0x100220[7], timing[7]);
 749         ram_wr32(fuc, 0x100220[2], timing[2]);
 750         ram_wr32(fuc, 0x100220[4], timing[4]);
 751         ram_wr32(fuc, 0x100220[5], timing[5]);
 752         ram_wr32(fuc, 0x100220[0], timing[0]);
 753         ram_wr32(fuc, 0x100220[8], timing[8]);
 754
 755         /* Misc */
 756         ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
 757
 758         /* XXX: A lot of "chipset"/"ram type" specific stuff...? */
 759         unk714  = ram_rd32(fuc, 0x100714) & ~0xf0000130;
 760         unk718  = ram_rd32(fuc, 0x100718) & ~0x00000100;
 761         unk71c  = ram_rd32(fuc, 0x10071c) & ~0x00000100;
 762         r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000;
 763
 764         if (next->bios.ramcfg_10_02_04) {
 765                 switch (ram->base.type) {
 766                 case NV_MEM_TYPE_DDR3:
 767                         if (nv_device(pfb)->chipset != 0xa8)
 768                                 r111100 |= 0x00000004;
 769                         /* no break */
 770                 case NV_MEM_TYPE_DDR2:
 771                         r111100 |= 0x08000000;
 772                         break;
 773                 default:
 774                         break;
 775                 }
 776         } else {
 777                 switch (ram->base.type) {
 778                 case NV_MEM_TYPE_DDR2:
 779                         r111100 |= 0x1a800000;
 780                         unk714  |= 0x00000010;
 781                         break;
 782                 case NV_MEM_TYPE_DDR3:
 783                         if (nv_device(pfb)->chipset == 0xa8) {
 784                                 r111100 |=  0x08000000;
 785                         } else {
 786                                 r111100 &= ~0x00000004;
 787                                 r111100 |=  0x12800000;
 788                         }
 789                         unk714  |= 0x00000010;
 790                         break;
 791                 case NV_MEM_TYPE_GDDR3:
 792                         r111100 |= 0x30000000;
 793                         unk714  |= 0x00000020;
 794                         break;
 795                 default:
 796                         break;
 797                 }
 798         }
 799
 800         unk714 |= (next->bios.ramcfg_10_04_01) << 8;
 801
 802         if (next->bios.ramcfg_10_02_20)
 803                 unk714 |= 0xf0000000;
 804         if (next->bios.ramcfg_10_02_02)
 805                 unk718 |= 0x00000100;
 806         if (next->bios.ramcfg_10_02_01)
 807                 unk71c |= 0x00000100;
 808         if (next->bios.timing_10_24 != 0xff) {
 809                 unk718 &= ~0xf0000000;
 810                 unk718 |= next->bios.timing_10_24 << 28;
 811         }
 812         if (next->bios.ramcfg_10_02_10)
 813                 r111100 &= ~0x04020000;
 814
 815         ram_mask(fuc, 0x100714, 0xffffffff, unk714);
 816         ram_mask(fuc, 0x10071c, 0xffffffff, unk71c);
 817         ram_mask(fuc, 0x100718, 0xffffffff, unk718);
 818         ram_mask(fuc, 0x111100, 0xffffffff, r111100);
 819
 820         if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT)
 821                 nva3_ram_fbvref(fuc, 1);
 822
 823         /* Reset DLL */
 824         if (!next->bios.ramcfg_10_DLLoff)
 825                 nouveau_sddr2_dll_reset(fuc);
 826
 827         if (ram->base.type == NV_MEM_TYPE_GDDR3) {
 828                 ram_nsec(fuc, 31000);
 829         } else {
 830                 ram_nsec(fuc, 14000);
 831         }
 832
 833         if (ram->base.type == NV_MEM_TYPE_DDR3) {
 834                 ram_wr32(fuc, 0x100264, 0x1);
 835                 ram_nsec(fuc, 2000);
 836         }
 837
 838         ram_nuke(fuc, 0x100700);
 839         ram_mask(fuc, 0x100700, 0x01000000, 0x01000000);
 840         ram_mask(fuc, 0x100700, 0x01000000, 0x00000000);
 841
 842         /* Re-enable FB */
 843         ram_unblock(fuc);
 844         ram_wr32(fuc, 0x611200, 0x3330);
 845
 846         /* Post fiddlings */
 847         if (next->bios.rammap_10_04_02)
 848                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
 849         if (next->bios.ramcfg_10_02_10) {
 850                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
 851                 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
 852         } else {
 853                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
 854         }
 855
 856         if (mclk.pll) {
 857                 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
 858                 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
 859         } else {
 860                 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
 861                 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
 862                 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
 863         }
 864
 865         return 0;
 866 }
 867
 868 static int
 869 nva3_ram_prog(struct nouveau_fb *pfb)
 870 {
 871         struct nouveau_device *device = nv_device(pfb);
 872         struct nva3_ram *ram = (void *)pfb->ram;
 873         struct nva3_ramfuc *fuc = &ram->fuc;
 874         bool exec = nouveau_boolopt(device->cfgopt, "NvMemExec", true);
 875
 876         if (exec) {
 877                 nv_mask(pfb, 0x001534, 0x2, 0x2);
 878
 879                 ram_exec(fuc, true);
 880
 881                 /* Post-processing, avoids flicker */
 882                 nv_mask(pfb, 0x002504, 0x1, 0x0);
 883                 nv_mask(pfb, 0x001534, 0x2, 0x0);
 884
 885                 nv_mask(pfb, 0x616308, 0x10, 0x10);
 886                 nv_mask(pfb, 0x616b08, 0x10, 0x10);
 887         } else {
 888                 ram_exec(fuc, false);
 889         }
 890         return 0;
 891 }
 892
 893 static void
 894 nva3_ram_tidy(struct nouveau_fb *pfb)
 895 {
 896         struct nva3_ram *ram = (void *)pfb->ram;
 897         struct nva3_ramfuc *fuc = &ram->fuc;
 898         ram_exec(fuc, false);
 899 }
 900
 901 static int
 902 nva3_ram_init(struct nouveau_object *object)
 903 {
 904         struct nouveau_fb *pfb = (void *)object->parent;
 905         struct nva3_ram   *ram = (void *)object;
 906         int ret;
 907
 908         ret = nouveau_ram_init(&ram->base);
 909         if (ret)
 910                 return ret;
 911
 912         nva3_link_train_init(pfb);
 913
 914         return 0;
 915 }
 916
 917 static int
 918 nva3_ram_fini(struct nouveau_object *object, bool suspend)
 919 {
 920         struct nouveau_fb *pfb = (void *)object->parent;
 921
 922         if (!suspend)
 923                 nva3_link_train_fini(pfb);
 924
 925         return 0;
 926 }
 927
 928 static int
 929 nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 930               struct nouveau_oclass *oclass, void *data, u32 datasize,
 931               struct nouveau_object **pobject)
 932 {
 933         struct nouveau_fb *pfb = nouveau_fb(parent);
 934         struct nouveau_gpio *gpio = nouveau_gpio(pfb);
 935         struct dcb_gpio_func func;
 936         struct nva3_ram *ram;
 937         int ret, i;
 938         u32 reg, shift;
 939
 940         ret = nv50_ram_create(parent, engine, oclass, &ram);
 941         *pobject = nv_object(ram);
 942         if (ret)
 943                 return ret;
 944
 945         switch (ram->base.type) {
 946         case NV_MEM_TYPE_DDR2:
 947         case NV_MEM_TYPE_DDR3:
 948         case NV_MEM_TYPE_GDDR3:
 949                 ram->base.calc = nva3_ram_calc;
 950                 ram->base.prog = nva3_ram_prog;
 951                 ram->base.tidy = nva3_ram_tidy;
 952                 break;
 953         default:
 954                 nv_warn(ram, "reclocking of this ram type unsupported\n");
 955                 return 0;
 956         }
 957
 958         ram->fuc.r_0x001610 = ramfuc_reg(0x001610);
 959         ram->fuc.r_0x001700 = ramfuc_reg(0x001700);
 960         ram->fuc.r_0x002504 = ramfuc_reg(0x002504);
 961         ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
 962         ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
 963         ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
 964         ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
 965         ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
 966         ram->fuc.r_0x100080 = ramfuc_reg(0x100080);
 967         ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
 968         ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
 969         for (i = 0; i < 9; i++)
 970                 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
 971         ram->fuc.r_0x100264 = ramfuc_reg(0x100264);
 972         ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
 973         ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
 974         ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
 975         ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
 976         ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
 977         ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
 978         ram->fuc.r_0x100700 = ramfuc_reg(0x100700);
 979         ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
 980         ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
 981         ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
 982         ram->fuc.r_0x100720 = ramfuc_reg(0x100720);
 983         ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask);
 984         ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask);
 985         ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask);
 986         ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask);
 987         ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
 988         ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask);
 989         ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
 990         ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
 991         ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0);
 992         ram->fuc.r_0x111400 = ramfuc_reg(0x111400);
 993         ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
 994
 995         if (ram->base.ranks > 1) {
 996                 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
 997                 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
 998                 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
 999                 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
1000         } else {
1001                 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
1002                 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
1003                 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
1004                 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
1005         }
1006
1007         ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1008         if (ret == 0) {
1009                 nv50_gpio_location(func.line, &reg, &shift);
1010                 ram->fuc.r_gpioFBVREF = ramfuc_reg(reg);
1011         }
1012
1013         return 0;
1014 }
1015
1016 struct nouveau_oclass
1017 nva3_ram_oclass = {
1018         .ofuncs = &(struct nouveau_ofuncs) {
1019                 .ctor = nva3_ram_ctor,
1020                 .dtor = _nouveau_ram_dtor,
1021                 .init = nva3_ram_init,
1022                 .fini = nva3_ram_fini,
1023         },
1024 };