drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm204.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "nv50.h"
  26
  27 #define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
  28 #define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
  29
  30 static void
  31 auxch_fini(struct nouveau_i2c *aux, int ch)
  32 {
  33         nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00310000, 0x00000000);
  34 }
  35
  36 static int
  37 auxch_init(struct nouveau_i2c *aux, int ch)
  38 {
  39         const u32 unksel = 1; /* nfi which to use, or if it matters.. */
  40         const u32 ureq = unksel ? 0x00100000 : 0x00200000;
  41         const u32 urep = unksel ? 0x01000000 : 0x02000000;
  42         u32 ctrl, timeout;
  43
  44         /* wait up to 1ms for any previous transaction to be done... */
  45         timeout = 1000;
  46         do {
  47                 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
  48                 udelay(1);
  49                 if (!timeout--) {
  50                         AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
  51                         return -EBUSY;
  52                 }
  53         } while (ctrl & 0x03010000);
  54
  55         /* set some magic, and wait up to 1ms for it to appear */
  56         nv_mask(aux, 0x00d954 + (ch * 0x50), 0x00300000, ureq);
  57         timeout = 1000;
  58         do {
  59                 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
  60                 udelay(1);
  61                 if (!timeout--) {
  62                         AUX_ERR("magic wait 0x%08x\n", ctrl);
  63                         auxch_fini(aux, ch);
  64                         return -EBUSY;
  65                 }
  66         } while ((ctrl & 0x03000000) != urep);
  67
  68         return 0;
  69 }
  70
  71 int
  72 gm204_aux(struct nouveau_i2c_port *base, bool retry,
  73          u8 type, u32 addr, u8 *data, u8 size)
  74 {
  75         struct nouveau_i2c *aux = nouveau_i2c(base);
  76         struct nv50_i2c_port *port = (void *)base;
  77         u32 ctrl, stat, timeout, retries;
  78         u32 xbuf[4] = {};
  79         int ch = port->addr;
  80         int ret, i;
  81
  82         AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
  83
  84         ret = auxch_init(aux, ch);
  85         if (ret)
  86                 goto out;
  87
  88         stat = nv_rd32(aux, 0x00d958 + (ch * 0x50));
  89         if (!(stat & 0x10000000)) {
  90                 AUX_DBG("sink not detected\n");
  91                 ret = -ENXIO;
  92                 goto out;
  93         }
  94
  95         if (!(type & 1)) {
  96                 memcpy(xbuf, data, size);
  97                 for (i = 0; i < 16; i += 4) {
  98                         AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
  99                         nv_wr32(aux, 0x00d930 + (ch * 0x50) + i, xbuf[i / 4]);
 100                 }
 101         }
 102
 103         ctrl  = nv_rd32(aux, 0x00d954 + (ch * 0x50));
 104         ctrl &= ~0x0001f0ff;
 105         ctrl |= type << 12;
 106         ctrl |= size - 1;
 107         nv_wr32(aux, 0x00d950 + (ch * 0x50), addr);
 108
 109         /* (maybe) retry transaction a number of times on failure... */
 110         for (retries = 0; !ret && retries < 32; retries++) {
 111                 /* reset, and delay a while if this is a retry */
 112                 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x80000000 | ctrl);
 113                 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00000000 | ctrl);
 114                 if (retries)
 115                         udelay(400);
 116
 117                 /* transaction request, wait up to 1ms for it to complete */
 118                 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00010000 | ctrl);
 119
 120                 timeout = 1000;
 121                 do {
 122                         ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50));
 123                         udelay(1);
 124                         if (!timeout--) {
 125                                 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
 126                                 ret = -EIO;
 127                                 goto out;
 128                         }
 129                 } while (ctrl & 0x00010000);
 130                 ret = 1;
 131
 132                 /* read status, and check if transaction completed ok */
 133                 stat = nv_mask(aux, 0x00d958 + (ch * 0x50), 0, 0);
 134                 if ((stat & 0x000f0000) == 0x00080000 ||
 135                     (stat & 0x000f0000) == 0x00020000)
 136                         ret = retry ? 0 : 1;
 137                 if ((stat & 0x00000100))
 138                         ret = -ETIMEDOUT;
 139                 if ((stat & 0x00000e00))
 140                         ret = -EIO;
 141
 142                 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
 143         }
 144
 145         if (type & 1) {
 146                 for (i = 0; i < 16; i += 4) {
 147                         xbuf[i / 4] = nv_rd32(aux, 0x00d940 + (ch * 0x50) + i);
 148                         AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
 149                 }
 150                 memcpy(data, xbuf, size);
 151         }
 152
 153 out:
 154         auxch_fini(aux, ch);
 155         return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
 156 }
 157
 158 static const struct nouveau_i2c_func
 159 gm204_aux_func = {
 160         .aux       = gm204_aux,
 161 };
 162
 163 int
 164 gm204_aux_port_ctor(struct nouveau_object *parent,
 165                     struct nouveau_object *engine,
 166                     struct nouveau_oclass *oclass, void *data, u32 index,
 167                     struct nouveau_object **pobject)
 168 {
 169         struct dcb_i2c_entry *info = data;
 170         struct nv50_i2c_port *port;
 171         int ret;
 172
 173         ret = nouveau_i2c_port_create(parent, engine, oclass, index,
 174                                       &nouveau_i2c_aux_algo, &gm204_aux_func,
 175                                       &port);
 176         *pobject = nv_object(port);
 177         if (ret)
 178                 return ret;
 179
 180         port->base.aux = info->auxch;
 181         port->addr = info->auxch;
 182         return 0;
 183 }
 184
 185 struct nouveau_oclass
 186 gm204_i2c_sclass[] = {
 187         { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
 188           .ofuncs = &(struct nouveau_ofuncs) {
 189                   .ctor = nvd0_i2c_port_ctor,
 190                   .dtor = _nouveau_i2c_port_dtor,
 191                   .init = nv50_i2c_port_init,
 192                   .fini = _nouveau_i2c_port_fini,
 193           },
 194         },
 195         { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
 196           .ofuncs = &(struct nouveau_ofuncs) {
 197                   .ctor = gm204_aux_port_ctor,
 198                   .dtor = _nouveau_i2c_port_dtor,
 199                   .init = _nouveau_i2c_port_init,
 200                   .fini = _nouveau_i2c_port_fini,
 201           },
 202         },
 203         {}
 204 };
 205
 206 struct nouveau_oclass *
 207 gm204_i2c_oclass = &(struct nouveau_i2c_impl) {
 208         .base.handle = NV_SUBDEV(I2C, 0x24),
 209         .base.ofuncs = &(struct nouveau_ofuncs) {
 210                 .ctor = _nouveau_i2c_ctor,
 211                 .dtor = _nouveau_i2c_dtor,
 212                 .init = _nouveau_i2c_init,
 213                 .fini = _nouveau_i2c_fini,
 214         },
 215         .sclass = gm204_i2c_sclass,
 216         .pad_x = &nv04_i2c_pad_oclass,
 217         .pad_s = &gm204_i2c_pad_oclass,
 218         .aux = 8,
 219         .aux_stat = nve0_aux_stat,
 220         .aux_mask = nve0_aux_mask,
 221 }.base;