drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 const struct nvkm_mc_map
  27 nv04_mc_reset[] = {
  28         { 0x00001000, NVKM_ENGINE_GR },
  29         { 0x00000100, NVKM_ENGINE_FIFO },
  30         {}
  31 };
  32
  33 static const struct nvkm_mc_map
  34 nv04_mc_intr[] = {
  35         { 0x01010000, NVKM_ENGINE_DISP },
  36         { 0x00001000, NVKM_ENGINE_GR },
  37         { 0x00000100, NVKM_ENGINE_FIFO },
  38         { 0x10000000, NVKM_SUBDEV_BUS },
  39         { 0x00100000, NVKM_SUBDEV_TIMER },
  40         {}
  41 };
  42
  43 void
  44 nv04_mc_intr_unarm(struct nvkm_mc *mc)
  45 {
  46         struct nvkm_device *device = mc->subdev.device;
  47         nvkm_wr32(device, 0x000140, 0x00000000);
  48         nvkm_rd32(device, 0x000140);
  49 }
  50
  51 void
  52 nv04_mc_intr_rearm(struct nvkm_mc *mc)
  53 {
  54         struct nvkm_device *device = mc->subdev.device;
  55         nvkm_wr32(device, 0x000140, 0x00000001);
  56 }
  57
  58 u32
  59 nv04_mc_intr_mask(struct nvkm_mc *mc)
  60 {
  61         return nvkm_rd32(mc->subdev.device, 0x000100);
  62 }
  63
  64 void
  65 nv04_mc_init(struct nvkm_mc *mc)
  66 {
  67         struct nvkm_device *device = mc->subdev.device;
  68         nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */
  69         nvkm_wr32(device, 0x001850, 0x00000001); /* disable rom access */
  70 }
  71
  72 static const struct nvkm_mc_func
  73 nv04_mc = {
  74         .init = nv04_mc_init,
  75         .intr = nv04_mc_intr,
  76         .intr_unarm = nv04_mc_intr_unarm,
  77         .intr_rearm = nv04_mc_intr_rearm,
  78         .intr_mask = nv04_mc_intr_mask,
  79         .reset = nv04_mc_reset,
  80 };
  81
  82 int
  83 nv04_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
  84 {
  85         return nvkm_mc_new_(&nv04_mc, device, index, pmc);
  86 }