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drm/nouveau/mmu: remove old vm creation hooks
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nvkm / subdev / mmu / gf100.c
1 /*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "vmm.h"
25
26 #include <core/gpuobj.h>
27 #include <subdev/fb.h>
28 #include <subdev/timer.h>
29
30 #include <nvif/class.h>
31
32 /* Map from compressed to corresponding uncompressed storage type.
33 * The value 0xff represents an invalid storage type.
34 */
35 const u8 gf100_pte_storage_type_map[256] =
36 {
37 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */
38 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff,
39 0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 0x11, /* 0x10 */
40 0x11, 0x11, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff,
41 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x26, 0x27, /* 0x20 */
42 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
43 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 */
44 0xff, 0xff, 0x26, 0x27, 0x28, 0x29, 0x26, 0x27,
45 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0x46, 0xff, /* 0x40 */
46 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
47 0xff, 0x46, 0x46, 0x46, 0x46, 0xff, 0xff, 0xff, /* 0x50 */
48 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
49 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x60 */
50 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
51 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x70 */
52 0xff, 0xff, 0xff, 0x7b, 0xff, 0xff, 0xff, 0xff,
53 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x7b, /* 0x80 */
54 0x7b, 0x7b, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xff,
55 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x90 */
56 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
57 0xff, 0xff, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xa7, /* 0xa0 */
58 0xa8, 0xa9, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff,
59 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */
60 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7,
61 0xa8, 0xa9, 0xaa, 0xc3, 0xff, 0xff, 0xff, 0xff, /* 0xc0 */
62 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe, 0xc3, 0xc3,
63 0xc3, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xd0 */
64 0xfe, 0xff, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe,
65 0xfe, 0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xff, /* 0xe0 */
66 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xfe, 0xff,
67 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, /* 0xf0 */
68 0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff
69 };
70
71
72 void
73 gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_memory *pgt[2])
74 {
75 u32 pde[2] = { 0, 0 };
76
77 if (pgt[0])
78 pde[1] = 0x00000001 | (nvkm_memory_addr(pgt[0]) >> 8);
79 if (pgt[1])
80 pde[0] = 0x00000001 | (nvkm_memory_addr(pgt[1]) >> 8);
81
82 nvkm_kmap(pgd);
83 nvkm_wo32(pgd, (index * 8) + 0, pde[0]);
84 nvkm_wo32(pgd, (index * 8) + 4, pde[1]);
85 nvkm_done(pgd);
86 }
87
88 static inline u64
89 gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
90 {
91 phys >>= 8;
92
93 phys |= 0x00000001; /* present */
94 if (vma->access & NV_MEM_ACCESS_SYS)
95 phys |= 0x00000002;
96
97 phys |= ((u64)target << 32);
98 phys |= ((u64)memtype << 36);
99 return phys;
100 }
101
102 void
103 gf100_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt,
104 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
105 {
106 u64 next = 1 << (vma->node->type - 8);
107
108 phys = gf100_vm_addr(vma, phys, mem->memtype, 0);
109 pte <<= 3;
110
111 if (mem->tag) {
112 u32 tag = mem->tag->offset + (delta >> 17);
113 phys |= (u64)tag << (32 + 12);
114 next |= (u64)1 << (32 + 12);
115 }
116
117 nvkm_kmap(pgt);
118 while (cnt--) {
119 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys));
120 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys));
121 phys += next;
122 pte += 8;
123 }
124 nvkm_done(pgt);
125 }
126
127 void
128 gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
129 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
130 {
131 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
132 /* compressed storage types are invalid for system memory */
133 u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff];
134
135 nvkm_kmap(pgt);
136 pte <<= 3;
137 while (cnt--) {
138 u64 phys = gf100_vm_addr(vma, *list++, memtype, target);
139 nvkm_wo32(pgt, pte + 0, lower_32_bits(phys));
140 nvkm_wo32(pgt, pte + 4, upper_32_bits(phys));
141 pte += 8;
142 }
143 nvkm_done(pgt);
144 }
145
146 void
147 gf100_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
148 {
149 nvkm_kmap(pgt);
150 pte <<= 3;
151 while (cnt--) {
152 nvkm_wo32(pgt, pte + 0, 0x00000000);
153 nvkm_wo32(pgt, pte + 4, 0x00000000);
154 pte += 8;
155 }
156 nvkm_done(pgt);
157 }
158
159 void
160 gf100_vm_flush(struct nvkm_vm *vm)
161 {
162 struct nvkm_mmu *mmu = vm->mmu;
163 struct nvkm_device *device = mmu->subdev.device;
164 struct nvkm_vm_pgd *vpgd;
165 u32 type;
166
167 type = 0x00000001; /* PAGE_ALL */
168 if (atomic_read(&vm->engref[NVKM_SUBDEV_BAR]))
169 type |= 0x00000004; /* HUB_ONLY */
170
171 mutex_lock(&mmu->subdev.mutex);
172 list_for_each_entry(vpgd, &vm->pgd_list, head) {
173 /* looks like maybe a "free flush slots" counter, the
174 * faster you write to 0x100cbc to more it decreases
175 */
176 nvkm_msec(device, 2000,
177 if (nvkm_rd32(device, 0x100c80) & 0x00ff0000)
178 break;
179 );
180
181 nvkm_wr32(device, 0x100cb8, vpgd->obj->addr >> 8);
182 nvkm_wr32(device, 0x100cbc, 0x80000000 | type);
183
184 /* wait for flush to be queued? */
185 nvkm_msec(device, 2000,
186 if (nvkm_rd32(device, 0x100c80) & 0x00008000)
187 break;
188 );
189 }
190 mutex_unlock(&mmu->subdev.mutex);
191 }
192
193 static const struct nvkm_mmu_func
194 gf100_mmu = {
195 .limit = (1ULL << 40),
196 .dma_bits = 40,
197 .pgt_bits = 27 - 12,
198 .spg_shift = 12,
199 .lpg_shift = 17,
200 .map_pgt = gf100_vm_map_pgt,
201 .map = gf100_vm_map,
202 .map_sg = gf100_vm_map_sg,
203 .unmap = gf100_vm_unmap,
204 .flush = gf100_vm_flush,
205 .vmm = {{ -1, -1, NVIF_CLASS_VMM_GF100}, gf100_vmm_new },
206 };
207
208 int
209 gf100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
210 {
211 return nvkm_mmu_new_(&gf100_mmu, device, index, pmmu);
212 }