drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "vmm.h"
  25
  26 #include <core/option.h>
  27 #include <subdev/timer.h>
  28
  29 #include <nvif/class.h>
  30
  31 #define NV44_GART_SIZE (512 * 1024 * 1024)
  32 #define NV44_GART_PAGE (  4 * 1024)
  33
  34 /*******************************************************************************
  35  * VM map/unmap callbacks
  36  ******************************************************************************/
  37
  38 static void
  39 nv44_vm_fill(struct nvkm_memory *pgt, dma_addr_t null,
  40              dma_addr_t *list, u32 pte, u32 cnt)
  41 {
  42         u32 base = (pte << 2) & ~0x0000000f;
  43         u32 tmp[4];
  44
  45         tmp[0] = nvkm_ro32(pgt, base + 0x0);
  46         tmp[1] = nvkm_ro32(pgt, base + 0x4);
  47         tmp[2] = nvkm_ro32(pgt, base + 0x8);
  48         tmp[3] = nvkm_ro32(pgt, base + 0xc);
  49
  50         while (cnt--) {
  51                 u32 addr = list ? (*list++ >> 12) : (null >> 12);
  52                 switch (pte++ & 0x3) {
  53                 case 0:
  54                         tmp[0] &= ~0x07ffffff;
  55                         tmp[0] |= addr;
  56                         break;
  57                 case 1:
  58                         tmp[0] &= ~0xf8000000;
  59                         tmp[0] |= addr << 27;
  60                         tmp[1] &= ~0x003fffff;
  61                         tmp[1] |= addr >> 5;
  62                         break;
  63                 case 2:
  64                         tmp[1] &= ~0xffc00000;
  65                         tmp[1] |= addr << 22;
  66                         tmp[2] &= ~0x0001ffff;
  67                         tmp[2] |= addr >> 10;
  68                         break;
  69                 case 3:
  70                         tmp[2] &= ~0xfffe0000;
  71                         tmp[2] |= addr << 17;
  72                         tmp[3] &= ~0x00000fff;
  73                         tmp[3] |= addr >> 15;
  74                         break;
  75                 }
  76         }
  77
  78         nvkm_wo32(pgt, base + 0x0, tmp[0]);
  79         nvkm_wo32(pgt, base + 0x4, tmp[1]);
  80         nvkm_wo32(pgt, base + 0x8, tmp[2]);
  81         nvkm_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
  82 }
  83
  84 static void
  85 nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,
  86                struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
  87 {
  88         u32 tmp[4];
  89         int i;
  90
  91         nvkm_kmap(pgt);
  92         if (pte & 3) {
  93                 u32  max = 4 - (pte & 3);
  94                 u32 part = (cnt > max) ? max : cnt;
  95                 nv44_vm_fill(pgt, vma->vm->null, list, pte, part);
  96                 pte  += part;
  97                 list += part;
  98                 cnt  -= part;
  99         }
 100
 101         while (cnt >= 4) {
 102                 for (i = 0; i < 4; i++)
 103                         tmp[i] = *list++ >> 12;
 104                 nvkm_wo32(pgt, pte++ * 4, tmp[0] >>  0 | tmp[1] << 27);
 105                 nvkm_wo32(pgt, pte++ * 4, tmp[1] >>  5 | tmp[2] << 22);
 106                 nvkm_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
 107                 nvkm_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
 108                 cnt -= 4;
 109         }
 110
 111         if (cnt)
 112                 nv44_vm_fill(pgt, vma->vm->null, list, pte, cnt);
 113         nvkm_done(pgt);
 114 }
 115
 116 static void
 117 nv44_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
 118 {
 119         nvkm_kmap(pgt);
 120         if (pte & 3) {
 121                 u32  max = 4 - (pte & 3);
 122                 u32 part = (cnt > max) ? max : cnt;
 123                 nv44_vm_fill(pgt, vma->vm->null, NULL, pte, part);
 124                 pte  += part;
 125                 cnt  -= part;
 126         }
 127
 128         while (cnt >= 4) {
 129                 nvkm_wo32(pgt, pte++ * 4, 0x00000000);
 130                 nvkm_wo32(pgt, pte++ * 4, 0x00000000);
 131                 nvkm_wo32(pgt, pte++ * 4, 0x00000000);
 132                 nvkm_wo32(pgt, pte++ * 4, 0x00000000);
 133                 cnt -= 4;
 134         }
 135
 136         if (cnt)
 137                 nv44_vm_fill(pgt, vma->vm->null, NULL, pte, cnt);
 138         nvkm_done(pgt);
 139 }
 140
 141 static void
 142 nv44_vm_flush(struct nvkm_vm *vm)
 143 {
 144         struct nvkm_device *device = vm->mmu->subdev.device;
 145         nvkm_wr32(device, 0x100814, vm->mmu->limit - NV44_GART_PAGE);
 146         nvkm_wr32(device, 0x100808, 0x00000020);
 147         nvkm_msec(device, 2000,
 148                 if (nvkm_rd32(device, 0x100808) & 0x00000001)
 149                         break;
 150         );
 151         nvkm_wr32(device, 0x100808, 0x00000000);
 152 }
 153
 154 /*******************************************************************************
 155  * MMU subdev
 156  ******************************************************************************/
 157
 158 static int
 159 nv44_mmu_oneinit(struct nvkm_mmu *mmu)
 160 {
 161         mmu->vmm->pgt[0].mem[0] = mmu->vmm->pd->pt[0]->memory;
 162         mmu->vmm->pgt[0].refcount[0] = 1;
 163         return 0;
 164 }
 165
 166 static void
 167 nv44_mmu_init(struct nvkm_mmu *mmu)
 168 {
 169         struct nvkm_device *device = mmu->subdev.device;
 170         struct nvkm_memory *gart = mmu->vmm->pgt[0].mem[0];
 171         u32 addr;
 172
 173         /* calculate vram address of this PRAMIN block, object must be
 174          * allocated on 512KiB alignment, and not exceed a total size
 175          * of 512KiB for this to work correctly
 176          */
 177         addr  = nvkm_rd32(device, 0x10020c);
 178         addr -= ((nvkm_memory_addr(gart) >> 19) + 1) << 19;
 179
 180         nvkm_wr32(device, 0x100850, 0x80000000);
 181         nvkm_wr32(device, 0x100818, mmu->vmm->null);
 182         nvkm_wr32(device, 0x100804, NV44_GART_SIZE);
 183         nvkm_wr32(device, 0x100850, 0x00008000);
 184         nvkm_mask(device, 0x10008c, 0x00000200, 0x00000200);
 185         nvkm_wr32(device, 0x100820, 0x00000000);
 186         nvkm_wr32(device, 0x10082c, 0x00000001);
 187         nvkm_wr32(device, 0x100800, addr | 0x00000010);
 188 }
 189
 190 static const struct nvkm_mmu_func
 191 nv44_mmu = {
 192         .oneinit = nv44_mmu_oneinit,
 193         .init = nv44_mmu_init,
 194         .limit = NV44_GART_SIZE,
 195         .dma_bits = 39,
 196         .pgt_bits = 32 - 12,
 197         .spg_shift = 12,
 198         .lpg_shift = 12,
 199         .map_sg = nv44_vm_map_sg,
 200         .unmap = nv44_vm_unmap,
 201         .flush = nv44_vm_flush,
 202         .vmm = {{ -1, -1, NVIF_CLASS_VMM_NV04}, nv44_vmm_new, true },
 203 };
 204
 205 int
 206 nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
 207 {
 208         if (device->type == NVKM_DEVICE_AGP ||
 209             !nvkm_boolopt(device->cfgopt, "NvPCIE", true))
 210                 return nv04_mmu_new(device, index, pmmu);
 211
 212         return nvkm_mmu_new_(&nv44_mmu, device, index, pmmu);
 213 }