drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #define gf119_pmu_code gk104_pmu_code
  25 #define gf119_pmu_data gk104_pmu_data
  26 #include "priv.h"
  27 #include "fuc/gf119.fuc4.h"
  28
  29 #include <core/option.h>
  30 #include <subdev/timer.h>
  31
  32 static void
  33 magic_(struct nvkm_device *device, u32 ctrl, int size)
  34 {
  35         nvkm_wr32(device, 0x00c800, 0x00000000);
  36         nvkm_wr32(device, 0x00c808, 0x00000000);
  37         nvkm_wr32(device, 0x00c800, ctrl);
  38         nvkm_msec(device, 2000,
  39                 if (nvkm_rd32(device, 0x00c800) & 0x40000000) {
  40                         while (size--)
  41                                 nvkm_wr32(device, 0x00c804, 0x00000000);
  42                         break;
  43                 }
  44         );
  45         nvkm_wr32(device, 0x00c800, 0x00000000);
  46 }
  47
  48 static void
  49 magic(struct nvkm_device *device, u32 ctrl)
  50 {
  51         magic_(device, 0x8000a41f | ctrl, 6);
  52         magic_(device, 0x80000421 | ctrl, 1);
  53 }
  54
  55 static void
  56 gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
  57 {
  58         struct nvkm_device *device = pmu->subdev.device;
  59
  60         nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
  61         nvkm_rd32(device, 0x000200);
  62         nvkm_mask(device, 0x000200, 0x08000000, 0x08000000);
  63         msleep(50);
  64
  65         nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002);
  66         nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
  67         nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
  68
  69         nvkm_mask(device, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000);
  70         msleep(50);
  71
  72         nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000);
  73         nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
  74         nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
  75
  76         nvkm_mask(device, 0x000200, 0x08000000, 0x00000000);
  77         nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
  78         nvkm_rd32(device, 0x000200);
  79
  80         if ( nvkm_boolopt(device->cfgopt, "War00C800_0",
  81             device->quirk ? device->quirk->War00C800_0 : false)) {
  82                 nvkm_info(&pmu->subdev, "hw bug workaround enabled\n");
  83                 switch (device->chipset) {
  84                 case 0xe4:
  85                         magic(device, 0x04000000);
  86                         magic(device, 0x06000000);
  87                         magic(device, 0x0c000000);
  88                         magic(device, 0x0e000000);
  89                         break;
  90                 case 0xe6:
  91                         magic(device, 0x02000000);
  92                         magic(device, 0x04000000);
  93                         magic(device, 0x0a000000);
  94                         break;
  95                 case 0xe7:
  96                         magic(device, 0x02000000);
  97                         break;
  98                 default:
  99                         break;
 100                 }
 101         }
 102 }
 103
 104 static const struct nvkm_pmu_func
 105 gk104_pmu = {
 106         .code.data = gk104_pmu_code,
 107         .code.size = sizeof(gk104_pmu_code),
 108         .data.data = gk104_pmu_data,
 109         .data.size = sizeof(gk104_pmu_data),
 110         .pgob = gk104_pmu_pgob,
 111 };
 112
 113 int
 114 gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
 115 {
 116         return nvkm_pmu_new_(&gk104_pmu, device, index, ppmu);
 117 }