2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
42 #include <linux/component.h>
46 #include "dss_features.h"
50 #define DISPC_SZ_REGS SZ_4K
52 enum omap_burst_size
{
58 #define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
61 #define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64 struct dispc_features
{
75 unsigned long max_lcd_pclk
;
76 unsigned long max_tv_pclk
;
77 int (*calc_scaling
) (unsigned long pclk
, unsigned long lclk
,
78 const struct videomode
*mgr_timings
,
79 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
80 enum omap_color_mode color_mode
, bool *five_taps
,
81 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
82 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
);
83 unsigned long (*calc_core_clk
) (unsigned long pclk
,
84 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround
:1;
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv
:1;
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround
:1;
97 bool set_max_preload
:1;
99 /* PIXEL_INC is not added to the last pixel of a line */
100 bool last_pixel_inc_missing
:1;
102 /* POL_FREQ has ALIGN bit */
103 bool supports_sync_align
:1;
105 bool has_writeback
:1;
107 bool supports_double_pixel
:1;
110 * Field order for VENC is different than HDMI. We should handle this in
111 * some intelligent manner, but as the SoCs have either HDMI or VENC,
112 * never both, we can just use this flag for now.
114 bool reverse_ilace_field_order
:1;
116 bool has_gamma_table
:1;
118 bool has_gamma_i734_bug
:1;
121 #define DISPC_MAX_NR_FIFOS 5
122 #define DISPC_MAX_CHANNEL_GAMMA 4
125 struct platform_device
*pdev
;
129 irq_handler_t user_handler
;
132 unsigned long core_clk_rate
;
133 unsigned long tv_pclk_rate
;
135 u32 fifo_size
[DISPC_MAX_NR_FIFOS
];
136 /* maps which plane is using a fifo. fifo-id -> plane-id */
137 int fifo_assignment
[DISPC_MAX_NR_FIFOS
];
140 u32 ctx
[DISPC_SZ_REGS
/ sizeof(u32
)];
142 u32
*gamma_table
[DISPC_MAX_CHANNEL_GAMMA
];
144 const struct dispc_features
*feat
;
148 struct regmap
*syscon_pol
;
149 u32 syscon_pol_offset
;
151 /* DISPC_CONTROL & DISPC_CONFIG lock*/
152 spinlock_t control_lock
;
155 enum omap_color_component
{
156 /* used for all color formats for OMAP3 and earlier
157 * and for RGB and Y color component on OMAP4
159 DISPC_COLOR_COMPONENT_RGB_Y
= 1 << 0,
160 /* used for UV component for
161 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
162 * color formats on OMAP4
164 DISPC_COLOR_COMPONENT_UV
= 1 << 1,
167 enum mgr_reg_fields
{
168 DISPC_MGR_FLD_ENABLE
,
169 DISPC_MGR_FLD_STNTFT
,
171 DISPC_MGR_FLD_TFTDATALINES
,
172 DISPC_MGR_FLD_STALLMODE
,
173 DISPC_MGR_FLD_TCKENABLE
,
174 DISPC_MGR_FLD_TCKSELECTION
,
176 DISPC_MGR_FLD_FIFOHANDCHECK
,
177 /* used to maintain a count of the above fields */
181 struct dispc_reg_field
{
187 struct dispc_gamma_desc
{
194 static const struct {
199 struct dispc_gamma_desc gamma
;
200 struct dispc_reg_field reg_desc
[DISPC_MGR_FLD_NUM
];
202 [OMAP_DSS_CHANNEL_LCD
] = {
204 .vsync_irq
= DISPC_IRQ_VSYNC
,
205 .framedone_irq
= DISPC_IRQ_FRAMEDONE
,
206 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST
,
210 .reg
= DISPC_GAMMA_TABLE0
,
214 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL
, 0, 0 },
215 [DISPC_MGR_FLD_STNTFT
] = { DISPC_CONTROL
, 3, 3 },
216 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL
, 5, 5 },
217 [DISPC_MGR_FLD_TFTDATALINES
] = { DISPC_CONTROL
, 9, 8 },
218 [DISPC_MGR_FLD_STALLMODE
] = { DISPC_CONTROL
, 11, 11 },
219 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG
, 10, 10 },
220 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG
, 11, 11 },
221 [DISPC_MGR_FLD_CPR
] = { DISPC_CONFIG
, 15, 15 },
222 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG
, 16, 16 },
225 [OMAP_DSS_CHANNEL_DIGIT
] = {
227 .vsync_irq
= DISPC_IRQ_EVSYNC_ODD
| DISPC_IRQ_EVSYNC_EVEN
,
228 .framedone_irq
= DISPC_IRQ_FRAMEDONETV
,
229 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST_DIGIT
,
233 .reg
= DISPC_GAMMA_TABLE2
,
237 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL
, 1, 1 },
238 [DISPC_MGR_FLD_STNTFT
] = { },
239 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL
, 6, 6 },
240 [DISPC_MGR_FLD_TFTDATALINES
] = { },
241 [DISPC_MGR_FLD_STALLMODE
] = { },
242 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG
, 12, 12 },
243 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG
, 13, 13 },
244 [DISPC_MGR_FLD_CPR
] = { },
245 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG
, 16, 16 },
248 [OMAP_DSS_CHANNEL_LCD2
] = {
250 .vsync_irq
= DISPC_IRQ_VSYNC2
,
251 .framedone_irq
= DISPC_IRQ_FRAMEDONE2
,
252 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST2
,
256 .reg
= DISPC_GAMMA_TABLE1
,
260 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL2
, 0, 0 },
261 [DISPC_MGR_FLD_STNTFT
] = { DISPC_CONTROL2
, 3, 3 },
262 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL2
, 5, 5 },
263 [DISPC_MGR_FLD_TFTDATALINES
] = { DISPC_CONTROL2
, 9, 8 },
264 [DISPC_MGR_FLD_STALLMODE
] = { DISPC_CONTROL2
, 11, 11 },
265 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG2
, 10, 10 },
266 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG2
, 11, 11 },
267 [DISPC_MGR_FLD_CPR
] = { DISPC_CONFIG2
, 15, 15 },
268 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG2
, 16, 16 },
271 [OMAP_DSS_CHANNEL_LCD3
] = {
273 .vsync_irq
= DISPC_IRQ_VSYNC3
,
274 .framedone_irq
= DISPC_IRQ_FRAMEDONE3
,
275 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST3
,
279 .reg
= DISPC_GAMMA_TABLE3
,
283 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL3
, 0, 0 },
284 [DISPC_MGR_FLD_STNTFT
] = { DISPC_CONTROL3
, 3, 3 },
285 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL3
, 5, 5 },
286 [DISPC_MGR_FLD_TFTDATALINES
] = { DISPC_CONTROL3
, 9, 8 },
287 [DISPC_MGR_FLD_STALLMODE
] = { DISPC_CONTROL3
, 11, 11 },
288 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG3
, 10, 10 },
289 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG3
, 11, 11 },
290 [DISPC_MGR_FLD_CPR
] = { DISPC_CONFIG3
, 15, 15 },
291 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG3
, 16, 16 },
296 struct color_conv_coef
{
297 int ry
, rcr
, rcb
, gy
, gcr
, gcb
, by
, bcr
, bcb
;
301 static unsigned long dispc_fclk_rate(void);
302 static unsigned long dispc_core_clk_rate(void);
303 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel
);
304 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel
);
306 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane
);
307 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane
);
309 static inline void dispc_write_reg(const u16 idx
, u32 val
)
311 __raw_writel(val
, dispc
.base
+ idx
);
314 static inline u32
dispc_read_reg(const u16 idx
)
316 return __raw_readl(dispc
.base
+ idx
);
319 static u32
mgr_fld_read(enum omap_channel channel
, enum mgr_reg_fields regfld
)
321 const struct dispc_reg_field rfld
= mgr_desc
[channel
].reg_desc
[regfld
];
322 return REG_GET(rfld
.reg
, rfld
.high
, rfld
.low
);
325 static void mgr_fld_write(enum omap_channel channel
,
326 enum mgr_reg_fields regfld
, int val
) {
327 const struct dispc_reg_field rfld
= mgr_desc
[channel
].reg_desc
[regfld
];
328 const bool need_lock
= rfld
.reg
== DISPC_CONTROL
|| rfld
.reg
== DISPC_CONFIG
;
332 spin_lock_irqsave(&dispc
.control_lock
, flags
);
334 REG_FLD_MOD(rfld
.reg
, val
, rfld
.high
, rfld
.low
);
337 spin_unlock_irqrestore(&dispc
.control_lock
, flags
);
341 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
343 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
345 static void dispc_save_context(void)
349 DSSDBG("dispc_save_context\n");
355 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
) ||
356 dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
358 if (dss_has_feature(FEAT_MGR_LCD2
)) {
362 if (dss_has_feature(FEAT_MGR_LCD3
)) {
367 for (i
= 0; i
< dss_feat_get_num_mgrs(); i
++) {
368 SR(DEFAULT_COLOR(i
));
371 if (i
== OMAP_DSS_CHANNEL_DIGIT
)
382 if (dss_has_feature(FEAT_CPR
)) {
389 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++) {
394 SR(OVL_ATTRIBUTES(i
));
395 SR(OVL_FIFO_THRESHOLD(i
));
397 SR(OVL_PIXEL_INC(i
));
398 if (dss_has_feature(FEAT_PRELOAD
))
400 if (i
== OMAP_DSS_GFX
) {
401 SR(OVL_WINDOW_SKIP(i
));
406 SR(OVL_PICTURE_SIZE(i
));
410 for (j
= 0; j
< 8; j
++)
411 SR(OVL_FIR_COEF_H(i
, j
));
413 for (j
= 0; j
< 8; j
++)
414 SR(OVL_FIR_COEF_HV(i
, j
));
416 for (j
= 0; j
< 5; j
++)
417 SR(OVL_CONV_COEF(i
, j
));
419 if (dss_has_feature(FEAT_FIR_COEF_V
)) {
420 for (j
= 0; j
< 8; j
++)
421 SR(OVL_FIR_COEF_V(i
, j
));
424 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
431 for (j
= 0; j
< 8; j
++)
432 SR(OVL_FIR_COEF_H2(i
, j
));
434 for (j
= 0; j
< 8; j
++)
435 SR(OVL_FIR_COEF_HV2(i
, j
));
437 for (j
= 0; j
< 8; j
++)
438 SR(OVL_FIR_COEF_V2(i
, j
));
440 if (dss_has_feature(FEAT_ATTR2
))
441 SR(OVL_ATTRIBUTES2(i
));
444 if (dss_has_feature(FEAT_CORE_CLK_DIV
))
447 dispc
.ctx_valid
= true;
449 DSSDBG("context saved\n");
452 static void dispc_restore_context(void)
456 DSSDBG("dispc_restore_context\n");
458 if (!dispc
.ctx_valid
)
465 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
) ||
466 dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
468 if (dss_has_feature(FEAT_MGR_LCD2
))
470 if (dss_has_feature(FEAT_MGR_LCD3
))
473 for (i
= 0; i
< dss_feat_get_num_mgrs(); i
++) {
474 RR(DEFAULT_COLOR(i
));
477 if (i
== OMAP_DSS_CHANNEL_DIGIT
)
488 if (dss_has_feature(FEAT_CPR
)) {
495 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++) {
500 RR(OVL_ATTRIBUTES(i
));
501 RR(OVL_FIFO_THRESHOLD(i
));
503 RR(OVL_PIXEL_INC(i
));
504 if (dss_has_feature(FEAT_PRELOAD
))
506 if (i
== OMAP_DSS_GFX
) {
507 RR(OVL_WINDOW_SKIP(i
));
512 RR(OVL_PICTURE_SIZE(i
));
516 for (j
= 0; j
< 8; j
++)
517 RR(OVL_FIR_COEF_H(i
, j
));
519 for (j
= 0; j
< 8; j
++)
520 RR(OVL_FIR_COEF_HV(i
, j
));
522 for (j
= 0; j
< 5; j
++)
523 RR(OVL_CONV_COEF(i
, j
));
525 if (dss_has_feature(FEAT_FIR_COEF_V
)) {
526 for (j
= 0; j
< 8; j
++)
527 RR(OVL_FIR_COEF_V(i
, j
));
530 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
537 for (j
= 0; j
< 8; j
++)
538 RR(OVL_FIR_COEF_H2(i
, j
));
540 for (j
= 0; j
< 8; j
++)
541 RR(OVL_FIR_COEF_HV2(i
, j
));
543 for (j
= 0; j
< 8; j
++)
544 RR(OVL_FIR_COEF_V2(i
, j
));
546 if (dss_has_feature(FEAT_ATTR2
))
547 RR(OVL_ATTRIBUTES2(i
));
550 if (dss_has_feature(FEAT_CORE_CLK_DIV
))
553 /* enable last, because LCD & DIGIT enable are here */
555 if (dss_has_feature(FEAT_MGR_LCD2
))
557 if (dss_has_feature(FEAT_MGR_LCD3
))
559 /* clear spurious SYNC_LOST_DIGIT interrupts */
560 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT
);
563 * enable last so IRQs won't trigger before
564 * the context is fully restored
568 DSSDBG("context restored\n");
574 int dispc_runtime_get(void)
578 DSSDBG("dispc_runtime_get\n");
580 r
= pm_runtime_get_sync(&dispc
.pdev
->dev
);
582 return r
< 0 ? r
: 0;
584 EXPORT_SYMBOL(dispc_runtime_get
);
586 void dispc_runtime_put(void)
590 DSSDBG("dispc_runtime_put\n");
592 r
= pm_runtime_put_sync(&dispc
.pdev
->dev
);
593 WARN_ON(r
< 0 && r
!= -ENOSYS
);
595 EXPORT_SYMBOL(dispc_runtime_put
);
597 u32
dispc_mgr_get_vsync_irq(enum omap_channel channel
)
599 return mgr_desc
[channel
].vsync_irq
;
601 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq
);
603 u32
dispc_mgr_get_framedone_irq(enum omap_channel channel
)
605 if (channel
== OMAP_DSS_CHANNEL_DIGIT
&& dispc
.feat
->no_framedone_tv
)
608 return mgr_desc
[channel
].framedone_irq
;
610 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq
);
612 u32
dispc_mgr_get_sync_lost_irq(enum omap_channel channel
)
614 return mgr_desc
[channel
].sync_lost_irq
;
616 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq
);
618 u32
dispc_wb_get_framedone_irq(void)
620 return DISPC_IRQ_FRAMEDONEWB
;
623 bool dispc_mgr_go_busy(enum omap_channel channel
)
625 return mgr_fld_read(channel
, DISPC_MGR_FLD_GO
) == 1;
627 EXPORT_SYMBOL(dispc_mgr_go_busy
);
629 void dispc_mgr_go(enum omap_channel channel
)
631 WARN_ON(!dispc_mgr_is_enabled(channel
));
632 WARN_ON(dispc_mgr_go_busy(channel
));
634 DSSDBG("GO %s\n", mgr_desc
[channel
].name
);
636 mgr_fld_write(channel
, DISPC_MGR_FLD_GO
, 1);
638 EXPORT_SYMBOL(dispc_mgr_go
);
640 bool dispc_wb_go_busy(void)
642 return REG_GET(DISPC_CONTROL2
, 6, 6) == 1;
645 void dispc_wb_go(void)
647 enum omap_plane plane
= OMAP_DSS_WB
;
650 enable
= REG_GET(DISPC_OVL_ATTRIBUTES(plane
), 0, 0) == 1;
655 go
= REG_GET(DISPC_CONTROL2
, 6, 6) == 1;
657 DSSERR("GO bit not down for WB\n");
661 REG_FLD_MOD(DISPC_CONTROL2
, 1, 6, 6);
664 static void dispc_ovl_write_firh_reg(enum omap_plane plane
, int reg
, u32 value
)
666 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane
, reg
), value
);
669 static void dispc_ovl_write_firhv_reg(enum omap_plane plane
, int reg
, u32 value
)
671 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane
, reg
), value
);
674 static void dispc_ovl_write_firv_reg(enum omap_plane plane
, int reg
, u32 value
)
676 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane
, reg
), value
);
679 static void dispc_ovl_write_firh2_reg(enum omap_plane plane
, int reg
, u32 value
)
681 BUG_ON(plane
== OMAP_DSS_GFX
);
683 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane
, reg
), value
);
686 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane
, int reg
,
689 BUG_ON(plane
== OMAP_DSS_GFX
);
691 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane
, reg
), value
);
694 static void dispc_ovl_write_firv2_reg(enum omap_plane plane
, int reg
, u32 value
)
696 BUG_ON(plane
== OMAP_DSS_GFX
);
698 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane
, reg
), value
);
701 static void dispc_ovl_set_scale_coef(enum omap_plane plane
, int fir_hinc
,
702 int fir_vinc
, int five_taps
,
703 enum omap_color_component color_comp
)
705 const struct dispc_coef
*h_coef
, *v_coef
;
708 h_coef
= dispc_ovl_get_scale_coef(fir_hinc
, true);
709 v_coef
= dispc_ovl_get_scale_coef(fir_vinc
, five_taps
);
711 for (i
= 0; i
< 8; i
++) {
714 h
= FLD_VAL(h_coef
[i
].hc0_vc00
, 7, 0)
715 | FLD_VAL(h_coef
[i
].hc1_vc0
, 15, 8)
716 | FLD_VAL(h_coef
[i
].hc2_vc1
, 23, 16)
717 | FLD_VAL(h_coef
[i
].hc3_vc2
, 31, 24);
718 hv
= FLD_VAL(h_coef
[i
].hc4_vc22
, 7, 0)
719 | FLD_VAL(v_coef
[i
].hc1_vc0
, 15, 8)
720 | FLD_VAL(v_coef
[i
].hc2_vc1
, 23, 16)
721 | FLD_VAL(v_coef
[i
].hc3_vc2
, 31, 24);
723 if (color_comp
== DISPC_COLOR_COMPONENT_RGB_Y
) {
724 dispc_ovl_write_firh_reg(plane
, i
, h
);
725 dispc_ovl_write_firhv_reg(plane
, i
, hv
);
727 dispc_ovl_write_firh2_reg(plane
, i
, h
);
728 dispc_ovl_write_firhv2_reg(plane
, i
, hv
);
734 for (i
= 0; i
< 8; i
++) {
736 v
= FLD_VAL(v_coef
[i
].hc0_vc00
, 7, 0)
737 | FLD_VAL(v_coef
[i
].hc4_vc22
, 15, 8);
738 if (color_comp
== DISPC_COLOR_COMPONENT_RGB_Y
)
739 dispc_ovl_write_firv_reg(plane
, i
, v
);
741 dispc_ovl_write_firv2_reg(plane
, i
, v
);
747 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane
,
748 const struct color_conv_coef
*ct
)
750 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
752 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 0), CVAL(ct
->rcr
, ct
->ry
));
753 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 1), CVAL(ct
->gy
, ct
->rcb
));
754 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 2), CVAL(ct
->gcb
, ct
->gcr
));
755 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 3), CVAL(ct
->bcr
, ct
->by
));
756 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 4), CVAL(0, ct
->bcb
));
758 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), ct
->full_range
, 11, 11);
763 static void dispc_setup_color_conv_coef(void)
766 int num_ovl
= dss_feat_get_num_ovls();
767 const struct color_conv_coef ctbl_bt601_5_ovl
= {
769 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
771 const struct color_conv_coef ctbl_bt601_5_wb
= {
773 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
776 for (i
= 1; i
< num_ovl
; i
++)
777 dispc_ovl_write_color_conv_coef(i
, &ctbl_bt601_5_ovl
);
779 if (dispc
.feat
->has_writeback
)
780 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB
, &ctbl_bt601_5_wb
);
783 static void dispc_ovl_set_ba0(enum omap_plane plane
, u32 paddr
)
785 dispc_write_reg(DISPC_OVL_BA0(plane
), paddr
);
788 static void dispc_ovl_set_ba1(enum omap_plane plane
, u32 paddr
)
790 dispc_write_reg(DISPC_OVL_BA1(plane
), paddr
);
793 static void dispc_ovl_set_ba0_uv(enum omap_plane plane
, u32 paddr
)
795 dispc_write_reg(DISPC_OVL_BA0_UV(plane
), paddr
);
798 static void dispc_ovl_set_ba1_uv(enum omap_plane plane
, u32 paddr
)
800 dispc_write_reg(DISPC_OVL_BA1_UV(plane
), paddr
);
803 static void dispc_ovl_set_pos(enum omap_plane plane
,
804 enum omap_overlay_caps caps
, int x
, int y
)
808 if ((caps
& OMAP_DSS_OVL_CAP_POS
) == 0)
811 val
= FLD_VAL(y
, 26, 16) | FLD_VAL(x
, 10, 0);
813 dispc_write_reg(DISPC_OVL_POSITION(plane
), val
);
816 static void dispc_ovl_set_input_size(enum omap_plane plane
, int width
,
819 u32 val
= FLD_VAL(height
- 1, 26, 16) | FLD_VAL(width
- 1, 10, 0);
821 if (plane
== OMAP_DSS_GFX
|| plane
== OMAP_DSS_WB
)
822 dispc_write_reg(DISPC_OVL_SIZE(plane
), val
);
824 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane
), val
);
827 static void dispc_ovl_set_output_size(enum omap_plane plane
, int width
,
832 BUG_ON(plane
== OMAP_DSS_GFX
);
834 val
= FLD_VAL(height
- 1, 26, 16) | FLD_VAL(width
- 1, 10, 0);
836 if (plane
== OMAP_DSS_WB
)
837 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane
), val
);
839 dispc_write_reg(DISPC_OVL_SIZE(plane
), val
);
842 static void dispc_ovl_set_zorder(enum omap_plane plane
,
843 enum omap_overlay_caps caps
, u8 zorder
)
845 if ((caps
& OMAP_DSS_OVL_CAP_ZORDER
) == 0)
848 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), zorder
, 27, 26);
851 static void dispc_ovl_enable_zorder_planes(void)
855 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
858 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++)
859 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i
), 1, 25, 25);
862 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane
,
863 enum omap_overlay_caps caps
, bool enable
)
865 if ((caps
& OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
) == 0)
868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
? 1 : 0, 28, 28);
871 static void dispc_ovl_setup_global_alpha(enum omap_plane plane
,
872 enum omap_overlay_caps caps
, u8 global_alpha
)
874 static const unsigned shifts
[] = { 0, 8, 16, 24, };
877 if ((caps
& OMAP_DSS_OVL_CAP_GLOBAL_ALPHA
) == 0)
880 shift
= shifts
[plane
];
881 REG_FLD_MOD(DISPC_GLOBAL_ALPHA
, global_alpha
, shift
+ 7, shift
);
884 static void dispc_ovl_set_pix_inc(enum omap_plane plane
, s32 inc
)
886 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane
), inc
);
889 static void dispc_ovl_set_row_inc(enum omap_plane plane
, s32 inc
)
891 dispc_write_reg(DISPC_OVL_ROW_INC(plane
), inc
);
894 static void dispc_ovl_set_color_mode(enum omap_plane plane
,
895 enum omap_color_mode color_mode
)
898 if (plane
!= OMAP_DSS_GFX
) {
899 switch (color_mode
) {
900 case OMAP_DSS_COLOR_NV12
:
902 case OMAP_DSS_COLOR_RGBX16
:
904 case OMAP_DSS_COLOR_RGBA16
:
906 case OMAP_DSS_COLOR_RGB12U
:
908 case OMAP_DSS_COLOR_ARGB16
:
910 case OMAP_DSS_COLOR_RGB16
:
912 case OMAP_DSS_COLOR_ARGB16_1555
:
914 case OMAP_DSS_COLOR_RGB24U
:
916 case OMAP_DSS_COLOR_RGB24P
:
918 case OMAP_DSS_COLOR_YUV2
:
920 case OMAP_DSS_COLOR_UYVY
:
922 case OMAP_DSS_COLOR_ARGB32
:
924 case OMAP_DSS_COLOR_RGBA32
:
926 case OMAP_DSS_COLOR_RGBX32
:
928 case OMAP_DSS_COLOR_XRGB16_1555
:
934 switch (color_mode
) {
935 case OMAP_DSS_COLOR_CLUT1
:
937 case OMAP_DSS_COLOR_CLUT2
:
939 case OMAP_DSS_COLOR_CLUT4
:
941 case OMAP_DSS_COLOR_CLUT8
:
943 case OMAP_DSS_COLOR_RGB12U
:
945 case OMAP_DSS_COLOR_ARGB16
:
947 case OMAP_DSS_COLOR_RGB16
:
949 case OMAP_DSS_COLOR_ARGB16_1555
:
951 case OMAP_DSS_COLOR_RGB24U
:
953 case OMAP_DSS_COLOR_RGB24P
:
955 case OMAP_DSS_COLOR_RGBX16
:
957 case OMAP_DSS_COLOR_RGBA16
:
959 case OMAP_DSS_COLOR_ARGB32
:
961 case OMAP_DSS_COLOR_RGBA32
:
963 case OMAP_DSS_COLOR_RGBX32
:
965 case OMAP_DSS_COLOR_XRGB16_1555
:
972 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), m
, 4, 1);
975 static void dispc_ovl_configure_burst_type(enum omap_plane plane
,
976 enum omap_dss_rotation_type rotation_type
)
978 if (dss_has_feature(FEAT_BURST_2D
) == 0)
981 if (rotation_type
== OMAP_DSS_ROT_TILER
)
982 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), 1, 29, 29);
984 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), 0, 29, 29);
987 void dispc_ovl_set_channel_out(enum omap_plane plane
, enum omap_channel channel
)
991 int chan
= 0, chan2
= 0;
997 case OMAP_DSS_VIDEO1
:
998 case OMAP_DSS_VIDEO2
:
999 case OMAP_DSS_VIDEO3
:
1007 val
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
1008 if (dss_has_feature(FEAT_MGR_LCD2
)) {
1010 case OMAP_DSS_CHANNEL_LCD
:
1014 case OMAP_DSS_CHANNEL_DIGIT
:
1018 case OMAP_DSS_CHANNEL_LCD2
:
1022 case OMAP_DSS_CHANNEL_LCD3
:
1023 if (dss_has_feature(FEAT_MGR_LCD3
)) {
1031 case OMAP_DSS_CHANNEL_WB
:
1040 val
= FLD_MOD(val
, chan
, shift
, shift
);
1041 val
= FLD_MOD(val
, chan2
, 31, 30);
1043 val
= FLD_MOD(val
, channel
, shift
, shift
);
1045 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), val
);
1047 EXPORT_SYMBOL(dispc_ovl_set_channel_out
);
1049 static enum omap_channel
dispc_ovl_get_channel_out(enum omap_plane plane
)
1058 case OMAP_DSS_VIDEO1
:
1059 case OMAP_DSS_VIDEO2
:
1060 case OMAP_DSS_VIDEO3
:
1068 val
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
1070 if (FLD_GET(val
, shift
, shift
) == 1)
1071 return OMAP_DSS_CHANNEL_DIGIT
;
1073 if (!dss_has_feature(FEAT_MGR_LCD2
))
1074 return OMAP_DSS_CHANNEL_LCD
;
1076 switch (FLD_GET(val
, 31, 30)) {
1079 return OMAP_DSS_CHANNEL_LCD
;
1081 return OMAP_DSS_CHANNEL_LCD2
;
1083 return OMAP_DSS_CHANNEL_LCD3
;
1085 return OMAP_DSS_CHANNEL_WB
;
1089 void dispc_wb_set_channel_in(enum dss_writeback_channel channel
)
1091 enum omap_plane plane
= OMAP_DSS_WB
;
1093 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), channel
, 18, 16);
1096 static void dispc_ovl_set_burst_size(enum omap_plane plane
,
1097 enum omap_burst_size burst_size
)
1099 static const unsigned shifts
[] = { 6, 14, 14, 14, 14, };
1102 shift
= shifts
[plane
];
1103 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), burst_size
, shift
+ 1, shift
);
1106 static void dispc_configure_burst_sizes(void)
1109 const int burst_size
= BURST_SIZE_X8
;
1111 /* Configure burst size always to maximum size */
1112 for (i
= 0; i
< dss_feat_get_num_ovls(); ++i
)
1113 dispc_ovl_set_burst_size(i
, burst_size
);
1114 if (dispc
.feat
->has_writeback
)
1115 dispc_ovl_set_burst_size(OMAP_DSS_WB
, burst_size
);
1118 static u32
dispc_ovl_get_burst_size(enum omap_plane plane
)
1120 unsigned unit
= dss_feat_get_burst_size_unit();
1121 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1125 static void dispc_mgr_enable_cpr(enum omap_channel channel
, bool enable
)
1127 if (channel
== OMAP_DSS_CHANNEL_DIGIT
)
1130 mgr_fld_write(channel
, DISPC_MGR_FLD_CPR
, enable
);
1133 static void dispc_mgr_set_cpr_coef(enum omap_channel channel
,
1134 const struct omap_dss_cpr_coefs
*coefs
)
1136 u32 coef_r
, coef_g
, coef_b
;
1138 if (!dss_mgr_is_lcd(channel
))
1141 coef_r
= FLD_VAL(coefs
->rr
, 31, 22) | FLD_VAL(coefs
->rg
, 20, 11) |
1142 FLD_VAL(coefs
->rb
, 9, 0);
1143 coef_g
= FLD_VAL(coefs
->gr
, 31, 22) | FLD_VAL(coefs
->gg
, 20, 11) |
1144 FLD_VAL(coefs
->gb
, 9, 0);
1145 coef_b
= FLD_VAL(coefs
->br
, 31, 22) | FLD_VAL(coefs
->bg
, 20, 11) |
1146 FLD_VAL(coefs
->bb
, 9, 0);
1148 dispc_write_reg(DISPC_CPR_COEF_R(channel
), coef_r
);
1149 dispc_write_reg(DISPC_CPR_COEF_G(channel
), coef_g
);
1150 dispc_write_reg(DISPC_CPR_COEF_B(channel
), coef_b
);
1153 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane
, bool enable
)
1157 BUG_ON(plane
== OMAP_DSS_GFX
);
1159 val
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
1160 val
= FLD_MOD(val
, enable
, 9, 9);
1161 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), val
);
1164 static void dispc_ovl_enable_replication(enum omap_plane plane
,
1165 enum omap_overlay_caps caps
, bool enable
)
1167 static const unsigned shifts
[] = { 5, 10, 10, 10 };
1170 if ((caps
& OMAP_DSS_OVL_CAP_REPLICATION
) == 0)
1173 shift
= shifts
[plane
];
1174 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
, shift
, shift
);
1177 static void dispc_mgr_set_size(enum omap_channel channel
, u16 width
,
1182 val
= FLD_VAL(height
- 1, dispc
.feat
->mgr_height_start
, 16) |
1183 FLD_VAL(width
- 1, dispc
.feat
->mgr_width_start
, 0);
1185 dispc_write_reg(DISPC_SIZE_MGR(channel
), val
);
1188 static void dispc_init_fifos(void)
1196 unit
= dss_feat_get_buffer_size_unit();
1198 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE
, &start
, &end
);
1200 for (fifo
= 0; fifo
< dispc
.feat
->num_fifos
; ++fifo
) {
1201 size
= REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo
), start
, end
);
1203 dispc
.fifo_size
[fifo
] = size
;
1206 * By default fifos are mapped directly to overlays, fifo 0 to
1207 * ovl 0, fifo 1 to ovl 1, etc.
1209 dispc
.fifo_assignment
[fifo
] = fifo
;
1213 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1214 * causes problems with certain use cases, like using the tiler in 2D
1215 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1216 * giving GFX plane a larger fifo. WB but should work fine with a
1219 if (dispc
.feat
->gfx_fifo_workaround
) {
1222 v
= dispc_read_reg(DISPC_GLOBAL_BUFFER
);
1224 v
= FLD_MOD(v
, 4, 2, 0); /* GFX BUF top to WB */
1225 v
= FLD_MOD(v
, 4, 5, 3); /* GFX BUF bottom to WB */
1226 v
= FLD_MOD(v
, 0, 26, 24); /* WB BUF top to GFX */
1227 v
= FLD_MOD(v
, 0, 29, 27); /* WB BUF bottom to GFX */
1229 dispc_write_reg(DISPC_GLOBAL_BUFFER
, v
);
1231 dispc
.fifo_assignment
[OMAP_DSS_GFX
] = OMAP_DSS_WB
;
1232 dispc
.fifo_assignment
[OMAP_DSS_WB
] = OMAP_DSS_GFX
;
1236 * Setup default fifo thresholds.
1238 for (i
= 0; i
< dss_feat_get_num_ovls(); ++i
) {
1240 const bool use_fifomerge
= false;
1241 const bool manual_update
= false;
1243 dispc_ovl_compute_fifo_thresholds(i
, &low
, &high
,
1244 use_fifomerge
, manual_update
);
1246 dispc_ovl_set_fifo_threshold(i
, low
, high
);
1249 if (dispc
.feat
->has_writeback
) {
1251 const bool use_fifomerge
= false;
1252 const bool manual_update
= false;
1254 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB
, &low
, &high
,
1255 use_fifomerge
, manual_update
);
1257 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB
, low
, high
);
1261 static u32
dispc_ovl_get_fifo_size(enum omap_plane plane
)
1266 for (fifo
= 0; fifo
< dispc
.feat
->num_fifos
; ++fifo
) {
1267 if (dispc
.fifo_assignment
[fifo
] == plane
)
1268 size
+= dispc
.fifo_size
[fifo
];
1274 void dispc_ovl_set_fifo_threshold(enum omap_plane plane
, u32 low
, u32 high
)
1276 u8 hi_start
, hi_end
, lo_start
, lo_end
;
1279 unit
= dss_feat_get_buffer_size_unit();
1281 WARN_ON(low
% unit
!= 0);
1282 WARN_ON(high
% unit
!= 0);
1287 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD
, &hi_start
, &hi_end
);
1288 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD
, &lo_start
, &lo_end
);
1290 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1292 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane
),
1293 lo_start
, lo_end
) * unit
,
1294 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane
),
1295 hi_start
, hi_end
) * unit
,
1296 low
* unit
, high
* unit
);
1298 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane
),
1299 FLD_VAL(high
, hi_start
, hi_end
) |
1300 FLD_VAL(low
, lo_start
, lo_end
));
1303 * configure the preload to the pipeline's high threhold, if HT it's too
1304 * large for the preload field, set the threshold to the maximum value
1305 * that can be held by the preload register
1307 if (dss_has_feature(FEAT_PRELOAD
) && dispc
.feat
->set_max_preload
&&
1308 plane
!= OMAP_DSS_WB
)
1309 dispc_write_reg(DISPC_OVL_PRELOAD(plane
), min(high
, 0xfffu
));
1312 void dispc_enable_fifomerge(bool enable
)
1314 if (!dss_has_feature(FEAT_FIFO_MERGE
)) {
1319 DSSDBG("FIFO merge %s\n", enable
? "enabled" : "disabled");
1320 REG_FLD_MOD(DISPC_CONFIG
, enable
? 1 : 0, 14, 14);
1323 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane
,
1324 u32
*fifo_low
, u32
*fifo_high
, bool use_fifomerge
,
1328 * All sizes are in bytes. Both the buffer and burst are made of
1329 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1332 unsigned buf_unit
= dss_feat_get_buffer_size_unit();
1333 unsigned ovl_fifo_size
, total_fifo_size
, burst_size
;
1336 burst_size
= dispc_ovl_get_burst_size(plane
);
1337 ovl_fifo_size
= dispc_ovl_get_fifo_size(plane
);
1339 if (use_fifomerge
) {
1340 total_fifo_size
= 0;
1341 for (i
= 0; i
< dss_feat_get_num_ovls(); ++i
)
1342 total_fifo_size
+= dispc_ovl_get_fifo_size(i
);
1344 total_fifo_size
= ovl_fifo_size
;
1348 * We use the same low threshold for both fifomerge and non-fifomerge
1349 * cases, but for fifomerge we calculate the high threshold using the
1350 * combined fifo size
1353 if (manual_update
&& dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG
)) {
1354 *fifo_low
= ovl_fifo_size
- burst_size
* 2;
1355 *fifo_high
= total_fifo_size
- burst_size
;
1356 } else if (plane
== OMAP_DSS_WB
) {
1358 * Most optimal configuration for writeback is to push out data
1359 * to the interconnect the moment writeback pushes enough pixels
1360 * in the FIFO to form a burst
1363 *fifo_high
= burst_size
;
1365 *fifo_low
= ovl_fifo_size
- burst_size
;
1366 *fifo_high
= total_fifo_size
- buf_unit
;
1370 static void dispc_ovl_set_mflag(enum omap_plane plane
, bool enable
)
1374 if (plane
== OMAP_DSS_GFX
)
1379 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
, bit
, bit
);
1382 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane
,
1385 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane
),
1386 FLD_VAL(high
, 31, 16) | FLD_VAL(low
, 15, 0));
1389 static void dispc_init_mflag(void)
1394 * HACK: NV12 color format and MFLAG seem to have problems working
1395 * together: using two displays, and having an NV12 overlay on one of
1396 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1397 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1398 * remove the errors, but there doesn't seem to be a clear logic on
1399 * which values work and which not.
1401 * As a work-around, set force MFLAG to always on.
1403 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE
,
1404 (1 << 0) | /* MFLAG_CTRL = force always on */
1405 (0 << 2)); /* MFLAG_START = disable */
1407 for (i
= 0; i
< dss_feat_get_num_ovls(); ++i
) {
1408 u32 size
= dispc_ovl_get_fifo_size(i
);
1409 u32 unit
= dss_feat_get_buffer_size_unit();
1412 dispc_ovl_set_mflag(i
, true);
1415 * Simulation team suggests below thesholds:
1416 * HT = fifosize * 5 / 8;
1417 * LT = fifosize * 4 / 8;
1420 low
= size
* 4 / 8 / unit
;
1421 high
= size
* 5 / 8 / unit
;
1423 dispc_ovl_set_mflag_threshold(i
, low
, high
);
1426 if (dispc
.feat
->has_writeback
) {
1427 u32 size
= dispc_ovl_get_fifo_size(OMAP_DSS_WB
);
1428 u32 unit
= dss_feat_get_buffer_size_unit();
1431 dispc_ovl_set_mflag(OMAP_DSS_WB
, true);
1434 * Simulation team suggests below thesholds:
1435 * HT = fifosize * 5 / 8;
1436 * LT = fifosize * 4 / 8;
1439 low
= size
* 4 / 8 / unit
;
1440 high
= size
* 5 / 8 / unit
;
1442 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB
, low
, high
);
1446 static void dispc_ovl_set_fir(enum omap_plane plane
,
1448 enum omap_color_component color_comp
)
1452 if (color_comp
== DISPC_COLOR_COMPONENT_RGB_Y
) {
1453 u8 hinc_start
, hinc_end
, vinc_start
, vinc_end
;
1455 dss_feat_get_reg_field(FEAT_REG_FIRHINC
,
1456 &hinc_start
, &hinc_end
);
1457 dss_feat_get_reg_field(FEAT_REG_FIRVINC
,
1458 &vinc_start
, &vinc_end
);
1459 val
= FLD_VAL(vinc
, vinc_start
, vinc_end
) |
1460 FLD_VAL(hinc
, hinc_start
, hinc_end
);
1462 dispc_write_reg(DISPC_OVL_FIR(plane
), val
);
1464 val
= FLD_VAL(vinc
, 28, 16) | FLD_VAL(hinc
, 12, 0);
1465 dispc_write_reg(DISPC_OVL_FIR2(plane
), val
);
1469 static void dispc_ovl_set_vid_accu0(enum omap_plane plane
, int haccu
, int vaccu
)
1472 u8 hor_start
, hor_end
, vert_start
, vert_end
;
1474 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU
, &hor_start
, &hor_end
);
1475 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU
, &vert_start
, &vert_end
);
1477 val
= FLD_VAL(vaccu
, vert_start
, vert_end
) |
1478 FLD_VAL(haccu
, hor_start
, hor_end
);
1480 dispc_write_reg(DISPC_OVL_ACCU0(plane
), val
);
1483 static void dispc_ovl_set_vid_accu1(enum omap_plane plane
, int haccu
, int vaccu
)
1486 u8 hor_start
, hor_end
, vert_start
, vert_end
;
1488 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU
, &hor_start
, &hor_end
);
1489 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU
, &vert_start
, &vert_end
);
1491 val
= FLD_VAL(vaccu
, vert_start
, vert_end
) |
1492 FLD_VAL(haccu
, hor_start
, hor_end
);
1494 dispc_write_reg(DISPC_OVL_ACCU1(plane
), val
);
1497 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane
, int haccu
,
1502 val
= FLD_VAL(vaccu
, 26, 16) | FLD_VAL(haccu
, 10, 0);
1503 dispc_write_reg(DISPC_OVL_ACCU2_0(plane
), val
);
1506 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane
, int haccu
,
1511 val
= FLD_VAL(vaccu
, 26, 16) | FLD_VAL(haccu
, 10, 0);
1512 dispc_write_reg(DISPC_OVL_ACCU2_1(plane
), val
);
1515 static void dispc_ovl_set_scale_param(enum omap_plane plane
,
1516 u16 orig_width
, u16 orig_height
,
1517 u16 out_width
, u16 out_height
,
1518 bool five_taps
, u8 rotation
,
1519 enum omap_color_component color_comp
)
1521 int fir_hinc
, fir_vinc
;
1523 fir_hinc
= 1024 * orig_width
/ out_width
;
1524 fir_vinc
= 1024 * orig_height
/ out_height
;
1526 dispc_ovl_set_scale_coef(plane
, fir_hinc
, fir_vinc
, five_taps
,
1528 dispc_ovl_set_fir(plane
, fir_hinc
, fir_vinc
, color_comp
);
1531 static void dispc_ovl_set_accu_uv(enum omap_plane plane
,
1532 u16 orig_width
, u16 orig_height
, u16 out_width
, u16 out_height
,
1533 bool ilace
, enum omap_color_mode color_mode
, u8 rotation
)
1535 int h_accu2_0
, h_accu2_1
;
1536 int v_accu2_0
, v_accu2_1
;
1537 int chroma_hinc
, chroma_vinc
;
1547 const struct accu
*accu_table
;
1548 const struct accu
*accu_val
;
1550 static const struct accu accu_nv12
[4] = {
1551 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1552 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1553 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1554 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1557 static const struct accu accu_nv12_ilace
[4] = {
1558 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1559 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1560 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1561 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1564 static const struct accu accu_yuv
[4] = {
1565 { 0, 1, 0, 1, 0, 1, 0, 1 },
1566 { 0, 1, 0, 1, 0, 1, 0, 1 },
1567 { -1, 1, 0, 1, 0, 1, 0, 1 },
1568 { 0, 1, 0, 1, -1, 1, 0, 1 },
1572 case OMAP_DSS_ROT_0
:
1575 case OMAP_DSS_ROT_90
:
1578 case OMAP_DSS_ROT_180
:
1581 case OMAP_DSS_ROT_270
:
1589 switch (color_mode
) {
1590 case OMAP_DSS_COLOR_NV12
:
1592 accu_table
= accu_nv12_ilace
;
1594 accu_table
= accu_nv12
;
1596 case OMAP_DSS_COLOR_YUV2
:
1597 case OMAP_DSS_COLOR_UYVY
:
1598 accu_table
= accu_yuv
;
1605 accu_val
= &accu_table
[idx
];
1607 chroma_hinc
= 1024 * orig_width
/ out_width
;
1608 chroma_vinc
= 1024 * orig_height
/ out_height
;
1610 h_accu2_0
= (accu_val
->h0_m
* chroma_hinc
/ accu_val
->h0_n
) % 1024;
1611 h_accu2_1
= (accu_val
->h1_m
* chroma_hinc
/ accu_val
->h1_n
) % 1024;
1612 v_accu2_0
= (accu_val
->v0_m
* chroma_vinc
/ accu_val
->v0_n
) % 1024;
1613 v_accu2_1
= (accu_val
->v1_m
* chroma_vinc
/ accu_val
->v1_n
) % 1024;
1615 dispc_ovl_set_vid_accu2_0(plane
, h_accu2_0
, v_accu2_0
);
1616 dispc_ovl_set_vid_accu2_1(plane
, h_accu2_1
, v_accu2_1
);
1619 static void dispc_ovl_set_scaling_common(enum omap_plane plane
,
1620 u16 orig_width
, u16 orig_height
,
1621 u16 out_width
, u16 out_height
,
1622 bool ilace
, bool five_taps
,
1623 bool fieldmode
, enum omap_color_mode color_mode
,
1630 dispc_ovl_set_scale_param(plane
, orig_width
, orig_height
,
1631 out_width
, out_height
, five_taps
,
1632 rotation
, DISPC_COLOR_COMPONENT_RGB_Y
);
1633 l
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
1635 /* RESIZEENABLE and VERTICALTAPS */
1636 l
&= ~((0x3 << 5) | (0x1 << 21));
1637 l
|= (orig_width
!= out_width
) ? (1 << 5) : 0;
1638 l
|= (orig_height
!= out_height
) ? (1 << 6) : 0;
1639 l
|= five_taps
? (1 << 21) : 0;
1641 /* VRESIZECONF and HRESIZECONF */
1642 if (dss_has_feature(FEAT_RESIZECONF
)) {
1644 l
|= (orig_width
<= out_width
) ? 0 : (1 << 7);
1645 l
|= (orig_height
<= out_height
) ? 0 : (1 << 8);
1648 /* LINEBUFFERSPLIT */
1649 if (dss_has_feature(FEAT_LINEBUFFERSPLIT
)) {
1651 l
|= five_taps
? (1 << 22) : 0;
1654 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), l
);
1657 * field 0 = even field = bottom field
1658 * field 1 = odd field = top field
1660 if (ilace
&& !fieldmode
) {
1662 accu0
= ((1024 * orig_height
/ out_height
) / 2) & 0x3ff;
1663 if (accu0
>= 1024/2) {
1669 dispc_ovl_set_vid_accu0(plane
, 0, accu0
);
1670 dispc_ovl_set_vid_accu1(plane
, 0, accu1
);
1673 static void dispc_ovl_set_scaling_uv(enum omap_plane plane
,
1674 u16 orig_width
, u16 orig_height
,
1675 u16 out_width
, u16 out_height
,
1676 bool ilace
, bool five_taps
,
1677 bool fieldmode
, enum omap_color_mode color_mode
,
1680 int scale_x
= out_width
!= orig_width
;
1681 int scale_y
= out_height
!= orig_height
;
1682 bool chroma_upscale
= plane
!= OMAP_DSS_WB
;
1684 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE
))
1686 if ((color_mode
!= OMAP_DSS_COLOR_YUV2
&&
1687 color_mode
!= OMAP_DSS_COLOR_UYVY
&&
1688 color_mode
!= OMAP_DSS_COLOR_NV12
)) {
1689 /* reset chroma resampling for RGB formats */
1690 if (plane
!= OMAP_DSS_WB
)
1691 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane
), 0, 8, 8);
1695 dispc_ovl_set_accu_uv(plane
, orig_width
, orig_height
, out_width
,
1696 out_height
, ilace
, color_mode
, rotation
);
1698 switch (color_mode
) {
1699 case OMAP_DSS_COLOR_NV12
:
1700 if (chroma_upscale
) {
1701 /* UV is subsampled by 2 horizontally and vertically */
1705 /* UV is downsampled by 2 horizontally and vertically */
1711 case OMAP_DSS_COLOR_YUV2
:
1712 case OMAP_DSS_COLOR_UYVY
:
1713 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1714 if (rotation
== OMAP_DSS_ROT_0
||
1715 rotation
== OMAP_DSS_ROT_180
) {
1717 /* UV is subsampled by 2 horizontally */
1720 /* UV is downsampled by 2 horizontally */
1724 /* must use FIR for YUV422 if rotated */
1725 if (rotation
!= OMAP_DSS_ROT_0
)
1726 scale_x
= scale_y
= true;
1734 if (out_width
!= orig_width
)
1736 if (out_height
!= orig_height
)
1739 dispc_ovl_set_scale_param(plane
, orig_width
, orig_height
,
1740 out_width
, out_height
, five_taps
,
1741 rotation
, DISPC_COLOR_COMPONENT_UV
);
1743 if (plane
!= OMAP_DSS_WB
)
1744 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane
),
1745 (scale_x
|| scale_y
) ? 1 : 0, 8, 8);
1748 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), scale_x
? 1 : 0, 5, 5);
1750 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), scale_y
? 1 : 0, 6, 6);
1753 static void dispc_ovl_set_scaling(enum omap_plane plane
,
1754 u16 orig_width
, u16 orig_height
,
1755 u16 out_width
, u16 out_height
,
1756 bool ilace
, bool five_taps
,
1757 bool fieldmode
, enum omap_color_mode color_mode
,
1760 BUG_ON(plane
== OMAP_DSS_GFX
);
1762 dispc_ovl_set_scaling_common(plane
,
1763 orig_width
, orig_height
,
1764 out_width
, out_height
,
1766 fieldmode
, color_mode
,
1769 dispc_ovl_set_scaling_uv(plane
,
1770 orig_width
, orig_height
,
1771 out_width
, out_height
,
1773 fieldmode
, color_mode
,
1777 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane
, u8 rotation
,
1778 enum omap_dss_rotation_type rotation_type
,
1779 bool mirroring
, enum omap_color_mode color_mode
)
1781 bool row_repeat
= false;
1784 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1785 color_mode
== OMAP_DSS_COLOR_UYVY
) {
1789 case OMAP_DSS_ROT_0
:
1792 case OMAP_DSS_ROT_90
:
1795 case OMAP_DSS_ROT_180
:
1798 case OMAP_DSS_ROT_270
:
1804 case OMAP_DSS_ROT_0
:
1807 case OMAP_DSS_ROT_90
:
1810 case OMAP_DSS_ROT_180
:
1813 case OMAP_DSS_ROT_270
:
1819 if (rotation
== OMAP_DSS_ROT_90
|| rotation
== OMAP_DSS_ROT_270
)
1826 * OMAP4/5 Errata i631:
1827 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1828 * rows beyond the framebuffer, which may cause OCP error.
1830 if (color_mode
== OMAP_DSS_COLOR_NV12
&&
1831 rotation_type
!= OMAP_DSS_ROT_TILER
)
1834 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), vidrot
, 13, 12);
1835 if (dss_has_feature(FEAT_ROWREPEATENABLE
))
1836 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
),
1837 row_repeat
? 1 : 0, 18, 18);
1839 if (color_mode
== OMAP_DSS_COLOR_NV12
) {
1840 bool doublestride
= (rotation_type
== OMAP_DSS_ROT_TILER
) &&
1841 (rotation
== OMAP_DSS_ROT_0
||
1842 rotation
== OMAP_DSS_ROT_180
);
1844 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), doublestride
, 22, 22);
1849 static int color_mode_to_bpp(enum omap_color_mode color_mode
)
1851 switch (color_mode
) {
1852 case OMAP_DSS_COLOR_CLUT1
:
1854 case OMAP_DSS_COLOR_CLUT2
:
1856 case OMAP_DSS_COLOR_CLUT4
:
1858 case OMAP_DSS_COLOR_CLUT8
:
1859 case OMAP_DSS_COLOR_NV12
:
1861 case OMAP_DSS_COLOR_RGB12U
:
1862 case OMAP_DSS_COLOR_RGB16
:
1863 case OMAP_DSS_COLOR_ARGB16
:
1864 case OMAP_DSS_COLOR_YUV2
:
1865 case OMAP_DSS_COLOR_UYVY
:
1866 case OMAP_DSS_COLOR_RGBA16
:
1867 case OMAP_DSS_COLOR_RGBX16
:
1868 case OMAP_DSS_COLOR_ARGB16_1555
:
1869 case OMAP_DSS_COLOR_XRGB16_1555
:
1871 case OMAP_DSS_COLOR_RGB24P
:
1873 case OMAP_DSS_COLOR_RGB24U
:
1874 case OMAP_DSS_COLOR_ARGB32
:
1875 case OMAP_DSS_COLOR_RGBA32
:
1876 case OMAP_DSS_COLOR_RGBX32
:
1884 static s32
pixinc(int pixels
, u8 ps
)
1888 else if (pixels
> 1)
1889 return 1 + (pixels
- 1) * ps
;
1890 else if (pixels
< 0)
1891 return 1 - (-pixels
+ 1) * ps
;
1897 static void calc_vrfb_rotation_offset(u8 rotation
, bool mirror
,
1899 u16 width
, u16 height
,
1900 enum omap_color_mode color_mode
, bool fieldmode
,
1901 unsigned int field_offset
,
1902 unsigned *offset0
, unsigned *offset1
,
1903 s32
*row_inc
, s32
*pix_inc
, int x_predecim
, int y_predecim
)
1907 /* FIXME CLUT formats */
1908 switch (color_mode
) {
1909 case OMAP_DSS_COLOR_CLUT1
:
1910 case OMAP_DSS_COLOR_CLUT2
:
1911 case OMAP_DSS_COLOR_CLUT4
:
1912 case OMAP_DSS_COLOR_CLUT8
:
1915 case OMAP_DSS_COLOR_YUV2
:
1916 case OMAP_DSS_COLOR_UYVY
:
1920 ps
= color_mode_to_bpp(color_mode
) / 8;
1924 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation
, screen_width
,
1928 * field 0 = even field = bottom field
1929 * field 1 = odd field = top field
1931 switch (rotation
+ mirror
* 4) {
1932 case OMAP_DSS_ROT_0
:
1933 case OMAP_DSS_ROT_180
:
1935 * If the pixel format is YUV or UYVY divide the width
1936 * of the image by 2 for 0 and 180 degree rotation.
1938 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1939 color_mode
== OMAP_DSS_COLOR_UYVY
)
1941 case OMAP_DSS_ROT_90
:
1942 case OMAP_DSS_ROT_270
:
1945 *offset0
= field_offset
* screen_width
* ps
;
1949 *row_inc
= pixinc(1 +
1950 (y_predecim
* screen_width
- x_predecim
* width
) +
1951 (fieldmode
? screen_width
: 0), ps
);
1952 *pix_inc
= pixinc(x_predecim
, ps
);
1955 case OMAP_DSS_ROT_0
+ 4:
1956 case OMAP_DSS_ROT_180
+ 4:
1957 /* If the pixel format is YUV or UYVY divide the width
1958 * of the image by 2 for 0 degree and 180 degree
1960 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1961 color_mode
== OMAP_DSS_COLOR_UYVY
)
1963 case OMAP_DSS_ROT_90
+ 4:
1964 case OMAP_DSS_ROT_270
+ 4:
1967 *offset0
= field_offset
* screen_width
* ps
;
1970 *row_inc
= pixinc(1 -
1971 (y_predecim
* screen_width
+ x_predecim
* width
) -
1972 (fieldmode
? screen_width
: 0), ps
);
1973 *pix_inc
= pixinc(x_predecim
, ps
);
1982 static void calc_dma_rotation_offset(u8 rotation
, bool mirror
,
1984 u16 width
, u16 height
,
1985 enum omap_color_mode color_mode
, bool fieldmode
,
1986 unsigned int field_offset
,
1987 unsigned *offset0
, unsigned *offset1
,
1988 s32
*row_inc
, s32
*pix_inc
, int x_predecim
, int y_predecim
)
1993 /* FIXME CLUT formats */
1994 switch (color_mode
) {
1995 case OMAP_DSS_COLOR_CLUT1
:
1996 case OMAP_DSS_COLOR_CLUT2
:
1997 case OMAP_DSS_COLOR_CLUT4
:
1998 case OMAP_DSS_COLOR_CLUT8
:
2002 ps
= color_mode_to_bpp(color_mode
) / 8;
2006 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation
, screen_width
,
2009 /* width & height are overlay sizes, convert to fb sizes */
2011 if (rotation
== OMAP_DSS_ROT_0
|| rotation
== OMAP_DSS_ROT_180
) {
2020 * field 0 = even field = bottom field
2021 * field 1 = odd field = top field
2023 switch (rotation
+ mirror
* 4) {
2024 case OMAP_DSS_ROT_0
:
2027 *offset0
= *offset1
+ field_offset
* screen_width
* ps
;
2029 *offset0
= *offset1
;
2030 *row_inc
= pixinc(1 +
2031 (y_predecim
* screen_width
- fbw
* x_predecim
) +
2032 (fieldmode
? screen_width
: 0), ps
);
2033 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2034 color_mode
== OMAP_DSS_COLOR_UYVY
)
2035 *pix_inc
= pixinc(x_predecim
, 2 * ps
);
2037 *pix_inc
= pixinc(x_predecim
, ps
);
2039 case OMAP_DSS_ROT_90
:
2040 *offset1
= screen_width
* (fbh
- 1) * ps
;
2042 *offset0
= *offset1
+ field_offset
* ps
;
2044 *offset0
= *offset1
;
2045 *row_inc
= pixinc(screen_width
* (fbh
* x_predecim
- 1) +
2046 y_predecim
+ (fieldmode
? 1 : 0), ps
);
2047 *pix_inc
= pixinc(-x_predecim
* screen_width
, ps
);
2049 case OMAP_DSS_ROT_180
:
2050 *offset1
= (screen_width
* (fbh
- 1) + fbw
- 1) * ps
;
2052 *offset0
= *offset1
- field_offset
* screen_width
* ps
;
2054 *offset0
= *offset1
;
2055 *row_inc
= pixinc(-1 -
2056 (y_predecim
* screen_width
- fbw
* x_predecim
) -
2057 (fieldmode
? screen_width
: 0), ps
);
2058 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2059 color_mode
== OMAP_DSS_COLOR_UYVY
)
2060 *pix_inc
= pixinc(-x_predecim
, 2 * ps
);
2062 *pix_inc
= pixinc(-x_predecim
, ps
);
2064 case OMAP_DSS_ROT_270
:
2065 *offset1
= (fbw
- 1) * ps
;
2067 *offset0
= *offset1
- field_offset
* ps
;
2069 *offset0
= *offset1
;
2070 *row_inc
= pixinc(-screen_width
* (fbh
* x_predecim
- 1) -
2071 y_predecim
- (fieldmode
? 1 : 0), ps
);
2072 *pix_inc
= pixinc(x_predecim
* screen_width
, ps
);
2076 case OMAP_DSS_ROT_0
+ 4:
2077 *offset1
= (fbw
- 1) * ps
;
2079 *offset0
= *offset1
+ field_offset
* screen_width
* ps
;
2081 *offset0
= *offset1
;
2082 *row_inc
= pixinc(y_predecim
* screen_width
* 2 - 1 +
2083 (fieldmode
? screen_width
: 0),
2085 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2086 color_mode
== OMAP_DSS_COLOR_UYVY
)
2087 *pix_inc
= pixinc(-x_predecim
, 2 * ps
);
2089 *pix_inc
= pixinc(-x_predecim
, ps
);
2092 case OMAP_DSS_ROT_90
+ 4:
2095 *offset0
= *offset1
+ field_offset
* ps
;
2097 *offset0
= *offset1
;
2098 *row_inc
= pixinc(-screen_width
* (fbh
* x_predecim
- 1) +
2099 y_predecim
+ (fieldmode
? 1 : 0),
2101 *pix_inc
= pixinc(x_predecim
* screen_width
, ps
);
2104 case OMAP_DSS_ROT_180
+ 4:
2105 *offset1
= screen_width
* (fbh
- 1) * ps
;
2107 *offset0
= *offset1
- field_offset
* screen_width
* ps
;
2109 *offset0
= *offset1
;
2110 *row_inc
= pixinc(1 - y_predecim
* screen_width
* 2 -
2111 (fieldmode
? screen_width
: 0),
2113 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2114 color_mode
== OMAP_DSS_COLOR_UYVY
)
2115 *pix_inc
= pixinc(x_predecim
, 2 * ps
);
2117 *pix_inc
= pixinc(x_predecim
, ps
);
2120 case OMAP_DSS_ROT_270
+ 4:
2121 *offset1
= (screen_width
* (fbh
- 1) + fbw
- 1) * ps
;
2123 *offset0
= *offset1
- field_offset
* ps
;
2125 *offset0
= *offset1
;
2126 *row_inc
= pixinc(screen_width
* (fbh
* x_predecim
- 1) -
2127 y_predecim
- (fieldmode
? 1 : 0),
2129 *pix_inc
= pixinc(-x_predecim
* screen_width
, ps
);
2138 static void calc_tiler_rotation_offset(u16 screen_width
, u16 width
,
2139 enum omap_color_mode color_mode
, bool fieldmode
,
2140 unsigned int field_offset
, unsigned *offset0
, unsigned *offset1
,
2141 s32
*row_inc
, s32
*pix_inc
, int x_predecim
, int y_predecim
)
2145 switch (color_mode
) {
2146 case OMAP_DSS_COLOR_CLUT1
:
2147 case OMAP_DSS_COLOR_CLUT2
:
2148 case OMAP_DSS_COLOR_CLUT4
:
2149 case OMAP_DSS_COLOR_CLUT8
:
2153 ps
= color_mode_to_bpp(color_mode
) / 8;
2157 DSSDBG("scrw %d, width %d\n", screen_width
, width
);
2160 * field 0 = even field = bottom field
2161 * field 1 = odd field = top field
2165 *offset0
= *offset1
+ field_offset
* screen_width
* ps
;
2167 *offset0
= *offset1
;
2168 *row_inc
= pixinc(1 + (y_predecim
* screen_width
- width
* x_predecim
) +
2169 (fieldmode
? screen_width
: 0), ps
);
2170 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2171 color_mode
== OMAP_DSS_COLOR_UYVY
)
2172 *pix_inc
= pixinc(x_predecim
, 2 * ps
);
2174 *pix_inc
= pixinc(x_predecim
, ps
);
2178 * This function is used to avoid synclosts in OMAP3, because of some
2179 * undocumented horizontal position and timing related limitations.
2181 static int check_horiz_timing_omap3(unsigned long pclk
, unsigned long lclk
,
2182 const struct videomode
*t
, u16 pos_x
,
2183 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2186 const int ds
= DIV_ROUND_UP(height
, out_height
);
2187 unsigned long nonactive
;
2188 static const u8 limits
[3] = { 8, 10, 20 };
2192 nonactive
= t
->hactive
+ t
->hfront_porch
+ t
->hsync_len
+
2193 t
->hback_porch
- out_width
;
2196 if (out_height
< height
)
2198 if (out_width
< width
)
2200 blank
= div_u64((u64
)(t
->hback_porch
+ t
->hsync_len
+ t
->hfront_porch
) *
2202 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank
, limits
[i
]);
2203 if (blank
<= limits
[i
])
2206 /* FIXME add checks for 3-tap filter once the limitations are known */
2211 * Pixel data should be prepared before visible display point starts.
2212 * So, atleast DS-2 lines must have already been fetched by DISPC
2213 * during nonactive - pos_x period.
2215 val
= div_u64((u64
)(nonactive
- pos_x
) * lclk
, pclk
);
2216 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2217 val
, max(0, ds
- 2) * width
);
2218 if (val
< max(0, ds
- 2) * width
)
2222 * All lines need to be refilled during the nonactive period of which
2223 * only one line can be loaded during the active period. So, atleast
2224 * DS - 1 lines should be loaded during nonactive period.
2226 val
= div_u64((u64
)nonactive
* lclk
, pclk
);
2227 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2228 val
, max(0, ds
- 1) * width
);
2229 if (val
< max(0, ds
- 1) * width
)
2235 static unsigned long calc_core_clk_five_taps(unsigned long pclk
,
2236 const struct videomode
*mgr_timings
, u16 width
,
2237 u16 height
, u16 out_width
, u16 out_height
,
2238 enum omap_color_mode color_mode
)
2243 if (height
<= out_height
&& width
<= out_width
)
2244 return (unsigned long) pclk
;
2246 if (height
> out_height
) {
2247 unsigned int ppl
= mgr_timings
->hactive
;
2249 tmp
= (u64
)pclk
* height
* out_width
;
2250 do_div(tmp
, 2 * out_height
* ppl
);
2253 if (height
> 2 * out_height
) {
2254 if (ppl
== out_width
)
2257 tmp
= (u64
)pclk
* (height
- 2 * out_height
) * out_width
;
2258 do_div(tmp
, 2 * out_height
* (ppl
- out_width
));
2259 core_clk
= max_t(u32
, core_clk
, tmp
);
2263 if (width
> out_width
) {
2264 tmp
= (u64
)pclk
* width
;
2265 do_div(tmp
, out_width
);
2266 core_clk
= max_t(u32
, core_clk
, tmp
);
2268 if (color_mode
== OMAP_DSS_COLOR_RGB24U
)
2275 static unsigned long calc_core_clk_24xx(unsigned long pclk
, u16 width
,
2276 u16 height
, u16 out_width
, u16 out_height
, bool mem_to_mem
)
2278 if (height
> out_height
&& width
> out_width
)
2284 static unsigned long calc_core_clk_34xx(unsigned long pclk
, u16 width
,
2285 u16 height
, u16 out_width
, u16 out_height
, bool mem_to_mem
)
2287 unsigned int hf
, vf
;
2290 * FIXME how to determine the 'A' factor
2291 * for the no downscaling case ?
2294 if (width
> 3 * out_width
)
2296 else if (width
> 2 * out_width
)
2298 else if (width
> out_width
)
2302 if (height
> out_height
)
2307 return pclk
* vf
* hf
;
2310 static unsigned long calc_core_clk_44xx(unsigned long pclk
, u16 width
,
2311 u16 height
, u16 out_width
, u16 out_height
, bool mem_to_mem
)
2314 * If the overlay/writeback is in mem to mem mode, there are no
2315 * downscaling limitations with respect to pixel clock, return 1 as
2316 * required core clock to represent that we have sufficient enough
2317 * core clock to do maximum downscaling
2322 if (width
> out_width
)
2323 return DIV_ROUND_UP(pclk
, out_width
) * width
;
2328 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk
, unsigned long lclk
,
2329 const struct videomode
*mgr_timings
,
2330 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2331 enum omap_color_mode color_mode
, bool *five_taps
,
2332 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
2333 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
)
2336 u16 in_width
, in_height
;
2337 int min_factor
= min(*decim_x
, *decim_y
);
2338 const int maxsinglelinewidth
=
2339 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH
);
2344 in_height
= height
/ *decim_y
;
2345 in_width
= width
/ *decim_x
;
2346 *core_clk
= dispc
.feat
->calc_core_clk(pclk
, in_width
,
2347 in_height
, out_width
, out_height
, mem_to_mem
);
2348 error
= (in_width
> maxsinglelinewidth
|| !*core_clk
||
2349 *core_clk
> dispc_core_clk_rate());
2351 if (*decim_x
== *decim_y
) {
2352 *decim_x
= min_factor
;
2355 swap(*decim_x
, *decim_y
);
2356 if (*decim_x
< *decim_y
)
2360 } while (*decim_x
<= *x_predecim
&& *decim_y
<= *y_predecim
&& error
);
2363 DSSERR("failed to find scaling settings\n");
2367 if (in_width
> maxsinglelinewidth
) {
2368 DSSERR("Cannot scale max input width exceeded");
2374 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk
, unsigned long lclk
,
2375 const struct videomode
*mgr_timings
,
2376 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2377 enum omap_color_mode color_mode
, bool *five_taps
,
2378 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
2379 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
)
2382 u16 in_width
, in_height
;
2383 const int maxsinglelinewidth
=
2384 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH
);
2387 in_height
= height
/ *decim_y
;
2388 in_width
= width
/ *decim_x
;
2389 *five_taps
= in_height
> out_height
;
2391 if (in_width
> maxsinglelinewidth
)
2392 if (in_height
> out_height
&&
2393 in_height
< out_height
* 2)
2397 *core_clk
= calc_core_clk_five_taps(pclk
, mgr_timings
,
2398 in_width
, in_height
, out_width
,
2399 out_height
, color_mode
);
2401 *core_clk
= dispc
.feat
->calc_core_clk(pclk
, in_width
,
2402 in_height
, out_width
, out_height
,
2405 error
= check_horiz_timing_omap3(pclk
, lclk
, mgr_timings
,
2406 pos_x
, in_width
, in_height
, out_width
,
2407 out_height
, *five_taps
);
2408 if (error
&& *five_taps
) {
2413 error
= (error
|| in_width
> maxsinglelinewidth
* 2 ||
2414 (in_width
> maxsinglelinewidth
&& *five_taps
) ||
2415 !*core_clk
|| *core_clk
> dispc_core_clk_rate());
2418 /* verify that we're inside the limits of scaler */
2419 if (in_width
/ 4 > out_width
)
2423 if (in_height
/ 4 > out_height
)
2426 if (in_height
/ 2 > out_height
)
2433 } while (*decim_x
<= *x_predecim
&& *decim_y
<= *y_predecim
&& error
);
2436 DSSERR("failed to find scaling settings\n");
2440 if (check_horiz_timing_omap3(pclk
, lclk
, mgr_timings
, pos_x
, in_width
,
2441 in_height
, out_width
, out_height
, *five_taps
)) {
2442 DSSERR("horizontal timing too tight\n");
2446 if (in_width
> (maxsinglelinewidth
* 2)) {
2447 DSSERR("Cannot setup scaling");
2448 DSSERR("width exceeds maximum width possible");
2452 if (in_width
> maxsinglelinewidth
&& *five_taps
) {
2453 DSSERR("cannot setup scaling with five taps");
2459 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk
, unsigned long lclk
,
2460 const struct videomode
*mgr_timings
,
2461 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2462 enum omap_color_mode color_mode
, bool *five_taps
,
2463 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
2464 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
)
2466 u16 in_width
, in_width_max
;
2467 int decim_x_min
= *decim_x
;
2468 u16 in_height
= height
/ *decim_y
;
2469 const int maxsinglelinewidth
=
2470 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH
);
2471 const int maxdownscale
= dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE
);
2474 in_width_max
= out_width
* maxdownscale
;
2476 in_width_max
= dispc_core_clk_rate() /
2477 DIV_ROUND_UP(pclk
, out_width
);
2480 *decim_x
= DIV_ROUND_UP(width
, in_width_max
);
2482 *decim_x
= *decim_x
> decim_x_min
? *decim_x
: decim_x_min
;
2483 if (*decim_x
> *x_predecim
)
2487 in_width
= width
/ *decim_x
;
2488 } while (*decim_x
<= *x_predecim
&&
2489 in_width
> maxsinglelinewidth
&& ++*decim_x
);
2491 if (in_width
> maxsinglelinewidth
) {
2492 DSSERR("Cannot scale width exceeds max line width");
2496 *core_clk
= dispc
.feat
->calc_core_clk(pclk
, in_width
, in_height
,
2497 out_width
, out_height
, mem_to_mem
);
2501 #define DIV_FRAC(dividend, divisor) \
2502 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2504 static int dispc_ovl_calc_scaling(unsigned long pclk
, unsigned long lclk
,
2505 enum omap_overlay_caps caps
,
2506 const struct videomode
*mgr_timings
,
2507 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2508 enum omap_color_mode color_mode
, bool *five_taps
,
2509 int *x_predecim
, int *y_predecim
, u16 pos_x
,
2510 enum omap_dss_rotation_type rotation_type
, bool mem_to_mem
)
2512 const int maxdownscale
= dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE
);
2513 const int max_decim_limit
= 16;
2514 unsigned long core_clk
= 0;
2515 int decim_x
, decim_y
, ret
;
2517 if (width
== out_width
&& height
== out_height
)
2520 if (!mem_to_mem
&& (pclk
== 0 || mgr_timings
->pixelclock
== 0)) {
2521 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2525 if ((caps
& OMAP_DSS_OVL_CAP_SCALE
) == 0)
2529 *x_predecim
= *y_predecim
= 1;
2531 *x_predecim
= max_decim_limit
;
2532 *y_predecim
= (rotation_type
== OMAP_DSS_ROT_TILER
&&
2533 dss_has_feature(FEAT_BURST_2D
)) ?
2534 2 : max_decim_limit
;
2537 if (color_mode
== OMAP_DSS_COLOR_CLUT1
||
2538 color_mode
== OMAP_DSS_COLOR_CLUT2
||
2539 color_mode
== OMAP_DSS_COLOR_CLUT4
||
2540 color_mode
== OMAP_DSS_COLOR_CLUT8
) {
2547 decim_x
= DIV_ROUND_UP(DIV_ROUND_UP(width
, out_width
), maxdownscale
);
2548 decim_y
= DIV_ROUND_UP(DIV_ROUND_UP(height
, out_height
), maxdownscale
);
2550 if (decim_x
> *x_predecim
|| out_width
> width
* 8)
2553 if (decim_y
> *y_predecim
|| out_height
> height
* 8)
2556 ret
= dispc
.feat
->calc_scaling(pclk
, lclk
, mgr_timings
, width
, height
,
2557 out_width
, out_height
, color_mode
, five_taps
,
2558 x_predecim
, y_predecim
, &decim_x
, &decim_y
, pos_x
, &core_clk
,
2563 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2565 out_width
, out_height
,
2566 out_width
/ width
, DIV_FRAC(out_width
, width
),
2567 out_height
/ height
, DIV_FRAC(out_height
, height
),
2570 width
/ decim_x
, height
/ decim_y
,
2571 out_width
/ (width
/ decim_x
), DIV_FRAC(out_width
, width
/ decim_x
),
2572 out_height
/ (height
/ decim_y
), DIV_FRAC(out_height
, height
/ decim_y
),
2575 core_clk
, dispc_core_clk_rate());
2577 if (!core_clk
|| core_clk
> dispc_core_clk_rate()) {
2578 DSSERR("failed to set up scaling, "
2579 "required core clk rate = %lu Hz, "
2580 "current core clk rate = %lu Hz\n",
2581 core_clk
, dispc_core_clk_rate());
2585 *x_predecim
= decim_x
;
2586 *y_predecim
= decim_y
;
2590 static int dispc_ovl_setup_common(enum omap_plane plane
,
2591 enum omap_overlay_caps caps
, u32 paddr
, u32 p_uv_addr
,
2592 u16 screen_width
, int pos_x
, int pos_y
, u16 width
, u16 height
,
2593 u16 out_width
, u16 out_height
, enum omap_color_mode color_mode
,
2594 u8 rotation
, bool mirror
, u8 zorder
, u8 pre_mult_alpha
,
2595 u8 global_alpha
, enum omap_dss_rotation_type rotation_type
,
2596 bool replication
, const struct videomode
*mgr_timings
,
2599 bool five_taps
= true;
2600 bool fieldmode
= false;
2602 unsigned offset0
, offset1
;
2605 u16 frame_width
, frame_height
;
2606 unsigned int field_offset
= 0;
2607 u16 in_height
= height
;
2608 u16 in_width
= width
;
2609 int x_predecim
= 1, y_predecim
= 1;
2610 bool ilace
= !!(mgr_timings
->flags
& DISPLAY_FLAGS_INTERLACED
);
2611 unsigned long pclk
= dispc_plane_pclk_rate(plane
);
2612 unsigned long lclk
= dispc_plane_lclk_rate(plane
);
2614 if (paddr
== 0 && rotation_type
!= OMAP_DSS_ROT_TILER
)
2617 switch (color_mode
) {
2618 case OMAP_DSS_COLOR_YUV2
:
2619 case OMAP_DSS_COLOR_UYVY
:
2620 case OMAP_DSS_COLOR_NV12
:
2622 DSSERR("input width %d is not even for YUV format\n",
2632 out_width
= out_width
== 0 ? width
: out_width
;
2633 out_height
= out_height
== 0 ? height
: out_height
;
2635 if (ilace
&& height
== out_height
)
2644 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2645 "out_height %d\n", in_height
, pos_y
,
2649 if (!dss_feat_color_mode_supported(plane
, color_mode
))
2652 r
= dispc_ovl_calc_scaling(pclk
, lclk
, caps
, mgr_timings
, in_width
,
2653 in_height
, out_width
, out_height
, color_mode
,
2654 &five_taps
, &x_predecim
, &y_predecim
, pos_x
,
2655 rotation_type
, mem_to_mem
);
2659 in_width
= in_width
/ x_predecim
;
2660 in_height
= in_height
/ y_predecim
;
2662 if (x_predecim
> 1 || y_predecim
> 1)
2663 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2664 x_predecim
, y_predecim
, in_width
, in_height
);
2666 switch (color_mode
) {
2667 case OMAP_DSS_COLOR_YUV2
:
2668 case OMAP_DSS_COLOR_UYVY
:
2669 case OMAP_DSS_COLOR_NV12
:
2671 DSSDBG("predecimated input width is not even for YUV format\n");
2672 DSSDBG("adjusting input width %d -> %d\n",
2673 in_width
, in_width
& ~1);
2683 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2684 color_mode
== OMAP_DSS_COLOR_UYVY
||
2685 color_mode
== OMAP_DSS_COLOR_NV12
)
2688 if (ilace
&& !fieldmode
) {
2690 * when downscaling the bottom field may have to start several
2691 * source lines below the top field. Unfortunately ACCUI
2692 * registers will only hold the fractional part of the offset
2693 * so the integer part must be added to the base address of the
2696 if (!in_height
|| in_height
== out_height
)
2699 field_offset
= in_height
/ out_height
/ 2;
2702 /* Fields are independent but interleaved in memory. */
2711 if (plane
== OMAP_DSS_WB
) {
2712 frame_width
= out_width
;
2713 frame_height
= out_height
;
2715 frame_width
= in_width
;
2716 frame_height
= height
;
2719 if (rotation_type
== OMAP_DSS_ROT_TILER
)
2720 calc_tiler_rotation_offset(screen_width
, frame_width
,
2721 color_mode
, fieldmode
, field_offset
,
2722 &offset0
, &offset1
, &row_inc
, &pix_inc
,
2723 x_predecim
, y_predecim
);
2724 else if (rotation_type
== OMAP_DSS_ROT_DMA
)
2725 calc_dma_rotation_offset(rotation
, mirror
, screen_width
,
2726 frame_width
, frame_height
,
2727 color_mode
, fieldmode
, field_offset
,
2728 &offset0
, &offset1
, &row_inc
, &pix_inc
,
2729 x_predecim
, y_predecim
);
2731 calc_vrfb_rotation_offset(rotation
, mirror
,
2732 screen_width
, frame_width
, frame_height
,
2733 color_mode
, fieldmode
, field_offset
,
2734 &offset0
, &offset1
, &row_inc
, &pix_inc
,
2735 x_predecim
, y_predecim
);
2737 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2738 offset0
, offset1
, row_inc
, pix_inc
);
2740 dispc_ovl_set_color_mode(plane
, color_mode
);
2742 dispc_ovl_configure_burst_type(plane
, rotation_type
);
2744 if (dispc
.feat
->reverse_ilace_field_order
)
2745 swap(offset0
, offset1
);
2747 dispc_ovl_set_ba0(plane
, paddr
+ offset0
);
2748 dispc_ovl_set_ba1(plane
, paddr
+ offset1
);
2750 if (OMAP_DSS_COLOR_NV12
== color_mode
) {
2751 dispc_ovl_set_ba0_uv(plane
, p_uv_addr
+ offset0
);
2752 dispc_ovl_set_ba1_uv(plane
, p_uv_addr
+ offset1
);
2755 if (dispc
.feat
->last_pixel_inc_missing
)
2756 row_inc
+= pix_inc
- 1;
2758 dispc_ovl_set_row_inc(plane
, row_inc
);
2759 dispc_ovl_set_pix_inc(plane
, pix_inc
);
2761 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x
, pos_y
, in_width
,
2762 in_height
, out_width
, out_height
);
2764 dispc_ovl_set_pos(plane
, caps
, pos_x
, pos_y
);
2766 dispc_ovl_set_input_size(plane
, in_width
, in_height
);
2768 if (caps
& OMAP_DSS_OVL_CAP_SCALE
) {
2769 dispc_ovl_set_scaling(plane
, in_width
, in_height
, out_width
,
2770 out_height
, ilace
, five_taps
, fieldmode
,
2771 color_mode
, rotation
);
2772 dispc_ovl_set_output_size(plane
, out_width
, out_height
);
2773 dispc_ovl_set_vid_color_conv(plane
, cconv
);
2776 dispc_ovl_set_rotation_attrs(plane
, rotation
, rotation_type
, mirror
,
2779 dispc_ovl_set_zorder(plane
, caps
, zorder
);
2780 dispc_ovl_set_pre_mult_alpha(plane
, caps
, pre_mult_alpha
);
2781 dispc_ovl_setup_global_alpha(plane
, caps
, global_alpha
);
2783 dispc_ovl_enable_replication(plane
, caps
, replication
);
2788 int dispc_ovl_setup(enum omap_plane plane
, const struct omap_overlay_info
*oi
,
2789 bool replication
, const struct videomode
*mgr_timings
,
2793 enum omap_overlay_caps caps
= dss_feat_get_overlay_caps(plane
);
2794 enum omap_channel channel
;
2796 channel
= dispc_ovl_get_channel_out(plane
);
2798 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2799 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2800 plane
, &oi
->paddr
, &oi
->p_uv_addr
, oi
->screen_width
, oi
->pos_x
,
2801 oi
->pos_y
, oi
->width
, oi
->height
, oi
->out_width
, oi
->out_height
,
2802 oi
->color_mode
, oi
->rotation
, oi
->mirror
, channel
, replication
);
2804 r
= dispc_ovl_setup_common(plane
, caps
, oi
->paddr
, oi
->p_uv_addr
,
2805 oi
->screen_width
, oi
->pos_x
, oi
->pos_y
, oi
->width
, oi
->height
,
2806 oi
->out_width
, oi
->out_height
, oi
->color_mode
, oi
->rotation
,
2807 oi
->mirror
, oi
->zorder
, oi
->pre_mult_alpha
, oi
->global_alpha
,
2808 oi
->rotation_type
, replication
, mgr_timings
, mem_to_mem
);
2812 EXPORT_SYMBOL(dispc_ovl_setup
);
2814 int dispc_wb_setup(const struct omap_dss_writeback_info
*wi
,
2815 bool mem_to_mem
, const struct videomode
*mgr_timings
)
2819 enum omap_plane plane
= OMAP_DSS_WB
;
2820 const int pos_x
= 0, pos_y
= 0;
2821 const u8 zorder
= 0, global_alpha
= 0;
2822 const bool replication
= false;
2824 int in_width
= mgr_timings
->hactive
;
2825 int in_height
= mgr_timings
->vactive
;
2826 enum omap_overlay_caps caps
=
2827 OMAP_DSS_OVL_CAP_SCALE
| OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
;
2829 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2830 "rot %d, mir %d\n", wi
->paddr
, wi
->p_uv_addr
, in_width
,
2831 in_height
, wi
->width
, wi
->height
, wi
->color_mode
, wi
->rotation
,
2834 r
= dispc_ovl_setup_common(plane
, caps
, wi
->paddr
, wi
->p_uv_addr
,
2835 wi
->buf_width
, pos_x
, pos_y
, in_width
, in_height
, wi
->width
,
2836 wi
->height
, wi
->color_mode
, wi
->rotation
, wi
->mirror
, zorder
,
2837 wi
->pre_mult_alpha
, global_alpha
, wi
->rotation_type
,
2838 replication
, mgr_timings
, mem_to_mem
);
2840 switch (wi
->color_mode
) {
2841 case OMAP_DSS_COLOR_RGB16
:
2842 case OMAP_DSS_COLOR_RGB24P
:
2843 case OMAP_DSS_COLOR_ARGB16
:
2844 case OMAP_DSS_COLOR_RGBA16
:
2845 case OMAP_DSS_COLOR_RGB12U
:
2846 case OMAP_DSS_COLOR_ARGB16_1555
:
2847 case OMAP_DSS_COLOR_XRGB16_1555
:
2848 case OMAP_DSS_COLOR_RGBX16
:
2856 /* setup extra DISPC_WB_ATTRIBUTES */
2857 l
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
2858 l
= FLD_MOD(l
, truncation
, 10, 10); /* TRUNCATIONENABLE */
2859 l
= FLD_MOD(l
, mem_to_mem
, 19, 19); /* WRITEBACKMODE */
2861 l
= FLD_MOD(l
, 1, 26, 24); /* CAPTUREMODE */
2863 l
= FLD_MOD(l
, 0, 26, 24); /* CAPTUREMODE */
2864 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), l
);
2868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane
), 0, 7, 0);
2872 wbdelay
= min(mgr_timings
->vfront_porch
+
2873 mgr_timings
->vsync_len
+ mgr_timings
->vback_porch
,
2877 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane
), wbdelay
, 7, 0);
2883 int dispc_ovl_enable(enum omap_plane plane
, bool enable
)
2885 DSSDBG("dispc_enable_plane %d, %d\n", plane
, enable
);
2887 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
? 1 : 0, 0, 0);
2891 EXPORT_SYMBOL(dispc_ovl_enable
);
2893 bool dispc_ovl_enabled(enum omap_plane plane
)
2895 return REG_GET(DISPC_OVL_ATTRIBUTES(plane
), 0, 0);
2897 EXPORT_SYMBOL(dispc_ovl_enabled
);
2899 enum omap_dss_output_id
dispc_mgr_get_supported_outputs(enum omap_channel channel
)
2901 return dss_feat_get_supported_outputs(channel
);
2903 EXPORT_SYMBOL(dispc_mgr_get_supported_outputs
);
2905 void dispc_mgr_enable(enum omap_channel channel
, bool enable
)
2907 mgr_fld_write(channel
, DISPC_MGR_FLD_ENABLE
, enable
);
2908 /* flush posted write */
2909 mgr_fld_read(channel
, DISPC_MGR_FLD_ENABLE
);
2911 EXPORT_SYMBOL(dispc_mgr_enable
);
2913 bool dispc_mgr_is_enabled(enum omap_channel channel
)
2915 return !!mgr_fld_read(channel
, DISPC_MGR_FLD_ENABLE
);
2917 EXPORT_SYMBOL(dispc_mgr_is_enabled
);
2919 void dispc_wb_enable(bool enable
)
2921 dispc_ovl_enable(OMAP_DSS_WB
, enable
);
2924 bool dispc_wb_is_enabled(void)
2926 return dispc_ovl_enabled(OMAP_DSS_WB
);
2929 static void dispc_lcd_enable_signal_polarity(bool act_high
)
2931 if (!dss_has_feature(FEAT_LCDENABLEPOL
))
2934 REG_FLD_MOD(DISPC_CONTROL
, act_high
? 1 : 0, 29, 29);
2937 void dispc_lcd_enable_signal(bool enable
)
2939 if (!dss_has_feature(FEAT_LCDENABLESIGNAL
))
2942 REG_FLD_MOD(DISPC_CONTROL
, enable
? 1 : 0, 28, 28);
2945 void dispc_pck_free_enable(bool enable
)
2947 if (!dss_has_feature(FEAT_PCKFREEENABLE
))
2950 REG_FLD_MOD(DISPC_CONTROL
, enable
? 1 : 0, 27, 27);
2953 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel
, bool enable
)
2955 mgr_fld_write(channel
, DISPC_MGR_FLD_FIFOHANDCHECK
, enable
);
2959 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel
)
2961 mgr_fld_write(channel
, DISPC_MGR_FLD_STNTFT
, 1);
2964 static void dispc_set_loadmode(enum omap_dss_load_mode mode
)
2966 REG_FLD_MOD(DISPC_CONFIG
, mode
, 2, 1);
2970 static void dispc_mgr_set_default_color(enum omap_channel channel
, u32 color
)
2972 dispc_write_reg(DISPC_DEFAULT_COLOR(channel
), color
);
2975 static void dispc_mgr_set_trans_key(enum omap_channel ch
,
2976 enum omap_dss_trans_key_type type
,
2979 mgr_fld_write(ch
, DISPC_MGR_FLD_TCKSELECTION
, type
);
2981 dispc_write_reg(DISPC_TRANS_COLOR(ch
), trans_key
);
2984 static void dispc_mgr_enable_trans_key(enum omap_channel ch
, bool enable
)
2986 mgr_fld_write(ch
, DISPC_MGR_FLD_TCKENABLE
, enable
);
2989 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch
,
2992 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
))
2995 if (ch
== OMAP_DSS_CHANNEL_LCD
)
2996 REG_FLD_MOD(DISPC_CONFIG
, enable
, 18, 18);
2997 else if (ch
== OMAP_DSS_CHANNEL_DIGIT
)
2998 REG_FLD_MOD(DISPC_CONFIG
, enable
, 19, 19);
3001 void dispc_mgr_setup(enum omap_channel channel
,
3002 const struct omap_overlay_manager_info
*info
)
3004 dispc_mgr_set_default_color(channel
, info
->default_color
);
3005 dispc_mgr_set_trans_key(channel
, info
->trans_key_type
, info
->trans_key
);
3006 dispc_mgr_enable_trans_key(channel
, info
->trans_enabled
);
3007 dispc_mgr_enable_alpha_fixed_zorder(channel
,
3008 info
->partial_alpha_enabled
);
3009 if (dss_has_feature(FEAT_CPR
)) {
3010 dispc_mgr_enable_cpr(channel
, info
->cpr_enable
);
3011 dispc_mgr_set_cpr_coef(channel
, &info
->cpr_coefs
);
3014 EXPORT_SYMBOL(dispc_mgr_setup
);
3016 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel
, u8 data_lines
)
3020 switch (data_lines
) {
3038 mgr_fld_write(channel
, DISPC_MGR_FLD_TFTDATALINES
, code
);
3041 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode
)
3047 case DSS_IO_PAD_MODE_RESET
:
3051 case DSS_IO_PAD_MODE_RFBI
:
3055 case DSS_IO_PAD_MODE_BYPASS
:
3064 l
= dispc_read_reg(DISPC_CONTROL
);
3065 l
= FLD_MOD(l
, gpout0
, 15, 15);
3066 l
= FLD_MOD(l
, gpout1
, 16, 16);
3067 dispc_write_reg(DISPC_CONTROL
, l
);
3070 static void dispc_mgr_enable_stallmode(enum omap_channel channel
, bool enable
)
3072 mgr_fld_write(channel
, DISPC_MGR_FLD_STALLMODE
, enable
);
3075 void dispc_mgr_set_lcd_config(enum omap_channel channel
,
3076 const struct dss_lcd_mgr_config
*config
)
3078 dispc_mgr_set_io_pad_mode(config
->io_pad_mode
);
3080 dispc_mgr_enable_stallmode(channel
, config
->stallmode
);
3081 dispc_mgr_enable_fifohandcheck(channel
, config
->fifohandcheck
);
3083 dispc_mgr_set_clock_div(channel
, &config
->clock_info
);
3085 dispc_mgr_set_tft_data_lines(channel
, config
->video_port_width
);
3087 dispc_lcd_enable_signal_polarity(config
->lcden_sig_polarity
);
3089 dispc_mgr_set_lcd_type_tft(channel
);
3091 EXPORT_SYMBOL(dispc_mgr_set_lcd_config
);
3093 static bool _dispc_mgr_size_ok(u16 width
, u16 height
)
3095 return width
<= dispc
.feat
->mgr_width_max
&&
3096 height
<= dispc
.feat
->mgr_height_max
;
3099 static bool _dispc_lcd_timings_ok(int hsync_len
, int hfp
, int hbp
,
3100 int vsw
, int vfp
, int vbp
)
3102 if (hsync_len
< 1 || hsync_len
> dispc
.feat
->sw_max
||
3103 hfp
< 1 || hfp
> dispc
.feat
->hp_max
||
3104 hbp
< 1 || hbp
> dispc
.feat
->hp_max
||
3105 vsw
< 1 || vsw
> dispc
.feat
->sw_max
||
3106 vfp
< 0 || vfp
> dispc
.feat
->vp_max
||
3107 vbp
< 0 || vbp
> dispc
.feat
->vp_max
)
3112 static bool _dispc_mgr_pclk_ok(enum omap_channel channel
,
3115 if (dss_mgr_is_lcd(channel
))
3116 return pclk
<= dispc
.feat
->max_lcd_pclk
;
3118 return pclk
<= dispc
.feat
->max_tv_pclk
;
3121 bool dispc_mgr_timings_ok(enum omap_channel channel
,
3122 const struct videomode
*timings
)
3124 if (!_dispc_mgr_size_ok(timings
->hactive
, timings
->vactive
))
3127 if (!_dispc_mgr_pclk_ok(channel
, timings
->pixelclock
))
3130 if (dss_mgr_is_lcd(channel
)) {
3131 /* TODO: OMAP4+ supports interlace for LCD outputs */
3132 if (timings
->flags
& DISPLAY_FLAGS_INTERLACED
)
3135 if (!_dispc_lcd_timings_ok(timings
->hsync_len
,
3136 timings
->hfront_porch
, timings
->hback_porch
,
3137 timings
->vsync_len
, timings
->vfront_porch
,
3138 timings
->vback_porch
))
3145 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel
,
3146 const struct videomode
*ovt
)
3148 u32 timing_h
, timing_v
, l
;
3149 bool onoff
, rf
, ipc
, vs
, hs
, de
;
3151 timing_h
= FLD_VAL(ovt
->hsync_len
- 1, dispc
.feat
->sw_start
, 0) |
3152 FLD_VAL(ovt
->hfront_porch
- 1, dispc
.feat
->fp_start
, 8) |
3153 FLD_VAL(ovt
->hback_porch
- 1, dispc
.feat
->bp_start
, 20);
3154 timing_v
= FLD_VAL(ovt
->vsync_len
- 1, dispc
.feat
->sw_start
, 0) |
3155 FLD_VAL(ovt
->vfront_porch
, dispc
.feat
->fp_start
, 8) |
3156 FLD_VAL(ovt
->vback_porch
, dispc
.feat
->bp_start
, 20);
3158 dispc_write_reg(DISPC_TIMING_H(channel
), timing_h
);
3159 dispc_write_reg(DISPC_TIMING_V(channel
), timing_v
);
3161 if (ovt
->flags
& DISPLAY_FLAGS_VSYNC_HIGH
)
3166 if (ovt
->flags
& DISPLAY_FLAGS_HSYNC_HIGH
)
3171 if (ovt
->flags
& DISPLAY_FLAGS_DE_HIGH
)
3176 if (ovt
->flags
& DISPLAY_FLAGS_PIXDATA_POSEDGE
)
3181 /* always use the 'rf' setting */
3184 if (ovt
->flags
& DISPLAY_FLAGS_SYNC_POSEDGE
)
3189 l
= FLD_VAL(onoff
, 17, 17) |
3190 FLD_VAL(rf
, 16, 16) |
3191 FLD_VAL(de
, 15, 15) |
3192 FLD_VAL(ipc
, 14, 14) |
3193 FLD_VAL(hs
, 13, 13) |
3194 FLD_VAL(vs
, 12, 12);
3196 /* always set ALIGN bit when available */
3197 if (dispc
.feat
->supports_sync_align
)
3200 dispc_write_reg(DISPC_POL_FREQ(channel
), l
);
3202 if (dispc
.syscon_pol
) {
3203 const int shifts
[] = {
3204 [OMAP_DSS_CHANNEL_LCD
] = 0,
3205 [OMAP_DSS_CHANNEL_LCD2
] = 1,
3206 [OMAP_DSS_CHANNEL_LCD3
] = 2,
3211 mask
= (1 << 0) | (1 << 3) | (1 << 6);
3212 val
= (rf
<< 0) | (ipc
<< 3) | (onoff
<< 6);
3214 mask
<<= 16 + shifts
[channel
];
3215 val
<<= 16 + shifts
[channel
];
3217 regmap_update_bits(dispc
.syscon_pol
, dispc
.syscon_pol_offset
,
3222 /* change name to mode? */
3223 void dispc_mgr_set_timings(enum omap_channel channel
,
3224 const struct videomode
*timings
)
3226 unsigned xtot
, ytot
;
3227 unsigned long ht
, vt
;
3228 struct videomode t
= *timings
;
3230 DSSDBG("channel %d xres %u yres %u\n", channel
, t
.hactive
, t
.vactive
);
3232 if (!dispc_mgr_timings_ok(channel
, &t
)) {
3237 if (dss_mgr_is_lcd(channel
)) {
3238 _dispc_mgr_set_lcd_timings(channel
, &t
);
3240 xtot
= t
.hactive
+ t
.hfront_porch
+ t
.hsync_len
+ t
.hback_porch
;
3241 ytot
= t
.vactive
+ t
.vfront_porch
+ t
.vsync_len
+ t
.vback_porch
;
3243 ht
= timings
->pixelclock
/ xtot
;
3244 vt
= timings
->pixelclock
/ xtot
/ ytot
;
3246 DSSDBG("pck %lu\n", timings
->pixelclock
);
3247 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3248 t
.hsync_len
, t
.hfront_porch
, t
.hback_porch
,
3249 t
.vsync_len
, t
.vfront_porch
, t
.vback_porch
);
3250 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3251 !!(t
.flags
& DISPLAY_FLAGS_VSYNC_HIGH
),
3252 !!(t
.flags
& DISPLAY_FLAGS_HSYNC_HIGH
),
3253 !!(t
.flags
& DISPLAY_FLAGS_PIXDATA_POSEDGE
),
3254 !!(t
.flags
& DISPLAY_FLAGS_DE_HIGH
),
3255 !!(t
.flags
& DISPLAY_FLAGS_SYNC_POSEDGE
));
3257 DSSDBG("hsync %luHz, vsync %luHz\n", ht
, vt
);
3259 if (t
.flags
& DISPLAY_FLAGS_INTERLACED
)
3262 if (dispc
.feat
->supports_double_pixel
)
3263 REG_FLD_MOD(DISPC_CONTROL
,
3264 !!(t
.flags
& DISPLAY_FLAGS_DOUBLECLK
),
3268 dispc_mgr_set_size(channel
, t
.hactive
, t
.vactive
);
3270 EXPORT_SYMBOL(dispc_mgr_set_timings
);
3272 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel
, u16 lck_div
,
3275 BUG_ON(lck_div
< 1);
3276 BUG_ON(pck_div
< 1);
3278 dispc_write_reg(DISPC_DIVISORo(channel
),
3279 FLD_VAL(lck_div
, 23, 16) | FLD_VAL(pck_div
, 7, 0));
3281 if (!dss_has_feature(FEAT_CORE_CLK_DIV
) &&
3282 channel
== OMAP_DSS_CHANNEL_LCD
)
3283 dispc
.core_clk_rate
= dispc_fclk_rate() / lck_div
;
3286 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel
, int *lck_div
,
3290 l
= dispc_read_reg(DISPC_DIVISORo(channel
));
3291 *lck_div
= FLD_GET(l
, 23, 16);
3292 *pck_div
= FLD_GET(l
, 7, 0);
3295 static unsigned long dispc_fclk_rate(void)
3298 enum dss_clk_source src
;
3300 src
= dss_get_dispc_clk_source();
3302 if (src
== DSS_CLK_SRC_FCK
) {
3303 r
= dss_get_dispc_clk_rate();
3305 struct dss_pll
*pll
;
3306 unsigned clkout_idx
;
3308 pll
= dss_pll_find_by_src(src
);
3309 clkout_idx
= dss_pll_get_clkout_idx_for_src(src
);
3311 r
= pll
->cinfo
.clkout
[clkout_idx
];
3317 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel
)
3321 enum dss_clk_source src
;
3323 /* for TV, LCLK rate is the FCLK rate */
3324 if (!dss_mgr_is_lcd(channel
))
3325 return dispc_fclk_rate();
3327 src
= dss_get_lcd_clk_source(channel
);
3329 if (src
== DSS_CLK_SRC_FCK
) {
3330 r
= dss_get_dispc_clk_rate();
3332 struct dss_pll
*pll
;
3333 unsigned clkout_idx
;
3335 pll
= dss_pll_find_by_src(src
);
3336 clkout_idx
= dss_pll_get_clkout_idx_for_src(src
);
3338 r
= pll
->cinfo
.clkout
[clkout_idx
];
3341 lcd
= REG_GET(DISPC_DIVISORo(channel
), 23, 16);
3346 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel
)
3350 if (dss_mgr_is_lcd(channel
)) {
3354 l
= dispc_read_reg(DISPC_DIVISORo(channel
));
3356 pcd
= FLD_GET(l
, 7, 0);
3358 r
= dispc_mgr_lclk_rate(channel
);
3362 return dispc
.tv_pclk_rate
;
3366 void dispc_set_tv_pclk(unsigned long pclk
)
3368 dispc
.tv_pclk_rate
= pclk
;
3371 static unsigned long dispc_core_clk_rate(void)
3373 return dispc
.core_clk_rate
;
3376 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane
)
3378 enum omap_channel channel
;
3380 if (plane
== OMAP_DSS_WB
)
3383 channel
= dispc_ovl_get_channel_out(plane
);
3385 return dispc_mgr_pclk_rate(channel
);
3388 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane
)
3390 enum omap_channel channel
;
3392 if (plane
== OMAP_DSS_WB
)
3395 channel
= dispc_ovl_get_channel_out(plane
);
3397 return dispc_mgr_lclk_rate(channel
);
3400 static void dispc_dump_clocks_channel(struct seq_file
*s
, enum omap_channel channel
)
3403 enum dss_clk_source lcd_clk_src
;
3405 seq_printf(s
, "- %s -\n", mgr_desc
[channel
].name
);
3407 lcd_clk_src
= dss_get_lcd_clk_source(channel
);
3409 seq_printf(s
, "%s clk source = %s\n", mgr_desc
[channel
].name
,
3410 dss_get_clk_source_name(lcd_clk_src
));
3412 dispc_mgr_get_lcd_divisor(channel
, &lcd
, &pcd
);
3414 seq_printf(s
, "lck\t\t%-16lulck div\t%u\n",
3415 dispc_mgr_lclk_rate(channel
), lcd
);
3416 seq_printf(s
, "pck\t\t%-16lupck div\t%u\n",
3417 dispc_mgr_pclk_rate(channel
), pcd
);
3420 void dispc_dump_clocks(struct seq_file
*s
)
3424 enum dss_clk_source dispc_clk_src
= dss_get_dispc_clk_source();
3426 if (dispc_runtime_get())
3429 seq_printf(s
, "- DISPC -\n");
3431 seq_printf(s
, "dispc fclk source = %s\n",
3432 dss_get_clk_source_name(dispc_clk_src
));
3434 seq_printf(s
, "fck\t\t%-16lu\n", dispc_fclk_rate());
3436 if (dss_has_feature(FEAT_CORE_CLK_DIV
)) {
3437 seq_printf(s
, "- DISPC-CORE-CLK -\n");
3438 l
= dispc_read_reg(DISPC_DIVISOR
);
3439 lcd
= FLD_GET(l
, 23, 16);
3441 seq_printf(s
, "lck\t\t%-16lulck div\t%u\n",
3442 (dispc_fclk_rate()/lcd
), lcd
);
3445 dispc_dump_clocks_channel(s
, OMAP_DSS_CHANNEL_LCD
);
3447 if (dss_has_feature(FEAT_MGR_LCD2
))
3448 dispc_dump_clocks_channel(s
, OMAP_DSS_CHANNEL_LCD2
);
3449 if (dss_has_feature(FEAT_MGR_LCD3
))
3450 dispc_dump_clocks_channel(s
, OMAP_DSS_CHANNEL_LCD3
);
3452 dispc_runtime_put();
3455 static void dispc_dump_regs(struct seq_file
*s
)
3458 const char *mgr_names
[] = {
3459 [OMAP_DSS_CHANNEL_LCD
] = "LCD",
3460 [OMAP_DSS_CHANNEL_DIGIT
] = "TV",
3461 [OMAP_DSS_CHANNEL_LCD2
] = "LCD2",
3462 [OMAP_DSS_CHANNEL_LCD3
] = "LCD3",
3464 const char *ovl_names
[] = {
3465 [OMAP_DSS_GFX
] = "GFX",
3466 [OMAP_DSS_VIDEO1
] = "VID1",
3467 [OMAP_DSS_VIDEO2
] = "VID2",
3468 [OMAP_DSS_VIDEO3
] = "VID3",
3469 [OMAP_DSS_WB
] = "WB",
3471 const char **p_names
;
3473 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3475 if (dispc_runtime_get())
3478 /* DISPC common registers */
3479 DUMPREG(DISPC_REVISION
);
3480 DUMPREG(DISPC_SYSCONFIG
);
3481 DUMPREG(DISPC_SYSSTATUS
);
3482 DUMPREG(DISPC_IRQSTATUS
);
3483 DUMPREG(DISPC_IRQENABLE
);
3484 DUMPREG(DISPC_CONTROL
);
3485 DUMPREG(DISPC_CONFIG
);
3486 DUMPREG(DISPC_CAPABLE
);
3487 DUMPREG(DISPC_LINE_STATUS
);
3488 DUMPREG(DISPC_LINE_NUMBER
);
3489 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
) ||
3490 dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
3491 DUMPREG(DISPC_GLOBAL_ALPHA
);
3492 if (dss_has_feature(FEAT_MGR_LCD2
)) {
3493 DUMPREG(DISPC_CONTROL2
);
3494 DUMPREG(DISPC_CONFIG2
);
3496 if (dss_has_feature(FEAT_MGR_LCD3
)) {
3497 DUMPREG(DISPC_CONTROL3
);
3498 DUMPREG(DISPC_CONFIG3
);
3500 if (dss_has_feature(FEAT_MFLAG
))
3501 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE
);
3505 #define DISPC_REG(i, name) name(i)
3506 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3507 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3508 dispc_read_reg(DISPC_REG(i, r)))
3510 p_names
= mgr_names
;
3512 /* DISPC channel specific registers */
3513 for (i
= 0; i
< dss_feat_get_num_mgrs(); i
++) {
3514 DUMPREG(i
, DISPC_DEFAULT_COLOR
);
3515 DUMPREG(i
, DISPC_TRANS_COLOR
);
3516 DUMPREG(i
, DISPC_SIZE_MGR
);
3518 if (i
== OMAP_DSS_CHANNEL_DIGIT
)
3521 DUMPREG(i
, DISPC_TIMING_H
);
3522 DUMPREG(i
, DISPC_TIMING_V
);
3523 DUMPREG(i
, DISPC_POL_FREQ
);
3524 DUMPREG(i
, DISPC_DIVISORo
);
3526 DUMPREG(i
, DISPC_DATA_CYCLE1
);
3527 DUMPREG(i
, DISPC_DATA_CYCLE2
);
3528 DUMPREG(i
, DISPC_DATA_CYCLE3
);
3530 if (dss_has_feature(FEAT_CPR
)) {
3531 DUMPREG(i
, DISPC_CPR_COEF_R
);
3532 DUMPREG(i
, DISPC_CPR_COEF_G
);
3533 DUMPREG(i
, DISPC_CPR_COEF_B
);
3537 p_names
= ovl_names
;
3539 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++) {
3540 DUMPREG(i
, DISPC_OVL_BA0
);
3541 DUMPREG(i
, DISPC_OVL_BA1
);
3542 DUMPREG(i
, DISPC_OVL_POSITION
);
3543 DUMPREG(i
, DISPC_OVL_SIZE
);
3544 DUMPREG(i
, DISPC_OVL_ATTRIBUTES
);
3545 DUMPREG(i
, DISPC_OVL_FIFO_THRESHOLD
);
3546 DUMPREG(i
, DISPC_OVL_FIFO_SIZE_STATUS
);
3547 DUMPREG(i
, DISPC_OVL_ROW_INC
);
3548 DUMPREG(i
, DISPC_OVL_PIXEL_INC
);
3550 if (dss_has_feature(FEAT_PRELOAD
))
3551 DUMPREG(i
, DISPC_OVL_PRELOAD
);
3552 if (dss_has_feature(FEAT_MFLAG
))
3553 DUMPREG(i
, DISPC_OVL_MFLAG_THRESHOLD
);
3555 if (i
== OMAP_DSS_GFX
) {
3556 DUMPREG(i
, DISPC_OVL_WINDOW_SKIP
);
3557 DUMPREG(i
, DISPC_OVL_TABLE_BA
);
3561 DUMPREG(i
, DISPC_OVL_FIR
);
3562 DUMPREG(i
, DISPC_OVL_PICTURE_SIZE
);
3563 DUMPREG(i
, DISPC_OVL_ACCU0
);
3564 DUMPREG(i
, DISPC_OVL_ACCU1
);
3565 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
3566 DUMPREG(i
, DISPC_OVL_BA0_UV
);
3567 DUMPREG(i
, DISPC_OVL_BA1_UV
);
3568 DUMPREG(i
, DISPC_OVL_FIR2
);
3569 DUMPREG(i
, DISPC_OVL_ACCU2_0
);
3570 DUMPREG(i
, DISPC_OVL_ACCU2_1
);
3572 if (dss_has_feature(FEAT_ATTR2
))
3573 DUMPREG(i
, DISPC_OVL_ATTRIBUTES2
);
3576 if (dispc
.feat
->has_writeback
) {
3578 DUMPREG(i
, DISPC_OVL_BA0
);
3579 DUMPREG(i
, DISPC_OVL_BA1
);
3580 DUMPREG(i
, DISPC_OVL_SIZE
);
3581 DUMPREG(i
, DISPC_OVL_ATTRIBUTES
);
3582 DUMPREG(i
, DISPC_OVL_FIFO_THRESHOLD
);
3583 DUMPREG(i
, DISPC_OVL_FIFO_SIZE_STATUS
);
3584 DUMPREG(i
, DISPC_OVL_ROW_INC
);
3585 DUMPREG(i
, DISPC_OVL_PIXEL_INC
);
3587 if (dss_has_feature(FEAT_MFLAG
))
3588 DUMPREG(i
, DISPC_OVL_MFLAG_THRESHOLD
);
3590 DUMPREG(i
, DISPC_OVL_FIR
);
3591 DUMPREG(i
, DISPC_OVL_PICTURE_SIZE
);
3592 DUMPREG(i
, DISPC_OVL_ACCU0
);
3593 DUMPREG(i
, DISPC_OVL_ACCU1
);
3594 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
3595 DUMPREG(i
, DISPC_OVL_BA0_UV
);
3596 DUMPREG(i
, DISPC_OVL_BA1_UV
);
3597 DUMPREG(i
, DISPC_OVL_FIR2
);
3598 DUMPREG(i
, DISPC_OVL_ACCU2_0
);
3599 DUMPREG(i
, DISPC_OVL_ACCU2_1
);
3601 if (dss_has_feature(FEAT_ATTR2
))
3602 DUMPREG(i
, DISPC_OVL_ATTRIBUTES2
);
3608 #define DISPC_REG(plane, name, i) name(plane, i)
3609 #define DUMPREG(plane, name, i) \
3610 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3611 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3612 dispc_read_reg(DISPC_REG(plane, name, i)))
3614 /* Video pipeline coefficient registers */
3616 /* start from OMAP_DSS_VIDEO1 */
3617 for (i
= 1; i
< dss_feat_get_num_ovls(); i
++) {
3618 for (j
= 0; j
< 8; j
++)
3619 DUMPREG(i
, DISPC_OVL_FIR_COEF_H
, j
);
3621 for (j
= 0; j
< 8; j
++)
3622 DUMPREG(i
, DISPC_OVL_FIR_COEF_HV
, j
);
3624 for (j
= 0; j
< 5; j
++)
3625 DUMPREG(i
, DISPC_OVL_CONV_COEF
, j
);
3627 if (dss_has_feature(FEAT_FIR_COEF_V
)) {
3628 for (j
= 0; j
< 8; j
++)
3629 DUMPREG(i
, DISPC_OVL_FIR_COEF_V
, j
);
3632 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
3633 for (j
= 0; j
< 8; j
++)
3634 DUMPREG(i
, DISPC_OVL_FIR_COEF_H2
, j
);
3636 for (j
= 0; j
< 8; j
++)
3637 DUMPREG(i
, DISPC_OVL_FIR_COEF_HV2
, j
);
3639 for (j
= 0; j
< 8; j
++)
3640 DUMPREG(i
, DISPC_OVL_FIR_COEF_V2
, j
);
3644 dispc_runtime_put();
3650 /* calculate clock rates using dividers in cinfo */
3651 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate
,
3652 struct dispc_clock_info
*cinfo
)
3654 if (cinfo
->lck_div
> 255 || cinfo
->lck_div
== 0)
3656 if (cinfo
->pck_div
< 1 || cinfo
->pck_div
> 255)
3659 cinfo
->lck
= dispc_fclk_rate
/ cinfo
->lck_div
;
3660 cinfo
->pck
= cinfo
->lck
/ cinfo
->pck_div
;
3665 bool dispc_div_calc(unsigned long dispc
,
3666 unsigned long pck_min
, unsigned long pck_max
,
3667 dispc_div_calc_func func
, void *data
)
3669 int lckd
, lckd_start
, lckd_stop
;
3670 int pckd
, pckd_start
, pckd_stop
;
3671 unsigned long pck
, lck
;
3672 unsigned long lck_max
;
3673 unsigned long pckd_hw_min
, pckd_hw_max
;
3674 unsigned min_fck_per_pck
;
3677 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3678 min_fck_per_pck
= CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
;
3680 min_fck_per_pck
= 0;
3683 pckd_hw_min
= dss_feat_get_param_min(FEAT_PARAM_DSS_PCD
);
3684 pckd_hw_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_PCD
);
3686 lck_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
3688 pck_min
= pck_min
? pck_min
: 1;
3689 pck_max
= pck_max
? pck_max
: ULONG_MAX
;
3691 lckd_start
= max(DIV_ROUND_UP(dispc
, lck_max
), 1ul);
3692 lckd_stop
= min(dispc
/ pck_min
, 255ul);
3694 for (lckd
= lckd_start
; lckd
<= lckd_stop
; ++lckd
) {
3697 pckd_start
= max(DIV_ROUND_UP(lck
, pck_max
), pckd_hw_min
);
3698 pckd_stop
= min(lck
/ pck_min
, pckd_hw_max
);
3700 for (pckd
= pckd_start
; pckd
<= pckd_stop
; ++pckd
) {
3704 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3705 * clock, which means we're configuring DISPC fclk here
3706 * also. Thus we need to use the calculated lck. For
3707 * OMAP4+ the DISPC fclk is a separate clock.
3709 if (dss_has_feature(FEAT_CORE_CLK_DIV
))
3710 fck
= dispc_core_clk_rate();
3714 if (fck
< pck
* min_fck_per_pck
)
3717 if (func(lckd
, pckd
, lck
, pck
, data
))
3725 void dispc_mgr_set_clock_div(enum omap_channel channel
,
3726 const struct dispc_clock_info
*cinfo
)
3728 DSSDBG("lck = %lu (%u)\n", cinfo
->lck
, cinfo
->lck_div
);
3729 DSSDBG("pck = %lu (%u)\n", cinfo
->pck
, cinfo
->pck_div
);
3731 dispc_mgr_set_lcd_divisor(channel
, cinfo
->lck_div
, cinfo
->pck_div
);
3734 int dispc_mgr_get_clock_div(enum omap_channel channel
,
3735 struct dispc_clock_info
*cinfo
)
3739 fck
= dispc_fclk_rate();
3741 cinfo
->lck_div
= REG_GET(DISPC_DIVISORo(channel
), 23, 16);
3742 cinfo
->pck_div
= REG_GET(DISPC_DIVISORo(channel
), 7, 0);
3744 cinfo
->lck
= fck
/ cinfo
->lck_div
;
3745 cinfo
->pck
= cinfo
->lck
/ cinfo
->pck_div
;
3750 u32
dispc_read_irqstatus(void)
3752 return dispc_read_reg(DISPC_IRQSTATUS
);
3754 EXPORT_SYMBOL(dispc_read_irqstatus
);
3756 void dispc_clear_irqstatus(u32 mask
)
3758 dispc_write_reg(DISPC_IRQSTATUS
, mask
);
3760 EXPORT_SYMBOL(dispc_clear_irqstatus
);
3762 u32
dispc_read_irqenable(void)
3764 return dispc_read_reg(DISPC_IRQENABLE
);
3766 EXPORT_SYMBOL(dispc_read_irqenable
);
3768 void dispc_write_irqenable(u32 mask
)
3770 u32 old_mask
= dispc_read_reg(DISPC_IRQENABLE
);
3772 /* clear the irqstatus for newly enabled irqs */
3773 dispc_clear_irqstatus((mask
^ old_mask
) & mask
);
3775 dispc_write_reg(DISPC_IRQENABLE
, mask
);
3777 EXPORT_SYMBOL(dispc_write_irqenable
);
3779 void dispc_enable_sidle(void)
3781 REG_FLD_MOD(DISPC_SYSCONFIG
, 2, 4, 3); /* SIDLEMODE: smart idle */
3784 void dispc_disable_sidle(void)
3786 REG_FLD_MOD(DISPC_SYSCONFIG
, 1, 4, 3); /* SIDLEMODE: no idle */
3789 u32
dispc_mgr_gamma_size(enum omap_channel channel
)
3791 const struct dispc_gamma_desc
*gdesc
= &mgr_desc
[channel
].gamma
;
3793 if (!dispc
.feat
->has_gamma_table
)
3798 EXPORT_SYMBOL(dispc_mgr_gamma_size
);
3800 static void dispc_mgr_write_gamma_table(enum omap_channel channel
)
3802 const struct dispc_gamma_desc
*gdesc
= &mgr_desc
[channel
].gamma
;
3803 u32
*table
= dispc
.gamma_table
[channel
];
3806 DSSDBG("%s: channel %d\n", __func__
, channel
);
3808 for (i
= 0; i
< gdesc
->len
; ++i
) {
3811 if (gdesc
->has_index
)
3816 dispc_write_reg(gdesc
->reg
, v
);
3820 static void dispc_restore_gamma_tables(void)
3822 DSSDBG("%s()\n", __func__
);
3824 if (!dispc
.feat
->has_gamma_table
)
3827 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD
);
3829 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT
);
3831 if (dss_has_feature(FEAT_MGR_LCD2
))
3832 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2
);
3834 if (dss_has_feature(FEAT_MGR_LCD3
))
3835 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3
);
3838 static const struct drm_color_lut dispc_mgr_gamma_default_lut
[] = {
3839 { .red
= 0, .green
= 0, .blue
= 0, },
3840 { .red
= U16_MAX
, .green
= U16_MAX
, .blue
= U16_MAX
, },
3843 void dispc_mgr_set_gamma(enum omap_channel channel
,
3844 const struct drm_color_lut
*lut
,
3845 unsigned int length
)
3847 const struct dispc_gamma_desc
*gdesc
= &mgr_desc
[channel
].gamma
;
3848 u32
*table
= dispc
.gamma_table
[channel
];
3851 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__
,
3852 channel
, length
, gdesc
->len
);
3854 if (!dispc
.feat
->has_gamma_table
)
3857 if (lut
== NULL
|| length
< 2) {
3858 lut
= dispc_mgr_gamma_default_lut
;
3859 length
= ARRAY_SIZE(dispc_mgr_gamma_default_lut
);
3862 for (i
= 0; i
< length
- 1; ++i
) {
3863 uint first
= i
* (gdesc
->len
- 1) / (length
- 1);
3864 uint last
= (i
+ 1) * (gdesc
->len
- 1) / (length
- 1);
3865 uint w
= last
- first
;
3872 for (j
= 0; j
<= w
; j
++) {
3873 r
= (lut
[i
].red
* (w
- j
) + lut
[i
+1].red
* j
) / w
;
3874 g
= (lut
[i
].green
* (w
- j
) + lut
[i
+1].green
* j
) / w
;
3875 b
= (lut
[i
].blue
* (w
- j
) + lut
[i
+1].blue
* j
) / w
;
3877 r
>>= 16 - gdesc
->bits
;
3878 g
>>= 16 - gdesc
->bits
;
3879 b
>>= 16 - gdesc
->bits
;
3881 table
[first
+ j
] = (r
<< (gdesc
->bits
* 2)) |
3882 (g
<< gdesc
->bits
) | b
;
3886 if (dispc
.is_enabled
)
3887 dispc_mgr_write_gamma_table(channel
);
3889 EXPORT_SYMBOL(dispc_mgr_set_gamma
);
3891 static int dispc_init_gamma_tables(void)
3895 if (!dispc
.feat
->has_gamma_table
)
3898 for (channel
= 0; channel
< ARRAY_SIZE(dispc
.gamma_table
); channel
++) {
3899 const struct dispc_gamma_desc
*gdesc
= &mgr_desc
[channel
].gamma
;
3902 if (channel
== OMAP_DSS_CHANNEL_LCD2
&&
3903 !dss_has_feature(FEAT_MGR_LCD2
))
3906 if (channel
== OMAP_DSS_CHANNEL_LCD3
&&
3907 !dss_has_feature(FEAT_MGR_LCD3
))
3910 gt
= devm_kmalloc_array(&dispc
.pdev
->dev
, gdesc
->len
,
3911 sizeof(u32
), GFP_KERNEL
);
3915 dispc
.gamma_table
[channel
] = gt
;
3917 dispc_mgr_set_gamma(channel
, NULL
, 0);
3922 static void _omap_dispc_initial_config(void)
3926 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3927 if (dss_has_feature(FEAT_CORE_CLK_DIV
)) {
3928 l
= dispc_read_reg(DISPC_DIVISOR
);
3929 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3930 l
= FLD_MOD(l
, 1, 0, 0);
3931 l
= FLD_MOD(l
, 1, 23, 16);
3932 dispc_write_reg(DISPC_DIVISOR
, l
);
3934 dispc
.core_clk_rate
= dispc_fclk_rate();
3937 /* Use gamma table mode, instead of palette mode */
3938 if (dispc
.feat
->has_gamma_table
)
3939 REG_FLD_MOD(DISPC_CONFIG
, 1, 3, 3);
3941 /* For older DSS versions (FEAT_FUNCGATED) this enables
3942 * func-clock auto-gating. For newer versions
3943 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables.
3945 if (dss_has_feature(FEAT_FUNCGATED
) || dispc
.feat
->has_gamma_table
)
3946 REG_FLD_MOD(DISPC_CONFIG
, 1, 9, 9);
3948 dispc_setup_color_conv_coef();
3950 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY
);
3954 dispc_configure_burst_sizes();
3956 dispc_ovl_enable_zorder_planes();
3958 if (dispc
.feat
->mstandby_workaround
)
3959 REG_FLD_MOD(DISPC_MSTANDBY_CTRL
, 1, 0, 0);
3961 if (dss_has_feature(FEAT_MFLAG
))
3965 static const struct dispc_features omap24xx_dispc_feats
= {
3972 .mgr_width_start
= 10,
3973 .mgr_height_start
= 26,
3974 .mgr_width_max
= 2048,
3975 .mgr_height_max
= 2048,
3976 .max_lcd_pclk
= 66500000,
3977 .calc_scaling
= dispc_ovl_calc_scaling_24xx
,
3978 .calc_core_clk
= calc_core_clk_24xx
,
3980 .no_framedone_tv
= true,
3981 .set_max_preload
= false,
3982 .last_pixel_inc_missing
= true,
3985 static const struct dispc_features omap34xx_rev1_0_dispc_feats
= {
3992 .mgr_width_start
= 10,
3993 .mgr_height_start
= 26,
3994 .mgr_width_max
= 2048,
3995 .mgr_height_max
= 2048,
3996 .max_lcd_pclk
= 173000000,
3997 .max_tv_pclk
= 59000000,
3998 .calc_scaling
= dispc_ovl_calc_scaling_34xx
,
3999 .calc_core_clk
= calc_core_clk_34xx
,
4001 .no_framedone_tv
= true,
4002 .set_max_preload
= false,
4003 .last_pixel_inc_missing
= true,
4006 static const struct dispc_features omap34xx_rev3_0_dispc_feats
= {
4013 .mgr_width_start
= 10,
4014 .mgr_height_start
= 26,
4015 .mgr_width_max
= 2048,
4016 .mgr_height_max
= 2048,
4017 .max_lcd_pclk
= 173000000,
4018 .max_tv_pclk
= 59000000,
4019 .calc_scaling
= dispc_ovl_calc_scaling_34xx
,
4020 .calc_core_clk
= calc_core_clk_34xx
,
4022 .no_framedone_tv
= true,
4023 .set_max_preload
= false,
4024 .last_pixel_inc_missing
= true,
4027 static const struct dispc_features omap44xx_dispc_feats
= {
4034 .mgr_width_start
= 10,
4035 .mgr_height_start
= 26,
4036 .mgr_width_max
= 2048,
4037 .mgr_height_max
= 2048,
4038 .max_lcd_pclk
= 170000000,
4039 .max_tv_pclk
= 185625000,
4040 .calc_scaling
= dispc_ovl_calc_scaling_44xx
,
4041 .calc_core_clk
= calc_core_clk_44xx
,
4043 .gfx_fifo_workaround
= true,
4044 .set_max_preload
= true,
4045 .supports_sync_align
= true,
4046 .has_writeback
= true,
4047 .supports_double_pixel
= true,
4048 .reverse_ilace_field_order
= true,
4049 .has_gamma_table
= true,
4050 .has_gamma_i734_bug
= true,
4053 static const struct dispc_features omap54xx_dispc_feats
= {
4060 .mgr_width_start
= 11,
4061 .mgr_height_start
= 27,
4062 .mgr_width_max
= 4096,
4063 .mgr_height_max
= 4096,
4064 .max_lcd_pclk
= 170000000,
4065 .max_tv_pclk
= 186000000,
4066 .calc_scaling
= dispc_ovl_calc_scaling_44xx
,
4067 .calc_core_clk
= calc_core_clk_44xx
,
4069 .gfx_fifo_workaround
= true,
4070 .mstandby_workaround
= true,
4071 .set_max_preload
= true,
4072 .supports_sync_align
= true,
4073 .has_writeback
= true,
4074 .supports_double_pixel
= true,
4075 .reverse_ilace_field_order
= true,
4076 .has_gamma_table
= true,
4077 .has_gamma_i734_bug
= true,
4080 static int dispc_init_features(struct platform_device
*pdev
)
4082 const struct dispc_features
*src
;
4083 struct dispc_features
*dst
;
4085 dst
= devm_kzalloc(&pdev
->dev
, sizeof(*dst
), GFP_KERNEL
);
4087 dev_err(&pdev
->dev
, "Failed to allocate DISPC Features\n");
4091 switch (omapdss_get_version()) {
4092 case OMAPDSS_VER_OMAP24xx
:
4093 src
= &omap24xx_dispc_feats
;
4096 case OMAPDSS_VER_OMAP34xx_ES1
:
4097 src
= &omap34xx_rev1_0_dispc_feats
;
4100 case OMAPDSS_VER_OMAP34xx_ES3
:
4101 case OMAPDSS_VER_OMAP3630
:
4102 case OMAPDSS_VER_AM35xx
:
4103 case OMAPDSS_VER_AM43xx
:
4104 src
= &omap34xx_rev3_0_dispc_feats
;
4107 case OMAPDSS_VER_OMAP4430_ES1
:
4108 case OMAPDSS_VER_OMAP4430_ES2
:
4109 case OMAPDSS_VER_OMAP4
:
4110 src
= &omap44xx_dispc_feats
;
4113 case OMAPDSS_VER_OMAP5
:
4114 case OMAPDSS_VER_DRA7xx
:
4115 src
= &omap54xx_dispc_feats
;
4122 memcpy(dst
, src
, sizeof(*dst
));
4128 static irqreturn_t
dispc_irq_handler(int irq
, void *arg
)
4130 if (!dispc
.is_enabled
)
4133 return dispc
.user_handler(irq
, dispc
.user_data
);
4136 int dispc_request_irq(irq_handler_t handler
, void *dev_id
)
4140 if (dispc
.user_handler
!= NULL
)
4143 dispc
.user_handler
= handler
;
4144 dispc
.user_data
= dev_id
;
4146 /* ensure the dispc_irq_handler sees the values above */
4149 r
= devm_request_irq(&dispc
.pdev
->dev
, dispc
.irq
, dispc_irq_handler
,
4150 IRQF_SHARED
, "OMAP DISPC", &dispc
);
4152 dispc
.user_handler
= NULL
;
4153 dispc
.user_data
= NULL
;
4158 EXPORT_SYMBOL(dispc_request_irq
);
4160 void dispc_free_irq(void *dev_id
)
4162 devm_free_irq(&dispc
.pdev
->dev
, dispc
.irq
, &dispc
);
4164 dispc
.user_handler
= NULL
;
4165 dispc
.user_data
= NULL
;
4167 EXPORT_SYMBOL(dispc_free_irq
);
4170 * Workaround for errata i734 in DSS dispc
4171 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4173 * For gamma tables to work on LCD1 the GFX plane has to be used at
4174 * least once after DSS HW has come out of reset. The workaround
4175 * sets up a minimal LCD setup with GFX plane and waits for one
4176 * vertical sync irq before disabling the setup and continuing with
4177 * the context restore. The physical outputs are gated during the
4178 * operation. This workaround requires that gamma table's LOADMODE
4179 * is set to 0x2 in DISPC_CONTROL1 register.
4182 * OMAP543x Multimedia Device Silicon Revision 2.0 Silicon Errata
4183 * Literature Number: SWPZ037E
4184 * Or some other relevant errata document for the DSS IP version.
4187 static const struct dispc_errata_i734_data
{
4188 struct videomode timings
;
4189 struct omap_overlay_info ovli
;
4190 struct omap_overlay_manager_info mgri
;
4191 struct dss_lcd_mgr_config lcd_conf
;
4194 .hactive
= 8, .vactive
= 1,
4195 .pixelclock
= 16000000,
4196 .hsync_len
= 8, .hfront_porch
= 4, .hback_porch
= 4,
4197 .vsync_len
= 1, .vfront_porch
= 1, .vback_porch
= 1,
4199 .flags
= DISPLAY_FLAGS_HSYNC_LOW
| DISPLAY_FLAGS_VSYNC_LOW
|
4200 DISPLAY_FLAGS_DE_HIGH
| DISPLAY_FLAGS_SYNC_POSEDGE
|
4201 DISPLAY_FLAGS_PIXDATA_POSEDGE
,
4205 .width
= 1, .height
= 1,
4206 .color_mode
= OMAP_DSS_COLOR_RGB24U
,
4207 .rotation
= OMAP_DSS_ROT_0
,
4208 .rotation_type
= OMAP_DSS_ROT_DMA
,
4210 .pos_x
= 0, .pos_y
= 0,
4211 .out_width
= 0, .out_height
= 0,
4212 .global_alpha
= 0xff,
4213 .pre_mult_alpha
= 0,
4218 .trans_enabled
= false,
4219 .partial_alpha_enabled
= false,
4220 .cpr_enable
= false,
4223 .io_pad_mode
= DSS_IO_PAD_MODE_BYPASS
,
4225 .fifohandcheck
= false,
4230 .video_port_width
= 24,
4231 .lcden_sig_polarity
= 0,
4235 static struct i734_buf
{
4241 static int dispc_errata_i734_wa_init(void)
4243 if (!dispc
.feat
->has_gamma_i734_bug
)
4246 i734_buf
.size
= i734
.ovli
.width
* i734
.ovli
.height
*
4247 color_mode_to_bpp(i734
.ovli
.color_mode
) / 8;
4249 i734_buf
.vaddr
= dma_alloc_writecombine(&dispc
.pdev
->dev
, i734_buf
.size
,
4250 &i734_buf
.paddr
, GFP_KERNEL
);
4251 if (!i734_buf
.vaddr
) {
4252 dev_err(&dispc
.pdev
->dev
, "%s: dma_alloc_writecombine failed",
4260 static void dispc_errata_i734_wa_fini(void)
4262 if (!dispc
.feat
->has_gamma_i734_bug
)
4265 dma_free_writecombine(&dispc
.pdev
->dev
, i734_buf
.size
, i734_buf
.vaddr
,
4269 static void dispc_errata_i734_wa(void)
4271 u32 framedone_irq
= dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD
);
4272 struct omap_overlay_info ovli
;
4273 struct dss_lcd_mgr_config lcd_conf
;
4277 if (!dispc
.feat
->has_gamma_i734_bug
)
4280 gatestate
= REG_GET(DISPC_CONFIG
, 8, 4);
4283 ovli
.paddr
= i734_buf
.paddr
;
4284 lcd_conf
= i734
.lcd_conf
;
4286 /* Gate all LCD1 outputs */
4287 REG_FLD_MOD(DISPC_CONFIG
, 0x1f, 8, 4);
4289 /* Setup and enable GFX plane */
4290 dispc_ovl_set_channel_out(OMAP_DSS_GFX
, OMAP_DSS_CHANNEL_LCD
);
4291 dispc_ovl_setup(OMAP_DSS_GFX
, &ovli
, false, &i734
.timings
, false);
4292 dispc_ovl_enable(OMAP_DSS_GFX
, true);
4294 /* Set up and enable display manager for LCD1 */
4295 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD
, &i734
.mgri
);
4296 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4297 &lcd_conf
.clock_info
);
4298 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD
, &lcd_conf
);
4299 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD
, &i734
.timings
);
4301 dispc_clear_irqstatus(framedone_irq
);
4303 /* Enable and shut the channel to produce just one frame */
4304 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD
, true);
4305 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD
, false);
4307 /* Busy wait for framedone. We can't fiddle with irq handlers
4308 * in PM resume. Typically the loop runs less than 5 times and
4309 * waits less than a micro second.
4312 while (!(dispc_read_irqstatus() & framedone_irq
)) {
4313 if (count
++ > 10000) {
4314 dev_err(&dispc
.pdev
->dev
, "%s: framedone timeout\n",
4319 dispc_ovl_enable(OMAP_DSS_GFX
, false);
4321 /* Clear all irq bits before continuing */
4322 dispc_clear_irqstatus(0xffffffff);
4324 /* Restore the original state to LCD1 output gates */
4325 REG_FLD_MOD(DISPC_CONFIG
, gatestate
, 8, 4);
4328 /* DISPC HW IP initialisation */
4329 static int dispc_bind(struct device
*dev
, struct device
*master
, void *data
)
4331 struct platform_device
*pdev
= to_platform_device(dev
);
4334 struct resource
*dispc_mem
;
4335 struct device_node
*np
= pdev
->dev
.of_node
;
4339 spin_lock_init(&dispc
.control_lock
);
4341 r
= dispc_init_features(dispc
.pdev
);
4345 r
= dispc_errata_i734_wa_init();
4349 dispc_mem
= platform_get_resource(dispc
.pdev
, IORESOURCE_MEM
, 0);
4351 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4355 dispc
.base
= devm_ioremap(&pdev
->dev
, dispc_mem
->start
,
4356 resource_size(dispc_mem
));
4358 DSSERR("can't ioremap DISPC\n");
4362 dispc
.irq
= platform_get_irq(dispc
.pdev
, 0);
4363 if (dispc
.irq
< 0) {
4364 DSSERR("platform_get_irq failed\n");
4368 if (np
&& of_property_read_bool(np
, "syscon-pol")) {
4369 dispc
.syscon_pol
= syscon_regmap_lookup_by_phandle(np
, "syscon-pol");
4370 if (IS_ERR(dispc
.syscon_pol
)) {
4371 dev_err(&pdev
->dev
, "failed to get syscon-pol regmap\n");
4372 return PTR_ERR(dispc
.syscon_pol
);
4375 if (of_property_read_u32_index(np
, "syscon-pol", 1,
4376 &dispc
.syscon_pol_offset
)) {
4377 dev_err(&pdev
->dev
, "failed to get syscon-pol offset\n");
4382 r
= dispc_init_gamma_tables();
4386 pm_runtime_enable(&pdev
->dev
);
4388 r
= dispc_runtime_get();
4390 goto err_runtime_get
;
4392 _omap_dispc_initial_config();
4394 rev
= dispc_read_reg(DISPC_REVISION
);
4395 dev_dbg(&pdev
->dev
, "OMAP DISPC rev %d.%d\n",
4396 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
4398 dispc_runtime_put();
4400 dss_debugfs_create_file("dispc", dispc_dump_regs
);
4405 pm_runtime_disable(&pdev
->dev
);
4409 static void dispc_unbind(struct device
*dev
, struct device
*master
,
4412 pm_runtime_disable(dev
);
4414 dispc_errata_i734_wa_fini();
4417 static const struct component_ops dispc_component_ops
= {
4419 .unbind
= dispc_unbind
,
4422 static int dispc_probe(struct platform_device
*pdev
)
4424 return component_add(&pdev
->dev
, &dispc_component_ops
);
4427 static int dispc_remove(struct platform_device
*pdev
)
4429 component_del(&pdev
->dev
, &dispc_component_ops
);
4433 static int dispc_runtime_suspend(struct device
*dev
)
4435 dispc
.is_enabled
= false;
4436 /* ensure the dispc_irq_handler sees the is_enabled value */
4438 /* wait for current handler to finish before turning the DISPC off */
4439 synchronize_irq(dispc
.irq
);
4441 dispc_save_context();
4446 static int dispc_runtime_resume(struct device
*dev
)
4449 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4450 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4451 * _omap_dispc_initial_config(). We can thus use it to detect if
4452 * we have lost register context.
4454 if (REG_GET(DISPC_CONFIG
, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY
) {
4455 _omap_dispc_initial_config();
4457 dispc_errata_i734_wa();
4459 dispc_restore_context();
4461 dispc_restore_gamma_tables();
4464 dispc
.is_enabled
= true;
4465 /* ensure the dispc_irq_handler sees the is_enabled value */
4471 static const struct dev_pm_ops dispc_pm_ops
= {
4472 .runtime_suspend
= dispc_runtime_suspend
,
4473 .runtime_resume
= dispc_runtime_resume
,
4476 static const struct of_device_id dispc_of_match
[] = {
4477 { .compatible
= "ti,omap2-dispc", },
4478 { .compatible
= "ti,omap3-dispc", },
4479 { .compatible
= "ti,omap4-dispc", },
4480 { .compatible
= "ti,omap5-dispc", },
4481 { .compatible
= "ti,dra7-dispc", },
4485 static struct platform_driver omap_dispchw_driver
= {
4486 .probe
= dispc_probe
,
4487 .remove
= dispc_remove
,
4489 .name
= "omapdss_dispc",
4490 .pm
= &dispc_pm_ops
,
4491 .of_match_table
= dispc_of_match
,
4492 .suppress_bind_attrs
= true,
4496 int __init
dispc_init_platform_driver(void)
4498 return platform_driver_register(&omap_dispchw_driver
);
4501 void dispc_uninit_platform_driver(void)
4503 platform_driver_unregister(&omap_dispchw_driver
);