2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
34 #include <linux/clk.h>
35 #include <linux/sys_soc.h>
41 struct platform_device
*pdev
;
42 enum dss_model dss_model
;
44 struct regulator
*vdds_dsi_reg
;
45 enum dss_clk_source clk_src
;
51 struct dss_lcd_mgr_config mgr_config
;
54 struct omap_dss_device output
;
56 bool port_initialized
;
59 static struct dpi_data
*dpi_get_data_from_dssdev(struct omap_dss_device
*dssdev
)
61 return container_of(dssdev
, struct dpi_data
, output
);
64 static enum dss_clk_source
dpi_get_clk_src_dra7xx(enum omap_channel channel
)
67 * Possible clock sources:
68 * LCD1: FCK/PLL1_1/HDMI_PLL
69 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3)
70 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1)
74 case OMAP_DSS_CHANNEL_LCD
:
76 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_1
))
77 return DSS_CLK_SRC_PLL1_1
;
80 case OMAP_DSS_CHANNEL_LCD2
:
82 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3
))
83 return DSS_CLK_SRC_PLL1_3
;
84 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_3
))
85 return DSS_CLK_SRC_PLL2_3
;
88 case OMAP_DSS_CHANNEL_LCD3
:
90 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_1
))
91 return DSS_CLK_SRC_PLL2_1
;
92 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3
))
93 return DSS_CLK_SRC_PLL1_3
;
100 return DSS_CLK_SRC_FCK
;
103 static enum dss_clk_source
dpi_get_clk_src(struct dpi_data
*dpi
)
105 enum omap_channel channel
= dpi
->output
.dispc_channel
;
108 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
109 * would also be used for DISPC fclk. Meaning, when the DPI output is
110 * disabled, DISPC clock will be disabled, and TV out will stop.
112 switch (dpi
->dss_model
) {
113 case DSS_MODEL_OMAP2
:
114 case DSS_MODEL_OMAP3
:
115 return DSS_CLK_SRC_FCK
;
117 case DSS_MODEL_OMAP4
:
119 case OMAP_DSS_CHANNEL_LCD
:
120 return DSS_CLK_SRC_PLL1_1
;
121 case OMAP_DSS_CHANNEL_LCD2
:
122 return DSS_CLK_SRC_PLL2_1
;
124 return DSS_CLK_SRC_FCK
;
127 case DSS_MODEL_OMAP5
:
129 case OMAP_DSS_CHANNEL_LCD
:
130 return DSS_CLK_SRC_PLL1_1
;
131 case OMAP_DSS_CHANNEL_LCD3
:
132 return DSS_CLK_SRC_PLL2_1
;
133 case OMAP_DSS_CHANNEL_LCD2
:
135 return DSS_CLK_SRC_FCK
;
139 return dpi_get_clk_src_dra7xx(channel
);
142 return DSS_CLK_SRC_FCK
;
146 struct dpi_clk_calc_ctx
{
152 unsigned long pck_min
, pck_max
;
156 struct dss_pll_clock_info pll_cinfo
;
158 struct dispc_clock_info dispc_cinfo
;
161 static bool dpi_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
162 unsigned long pck
, void *data
)
164 struct dpi_clk_calc_ctx
*ctx
= data
;
167 * Odd dividers give us uneven duty cycle, causing problem when level
168 * shifted. So skip all odd dividers when the pixel clock is on the
171 if (ctx
->pck_min
>= 100000000) {
172 if (lckd
> 1 && lckd
% 2 != 0)
175 if (pckd
> 1 && pckd
% 2 != 0)
179 ctx
->dispc_cinfo
.lck_div
= lckd
;
180 ctx
->dispc_cinfo
.pck_div
= pckd
;
181 ctx
->dispc_cinfo
.lck
= lck
;
182 ctx
->dispc_cinfo
.pck
= pck
;
188 static bool dpi_calc_hsdiv_cb(int m_dispc
, unsigned long dispc
,
191 struct dpi_clk_calc_ctx
*ctx
= data
;
193 ctx
->pll_cinfo
.mX
[ctx
->clkout_idx
] = m_dispc
;
194 ctx
->pll_cinfo
.clkout
[ctx
->clkout_idx
] = dispc
;
196 return dispc_div_calc(dispc
, ctx
->pck_min
, ctx
->pck_max
,
197 dpi_calc_dispc_cb
, ctx
);
201 static bool dpi_calc_pll_cb(int n
, int m
, unsigned long fint
,
202 unsigned long clkdco
,
205 struct dpi_clk_calc_ctx
*ctx
= data
;
207 ctx
->pll_cinfo
.n
= n
;
208 ctx
->pll_cinfo
.m
= m
;
209 ctx
->pll_cinfo
.fint
= fint
;
210 ctx
->pll_cinfo
.clkdco
= clkdco
;
212 return dss_pll_hsdiv_calc_a(ctx
->pll
, clkdco
,
213 ctx
->pck_min
, dss_get_max_fck_rate(),
214 dpi_calc_hsdiv_cb
, ctx
);
217 static bool dpi_calc_dss_cb(unsigned long fck
, void *data
)
219 struct dpi_clk_calc_ctx
*ctx
= data
;
223 return dispc_div_calc(fck
, ctx
->pck_min
, ctx
->pck_max
,
224 dpi_calc_dispc_cb
, ctx
);
227 static bool dpi_pll_clk_calc(struct dpi_data
*dpi
, unsigned long pck
,
228 struct dpi_clk_calc_ctx
*ctx
)
232 memset(ctx
, 0, sizeof(*ctx
));
234 ctx
->clkout_idx
= dss_pll_get_clkout_idx_for_src(dpi
->clk_src
);
236 clkin
= clk_get_rate(dpi
->pll
->clkin
);
238 if (dpi
->pll
->hw
->type
== DSS_PLL_TYPE_A
) {
239 unsigned long pll_min
, pll_max
;
241 ctx
->pck_min
= pck
- 1000;
242 ctx
->pck_max
= pck
+ 1000;
247 return dss_pll_calc_a(ctx
->pll
, clkin
,
249 dpi_calc_pll_cb
, ctx
);
250 } else { /* DSS_PLL_TYPE_B */
251 dss_pll_calc_b(dpi
->pll
, clkin
, pck
, &ctx
->pll_cinfo
);
253 ctx
->dispc_cinfo
.lck_div
= 1;
254 ctx
->dispc_cinfo
.pck_div
= 1;
255 ctx
->dispc_cinfo
.lck
= ctx
->pll_cinfo
.clkout
[0];
256 ctx
->dispc_cinfo
.pck
= ctx
->dispc_cinfo
.lck
;
262 static bool dpi_dss_clk_calc(unsigned long pck
, struct dpi_clk_calc_ctx
*ctx
)
267 * DSS fck gives us very few possibilities, so finding a good pixel
268 * clock may not be possible. We try multiple times to find the clock,
269 * each time widening the pixel clock range we look for, up to
273 for (i
= 0; i
< 25; ++i
) {
276 memset(ctx
, 0, sizeof(*ctx
));
277 if (pck
> 1000 * i
* i
* i
)
278 ctx
->pck_min
= max(pck
- 1000 * i
* i
* i
, 0lu);
281 ctx
->pck_max
= pck
+ 1000 * i
* i
* i
;
283 ok
= dss_div_calc(pck
, ctx
->pck_min
, dpi_calc_dss_cb
, ctx
);
293 static int dpi_set_pll_clk(struct dpi_data
*dpi
, enum omap_channel channel
,
294 unsigned long pck_req
, unsigned long *fck
, int *lck_div
,
297 struct dpi_clk_calc_ctx ctx
;
301 ok
= dpi_pll_clk_calc(dpi
, pck_req
, &ctx
);
305 r
= dss_pll_set_config(dpi
->pll
, &ctx
.pll_cinfo
);
309 dss_select_lcd_clk_source(channel
, dpi
->clk_src
);
311 dpi
->mgr_config
.clock_info
= ctx
.dispc_cinfo
;
313 *fck
= ctx
.pll_cinfo
.clkout
[ctx
.clkout_idx
];
314 *lck_div
= ctx
.dispc_cinfo
.lck_div
;
315 *pck_div
= ctx
.dispc_cinfo
.pck_div
;
320 static int dpi_set_dispc_clk(struct dpi_data
*dpi
, unsigned long pck_req
,
321 unsigned long *fck
, int *lck_div
, int *pck_div
)
323 struct dpi_clk_calc_ctx ctx
;
327 ok
= dpi_dss_clk_calc(pck_req
, &ctx
);
331 r
= dss_set_fck_rate(ctx
.fck
);
335 dpi
->mgr_config
.clock_info
= ctx
.dispc_cinfo
;
338 *lck_div
= ctx
.dispc_cinfo
.lck_div
;
339 *pck_div
= ctx
.dispc_cinfo
.pck_div
;
344 static int dpi_set_mode(struct dpi_data
*dpi
)
346 struct omap_dss_device
*out
= &dpi
->output
;
347 enum omap_channel channel
= out
->dispc_channel
;
348 struct videomode
*vm
= &dpi
->vm
;
349 int lck_div
= 0, pck_div
= 0;
350 unsigned long fck
= 0;
355 r
= dpi_set_pll_clk(dpi
, channel
, vm
->pixelclock
, &fck
,
358 r
= dpi_set_dispc_clk(dpi
, vm
->pixelclock
, &fck
,
363 pck
= fck
/ lck_div
/ pck_div
;
365 if (pck
!= vm
->pixelclock
) {
366 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
367 vm
->pixelclock
, pck
);
369 vm
->pixelclock
= pck
;
372 dss_mgr_set_timings(channel
, vm
);
377 static void dpi_config_lcd_manager(struct dpi_data
*dpi
)
379 struct omap_dss_device
*out
= &dpi
->output
;
380 enum omap_channel channel
= out
->dispc_channel
;
382 dpi
->mgr_config
.io_pad_mode
= DSS_IO_PAD_MODE_BYPASS
;
384 dpi
->mgr_config
.stallmode
= false;
385 dpi
->mgr_config
.fifohandcheck
= false;
387 dpi
->mgr_config
.video_port_width
= dpi
->data_lines
;
389 dpi
->mgr_config
.lcden_sig_polarity
= 0;
391 dss_mgr_set_lcd_config(channel
, &dpi
->mgr_config
);
394 static int dpi_display_enable(struct omap_dss_device
*dssdev
)
396 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
397 struct omap_dss_device
*out
= &dpi
->output
;
398 enum omap_channel channel
= out
->dispc_channel
;
401 mutex_lock(&dpi
->lock
);
403 if (!out
->dispc_channel_connected
) {
404 DSSERR("failed to enable display: no output/manager\n");
409 if (dpi
->vdds_dsi_reg
) {
410 r
= regulator_enable(dpi
->vdds_dsi_reg
);
415 r
= dispc_runtime_get();
419 r
= dss_dpi_select_source(out
->port_num
, channel
);
424 r
= dss_pll_enable(dpi
->pll
);
429 r
= dpi_set_mode(dpi
);
433 dpi_config_lcd_manager(dpi
);
437 r
= dss_mgr_enable(channel
);
441 mutex_unlock(&dpi
->lock
);
448 dss_pll_disable(dpi
->pll
);
453 if (dpi
->vdds_dsi_reg
)
454 regulator_disable(dpi
->vdds_dsi_reg
);
457 mutex_unlock(&dpi
->lock
);
461 static void dpi_display_disable(struct omap_dss_device
*dssdev
)
463 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
464 enum omap_channel channel
= dpi
->output
.dispc_channel
;
466 mutex_lock(&dpi
->lock
);
468 dss_mgr_disable(channel
);
471 dss_select_lcd_clk_source(channel
, DSS_CLK_SRC_FCK
);
472 dss_pll_disable(dpi
->pll
);
477 if (dpi
->vdds_dsi_reg
)
478 regulator_disable(dpi
->vdds_dsi_reg
);
480 mutex_unlock(&dpi
->lock
);
483 static void dpi_set_timings(struct omap_dss_device
*dssdev
,
484 struct videomode
*vm
)
486 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
488 DSSDBG("dpi_set_timings\n");
490 mutex_lock(&dpi
->lock
);
494 mutex_unlock(&dpi
->lock
);
497 static void dpi_get_timings(struct omap_dss_device
*dssdev
,
498 struct videomode
*vm
)
500 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
502 mutex_lock(&dpi
->lock
);
506 mutex_unlock(&dpi
->lock
);
509 static int dpi_check_timings(struct omap_dss_device
*dssdev
,
510 struct videomode
*vm
)
512 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
513 enum omap_channel channel
= dpi
->output
.dispc_channel
;
514 int lck_div
, pck_div
;
517 struct dpi_clk_calc_ctx ctx
;
520 if (vm
->hactive
% 8 != 0)
523 if (!dispc_mgr_timings_ok(channel
, vm
))
526 if (vm
->pixelclock
== 0)
530 ok
= dpi_pll_clk_calc(dpi
, vm
->pixelclock
, &ctx
);
534 fck
= ctx
.pll_cinfo
.clkout
[ctx
.clkout_idx
];
536 ok
= dpi_dss_clk_calc(vm
->pixelclock
, &ctx
);
543 lck_div
= ctx
.dispc_cinfo
.lck_div
;
544 pck_div
= ctx
.dispc_cinfo
.pck_div
;
546 pck
= fck
/ lck_div
/ pck_div
;
548 vm
->pixelclock
= pck
;
553 static int dpi_verify_pll(struct dss_pll
*pll
)
557 /* do initial setup with the PLL to see if it is operational */
559 r
= dss_pll_enable(pll
);
563 dss_pll_disable(pll
);
568 static const struct soc_device_attribute dpi_soc_devices
[] = {
569 { .family
= "OMAP3[456]*" },
570 { .family
= "[AD]M37*" },
574 static int dpi_init_regulator(struct dpi_data
*dpi
)
576 struct regulator
*vdds_dsi
;
579 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and
582 if (!soc_device_match(dpi_soc_devices
))
585 if (dpi
->vdds_dsi_reg
)
588 vdds_dsi
= devm_regulator_get(&dpi
->pdev
->dev
, "vdds_dsi");
589 if (IS_ERR(vdds_dsi
)) {
590 if (PTR_ERR(vdds_dsi
) != -EPROBE_DEFER
)
591 DSSERR("can't get VDDS_DSI regulator\n");
592 return PTR_ERR(vdds_dsi
);
595 dpi
->vdds_dsi_reg
= vdds_dsi
;
600 static void dpi_init_pll(struct dpi_data
*dpi
)
607 dpi
->clk_src
= dpi_get_clk_src(dpi
);
609 pll
= dss_pll_find_by_src(dpi
->clk_src
);
613 if (dpi_verify_pll(pll
)) {
614 DSSWARN("PLL not operational\n");
622 * Return a hardcoded channel for the DPI output. This should work for
623 * current use cases, but this can be later expanded to either resolve
624 * the channel in some more dynamic manner, or get the channel as a user
627 static enum omap_channel
dpi_get_channel(struct dpi_data
*dpi
, int port_num
)
629 switch (dpi
->dss_model
) {
630 case DSS_MODEL_OMAP2
:
631 case DSS_MODEL_OMAP3
:
632 return OMAP_DSS_CHANNEL_LCD
;
637 return OMAP_DSS_CHANNEL_LCD3
;
639 return OMAP_DSS_CHANNEL_LCD2
;
642 return OMAP_DSS_CHANNEL_LCD
;
645 case DSS_MODEL_OMAP4
:
646 return OMAP_DSS_CHANNEL_LCD2
;
648 case DSS_MODEL_OMAP5
:
649 return OMAP_DSS_CHANNEL_LCD3
;
652 DSSWARN("unsupported DSS version\n");
653 return OMAP_DSS_CHANNEL_LCD
;
657 static int dpi_connect(struct omap_dss_device
*dssdev
,
658 struct omap_dss_device
*dst
)
660 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
661 enum omap_channel channel
= dpi
->output
.dispc_channel
;
664 r
= dpi_init_regulator(dpi
);
670 r
= dss_mgr_connect(channel
, dssdev
);
674 r
= omapdss_output_set_device(dssdev
, dst
);
676 DSSERR("failed to connect output to new device: %s\n",
678 dss_mgr_disconnect(channel
, dssdev
);
685 static void dpi_disconnect(struct omap_dss_device
*dssdev
,
686 struct omap_dss_device
*dst
)
688 struct dpi_data
*dpi
= dpi_get_data_from_dssdev(dssdev
);
689 enum omap_channel channel
= dpi
->output
.dispc_channel
;
691 WARN_ON(dst
!= dssdev
->dst
);
693 if (dst
!= dssdev
->dst
)
696 omapdss_output_unset_device(dssdev
);
698 dss_mgr_disconnect(channel
, dssdev
);
701 static const struct omapdss_dpi_ops dpi_ops
= {
702 .connect
= dpi_connect
,
703 .disconnect
= dpi_disconnect
,
705 .enable
= dpi_display_enable
,
706 .disable
= dpi_display_disable
,
708 .check_timings
= dpi_check_timings
,
709 .set_timings
= dpi_set_timings
,
710 .get_timings
= dpi_get_timings
,
713 static void dpi_init_output_port(struct dpi_data
*dpi
, struct device_node
*port
)
715 struct omap_dss_device
*out
= &dpi
->output
;
719 r
= of_property_read_u32(port
, "reg", &port_num
);
736 out
->dev
= &dpi
->pdev
->dev
;
737 out
->id
= OMAP_DSS_OUTPUT_DPI
;
738 out
->output_type
= OMAP_DISPLAY_TYPE_DPI
;
739 out
->dispc_channel
= dpi_get_channel(dpi
, port_num
);
740 out
->port_num
= port_num
;
741 out
->ops
.dpi
= &dpi_ops
;
742 out
->owner
= THIS_MODULE
;
744 omapdss_register_output(out
);
747 static void dpi_uninit_output_port(struct device_node
*port
)
749 struct dpi_data
*dpi
= port
->data
;
750 struct omap_dss_device
*out
= &dpi
->output
;
752 omapdss_unregister_output(out
);
755 int dpi_init_port(struct platform_device
*pdev
, struct device_node
*port
,
756 enum dss_model dss_model
)
758 struct dpi_data
*dpi
;
759 struct device_node
*ep
;
763 dpi
= devm_kzalloc(&pdev
->dev
, sizeof(*dpi
), GFP_KERNEL
);
767 ep
= of_get_next_child(port
, NULL
);
771 r
= of_property_read_u32(ep
, "data-lines", &datalines
);
773 DSSERR("failed to parse datalines\n");
777 dpi
->data_lines
= datalines
;
782 dpi
->dss_model
= dss_model
;
785 mutex_init(&dpi
->lock
);
787 dpi_init_output_port(dpi
, port
);
789 dpi
->port_initialized
= true;
799 void dpi_uninit_port(struct device_node
*port
)
801 struct dpi_data
*dpi
= port
->data
;
803 if (!dpi
->port_initialized
)
806 dpi_uninit_output_port(port
);