4 * Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
8 * Mythri pk <mythripk@ti.com>
10 * Heavily modified to use the linux CEC framework:
12 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
14 * This program is free software; you may redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
22 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
23 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
24 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include <linux/kernel.h>
29 #include <linux/err.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
36 #include "hdmi4_core.h"
37 #include "hdmi4_cec.h"
40 #define HDMI_CEC_DEV_ID 0x900
41 #define HDMI_CEC_SPEC 0x904
43 /* Not really a debug register, more a low-level control register */
44 #define HDMI_CEC_DBG_3 0x91C
45 #define HDMI_CEC_TX_INIT 0x920
46 #define HDMI_CEC_TX_DEST 0x924
47 #define HDMI_CEC_SETUP 0x938
48 #define HDMI_CEC_TX_COMMAND 0x93C
49 #define HDMI_CEC_TX_OPERAND 0x940
50 #define HDMI_CEC_TRANSMIT_DATA 0x97C
51 #define HDMI_CEC_CA_7_0 0x988
52 #define HDMI_CEC_CA_15_8 0x98C
53 #define HDMI_CEC_INT_STATUS_0 0x998
54 #define HDMI_CEC_INT_STATUS_1 0x99C
55 #define HDMI_CEC_INT_ENABLE_0 0x990
56 #define HDMI_CEC_INT_ENABLE_1 0x994
57 #define HDMI_CEC_RX_CONTROL 0x9B0
58 #define HDMI_CEC_RX_COUNT 0x9B4
59 #define HDMI_CEC_RX_CMD_HEADER 0x9B8
60 #define HDMI_CEC_RX_COMMAND 0x9BC
61 #define HDMI_CEC_RX_OPERAND 0x9C0
63 #define HDMI_CEC_TX_FIFO_INT_MASK 0x64
64 #define HDMI_CEC_RETRANSMIT_CNT_INT_MASK 0x2
66 #define HDMI_CORE_CEC_RETRY 200
68 static void hdmi_cec_received_msg(struct hdmi_core_data
*core
)
70 u32 cnt
= hdmi_read_reg(core
->base
, HDMI_CEC_RX_COUNT
) & 0xff;
72 /* While there are CEC frames in the FIFO */
74 /* and the frame doesn't have an error */
76 struct cec_msg msg
= {};
79 /* then read the message */
81 msg
.msg
[0] = hdmi_read_reg(core
->base
,
82 HDMI_CEC_RX_CMD_HEADER
);
83 msg
.msg
[1] = hdmi_read_reg(core
->base
,
85 for (i
= 0; i
< msg
.len
; i
++) {
86 unsigned int reg
= HDMI_CEC_RX_OPERAND
+ i
* 4;
89 hdmi_read_reg(core
->base
, reg
);
92 cec_received_msg(core
->adap
, &msg
);
94 /* Clear the current frame from the FIFO */
95 hdmi_write_reg(core
->base
, HDMI_CEC_RX_CONTROL
, 1);
96 /* Wait until the current frame is cleared */
97 while (hdmi_read_reg(core
->base
, HDMI_CEC_RX_CONTROL
) & 1)
100 * Re-read the count register and loop to see if there are
101 * more messages in the FIFO.
103 cnt
= hdmi_read_reg(core
->base
, HDMI_CEC_RX_COUNT
) & 0xff;
107 static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data
*core
, u32 stat1
)
110 u32 dbg3
= hdmi_read_reg(core
->base
, HDMI_CEC_DBG_3
);
112 cec_transmit_done(core
->adap
,
114 CEC_TX_STATUS_MAX_RETRIES
,
115 0, (dbg3
>> 4) & 7, 0, 0);
116 } else if (stat1
& 1) {
117 cec_transmit_done(core
->adap
,
118 CEC_TX_STATUS_ARB_LOST
|
119 CEC_TX_STATUS_MAX_RETRIES
,
121 } else if (stat1
== 0) {
122 cec_transmit_done(core
->adap
, CEC_TX_STATUS_OK
,
127 void hdmi4_cec_irq(struct hdmi_core_data
*core
)
129 u32 stat0
= hdmi_read_reg(core
->base
, HDMI_CEC_INT_STATUS_0
);
130 u32 stat1
= hdmi_read_reg(core
->base
, HDMI_CEC_INT_STATUS_1
);
132 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_0
, stat0
);
133 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_1
, stat1
);
136 REG_FLD_MOD(core
->base
, HDMI_CEC_DBG_3
, 0x1, 7, 7);
137 else if (stat0
& 0x24)
138 hdmi_cec_transmit_fifo_empty(core
, stat1
);
140 u32 dbg3
= hdmi_read_reg(core
->base
, HDMI_CEC_DBG_3
);
142 cec_transmit_done(core
->adap
,
144 CEC_TX_STATUS_MAX_RETRIES
,
145 0, (dbg3
>> 4) & 7, 0, 0);
146 } else if (stat1
& 1) {
147 cec_transmit_done(core
->adap
,
148 CEC_TX_STATUS_ARB_LOST
|
149 CEC_TX_STATUS_MAX_RETRIES
,
153 hdmi_cec_received_msg(core
);
155 REG_FLD_MOD(core
->base
, HDMI_CEC_DBG_3
, 0x1, 7, 7);
158 static bool hdmi_cec_clear_tx_fifo(struct cec_adapter
*adap
)
160 struct hdmi_core_data
*core
= cec_get_drvdata(adap
);
161 int retry
= HDMI_CORE_CEC_RETRY
;
164 REG_FLD_MOD(core
->base
, HDMI_CEC_DBG_3
, 0x1, 7, 7);
166 temp
= hdmi_read_reg(core
->base
, HDMI_CEC_DBG_3
);
167 if (FLD_GET(temp
, 7, 7) == 0)
174 static bool hdmi_cec_clear_rx_fifo(struct cec_adapter
*adap
)
176 struct hdmi_core_data
*core
= cec_get_drvdata(adap
);
177 int retry
= HDMI_CORE_CEC_RETRY
;
180 hdmi_write_reg(core
->base
, HDMI_CEC_RX_CONTROL
, 0x3);
181 retry
= HDMI_CORE_CEC_RETRY
;
183 temp
= hdmi_read_reg(core
->base
, HDMI_CEC_RX_CONTROL
);
184 if (FLD_GET(temp
, 1, 0) == 0)
191 static int hdmi_cec_adap_enable(struct cec_adapter
*adap
, bool enable
)
193 struct hdmi_core_data
*core
= cec_get_drvdata(adap
);
197 hdmi_write_reg(core
->base
, HDMI_CEC_INT_ENABLE_0
, 0);
198 hdmi_write_reg(core
->base
, HDMI_CEC_INT_ENABLE_1
, 0);
199 REG_FLD_MOD(core
->base
, HDMI_CORE_SYS_INTR_UNMASK4
, 0, 3, 3);
200 hdmi_wp_clear_irqenable(core
->wp
, HDMI_IRQ_CORE
);
201 hdmi_wp_set_irqstatus(core
->wp
, HDMI_IRQ_CORE
);
202 hdmi4_core_disable(NULL
);
205 err
= hdmi4_core_enable(NULL
);
210 if (!hdmi_cec_clear_tx_fifo(adap
)) {
211 pr_err("cec-%s: could not clear TX FIFO\n", adap
->name
);
216 if (!hdmi_cec_clear_rx_fifo(adap
)) {
217 pr_err("cec-%s: could not clear RX FIFO\n", adap
->name
);
221 /* Clear CEC interrupts */
222 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_1
,
223 hdmi_read_reg(core
->base
, HDMI_CEC_INT_STATUS_1
));
224 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_0
,
225 hdmi_read_reg(core
->base
, HDMI_CEC_INT_STATUS_0
));
227 /* Enable HDMI core interrupts */
228 hdmi_wp_set_irqenable(core
->wp
, HDMI_IRQ_CORE
);
229 /* Unmask CEC interrupt */
230 REG_FLD_MOD(core
->base
, HDMI_CORE_SYS_INTR_UNMASK4
, 0x1, 3, 3);
232 * Enable CEC interrupts:
233 * Transmit Buffer Full/Empty Change event
234 * Transmitter FIFO Empty event
235 * Receiver FIFO Not Empty event
237 hdmi_write_reg(core
->base
, HDMI_CEC_INT_ENABLE_0
, 0x26);
239 * Enable CEC interrupts:
240 * RX FIFO Overrun Error event
241 * Short Pulse Detected event
242 * Frame Retransmit Count Exceeded event
243 * Start Bit Irregularity event
245 hdmi_write_reg(core
->base
, HDMI_CEC_INT_ENABLE_1
, 0x0f);
247 /* cec calibration enable (self clearing) */
248 hdmi_write_reg(core
->base
, HDMI_CEC_SETUP
, 0x03);
250 hdmi_write_reg(core
->base
, HDMI_CEC_SETUP
, 0x04);
252 temp
= hdmi_read_reg(core
->base
, HDMI_CEC_SETUP
);
253 if (FLD_GET(temp
, 4, 4) != 0) {
254 temp
= FLD_MOD(temp
, 0, 4, 4);
255 hdmi_write_reg(core
->base
, HDMI_CEC_SETUP
, temp
);
258 * If we enabled CEC in middle of a CEC message on the bus,
259 * we could have start bit irregularity and/or short
260 * pulse event. Clear them now.
262 temp
= hdmi_read_reg(core
->base
, HDMI_CEC_INT_STATUS_1
);
263 temp
= FLD_MOD(0x0, 0x5, 2, 0);
264 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_1
, temp
);
269 static int hdmi_cec_adap_log_addr(struct cec_adapter
*adap
, u8 log_addr
)
271 struct hdmi_core_data
*core
= cec_get_drvdata(adap
);
274 if (log_addr
== CEC_LOG_ADDR_INVALID
) {
275 hdmi_write_reg(core
->base
, HDMI_CEC_CA_7_0
, 0);
276 hdmi_write_reg(core
->base
, HDMI_CEC_CA_15_8
, 0);
280 v
= hdmi_read_reg(core
->base
, HDMI_CEC_CA_7_0
);
282 hdmi_write_reg(core
->base
, HDMI_CEC_CA_7_0
, v
);
284 v
= hdmi_read_reg(core
->base
, HDMI_CEC_CA_15_8
);
285 v
|= 1 << (log_addr
- 8);
286 hdmi_write_reg(core
->base
, HDMI_CEC_CA_15_8
, v
);
291 static int hdmi_cec_adap_transmit(struct cec_adapter
*adap
, u8 attempts
,
292 u32 signal_free_time
, struct cec_msg
*msg
)
294 struct hdmi_core_data
*core
= cec_get_drvdata(adap
);
299 if (!hdmi_cec_clear_tx_fifo(adap
)) {
300 pr_err("cec-%s: could not clear TX FIFO for transmit\n",
305 /* Clear TX interrupts */
306 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_0
,
307 HDMI_CEC_TX_FIFO_INT_MASK
);
309 hdmi_write_reg(core
->base
, HDMI_CEC_INT_STATUS_1
,
310 HDMI_CEC_RETRANSMIT_CNT_INT_MASK
);
312 /* Set the retry count */
313 REG_FLD_MOD(core
->base
, HDMI_CEC_DBG_3
, attempts
- 1, 6, 4);
315 /* Set the initiator addresses */
316 hdmi_write_reg(core
->base
, HDMI_CEC_TX_INIT
, cec_msg_initiator(msg
));
318 /* Set destination id */
319 temp
= cec_msg_destination(msg
);
322 hdmi_write_reg(core
->base
, HDMI_CEC_TX_DEST
, temp
);
326 /* Setup command and arguments for the command */
327 hdmi_write_reg(core
->base
, HDMI_CEC_TX_COMMAND
, msg
->msg
[1]);
329 for (i
= 0; i
< msg
->len
- 2; i
++)
330 hdmi_write_reg(core
->base
, HDMI_CEC_TX_OPERAND
+ i
* 4,
334 hdmi_write_reg(core
->base
, HDMI_CEC_TRANSMIT_DATA
,
335 (msg
->len
- 2) | 0x10);
339 static const struct cec_adap_ops hdmi_cec_adap_ops
= {
340 .adap_enable
= hdmi_cec_adap_enable
,
341 .adap_log_addr
= hdmi_cec_adap_log_addr
,
342 .adap_transmit
= hdmi_cec_adap_transmit
,
345 void hdmi4_cec_set_phys_addr(struct hdmi_core_data
*core
, u16 pa
)
347 cec_s_phys_addr(core
->adap
, pa
, false);
350 int hdmi4_cec_init(struct platform_device
*pdev
, struct hdmi_core_data
*core
,
351 struct hdmi_wp_data
*wp
)
353 const u32 caps
= CEC_CAP_TRANSMIT
| CEC_CAP_LOG_ADDRS
|
354 CEC_CAP_PASSTHROUGH
| CEC_CAP_RC
;
357 core
->adap
= cec_allocate_adapter(&hdmi_cec_adap_ops
, core
,
358 "omap4", caps
, CEC_MAX_LOG_ADDRS
);
359 ret
= PTR_ERR_OR_ZERO(core
->adap
);
365 * Initialize CEC clock divider: CEC needs 2MHz clock hence
366 * set the devider to 24 to get 48/24=2MHz clock
368 REG_FLD_MOD(core
->wp
->base
, HDMI_WP_CLK
, 0x18, 5, 0);
370 ret
= cec_register_adapter(core
->adap
, &pdev
->dev
);
372 cec_delete_adapter(core
->adap
);
378 void hdmi4_cec_uninit(struct hdmi_core_data
*core
)
380 cec_unregister_adapter(core
->adap
);