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drm/omap: Replace struct omap_video_timings with videomode
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / hdmi5_core.c
1 /*
2 * OMAP5 HDMI CORE IP driver library
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/delay.h>
30 #include <linux/string.h>
31 #include <linux/seq_file.h>
32 #include <drm/drm_edid.h>
33 #include <sound/asound.h>
34 #include <sound/asoundef.h>
35
36 #include "hdmi5_core.h"
37
38 /* only 24 bit color depth used for now */
39 static const struct csc_table csc_table_deepcolor[] = {
40 /* HDMI_DEEP_COLOR_24BIT */
41 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
42 /* HDMI_DEEP_COLOR_30BIT */
43 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
44 /* HDMI_DEEP_COLOR_36BIT */
45 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
46 /* FULL RANGE */
47 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
48 };
49
50 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
51 {
52 void __iomem *base = core->base;
53 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
54 const unsigned ss_scl_high = 4600; /* ns */
55 const unsigned ss_scl_low = 5400; /* ns */
56 const unsigned fs_scl_high = 600; /* ns */
57 const unsigned fs_scl_low = 1300; /* ns */
58 const unsigned sda_hold = 1000; /* ns */
59 const unsigned sfr_div = 10;
60 unsigned long long sfr;
61 unsigned v;
62
63 sfr = iclk / sfr_div; /* SFR_DIV */
64 sfr /= 1000; /* SFR clock in kHz */
65
66 /* Reset */
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
68 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
69 0, 0, 1) != 1)
70 DSSERR("HDMI I2CM reset failed\n");
71
72 /* Standard (0) or Fast (1) Mode */
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
74
75 /* Standard Mode SCL High counter */
76 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
77 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
78 (v >> 8) & 0xff, 7, 0);
79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
80 v & 0xff, 7, 0);
81
82 /* Standard Mode SCL Low counter */
83 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
85 (v >> 8) & 0xff, 7, 0);
86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
87 v & 0xff, 7, 0);
88
89 /* Fast Mode SCL High Counter */
90 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
91 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
92 (v >> 8) & 0xff, 7, 0);
93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
94 v & 0xff, 7, 0);
95
96 /* Fast Mode SCL Low Counter */
97 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
98 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
99 (v >> 8) & 0xff, 7, 0);
100 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
101 v & 0xff, 7, 0);
102
103 /* SDA Hold Time */
104 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
105 REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
106
107 REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
108 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
109
110 /* NACK_POL to high */
111 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
112
113 /* NACK_MASK to unmasked */
114 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
115
116 /* ARBITRATION_POL to high */
117 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
118
119 /* ARBITRATION_MASK to unmasked */
120 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
121
122 /* DONE_POL to high */
123 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
124
125 /* DONE_MASK to unmasked */
126 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
127 }
128
129 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
130 {
131 void __iomem *base = core->base;
132
133 /* Mask I2C interrupts */
134 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
135 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
136 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
137 }
138
139 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
140 {
141 void __iomem *base = core->base;
142 u8 cur_addr;
143 char checksum = 0;
144 const int retries = 1000;
145 u8 seg_ptr = ext / 2;
146 u8 edidbase = ((ext % 2) * 0x80);
147
148 REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
149
150 /*
151 * TODO: We use polling here, although we probably should use proper
152 * interrupts.
153 */
154 for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
155 int i;
156
157 /* clear ERROR and DONE */
158 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
159
160 REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
161 edidbase + cur_addr, 7, 0);
162
163 if (seg_ptr)
164 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
165 else
166 REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
167
168 for (i = 0; i < retries; ++i) {
169 u32 stat;
170
171 stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
172
173 /* I2CM_ERROR */
174 if (stat & 1) {
175 DSSERR("HDMI I2C Master Error\n");
176 return -EIO;
177 }
178
179 /* I2CM_DONE */
180 if (stat & (1 << 1))
181 break;
182
183 usleep_range(250, 1000);
184 }
185
186 if (i == retries) {
187 DSSERR("HDMI I2C timeout reading EDID\n");
188 return -EIO;
189 }
190
191 pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
192 checksum += pedid[cur_addr];
193 }
194
195 return 0;
196
197 }
198
199 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
200 {
201 int r, n, i;
202 int max_ext_blocks = (len / 128) - 1;
203
204 if (len < 128)
205 return -EINVAL;
206
207 hdmi_core_ddc_init(core);
208
209 r = hdmi_core_ddc_edid(core, edid, 0);
210 if (r)
211 goto out;
212
213 n = edid[0x7e];
214
215 if (n > max_ext_blocks)
216 n = max_ext_blocks;
217
218 for (i = 1; i <= n; i++) {
219 r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
220 if (r)
221 goto out;
222 }
223
224 out:
225 hdmi_core_ddc_uninit(core);
226
227 return r ? r : len;
228 }
229
230 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
231 {
232
233 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
234 hdmi_read_reg(core->base, r))
235
236 DUMPCORE(HDMI_CORE_FC_INVIDCONF);
237 DUMPCORE(HDMI_CORE_FC_INHACTIV0);
238 DUMPCORE(HDMI_CORE_FC_INHACTIV1);
239 DUMPCORE(HDMI_CORE_FC_INHBLANK0);
240 DUMPCORE(HDMI_CORE_FC_INHBLANK1);
241 DUMPCORE(HDMI_CORE_FC_INVACTIV0);
242 DUMPCORE(HDMI_CORE_FC_INVACTIV1);
243 DUMPCORE(HDMI_CORE_FC_INVBLANK);
244 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
245 DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
246 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
247 DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
248 DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
249 DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
250 DUMPCORE(HDMI_CORE_FC_CTRLDUR);
251 DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
252 DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
253 DUMPCORE(HDMI_CORE_FC_CH0PREAM);
254 DUMPCORE(HDMI_CORE_FC_CH1PREAM);
255 DUMPCORE(HDMI_CORE_FC_CH2PREAM);
256 DUMPCORE(HDMI_CORE_FC_AVICONF0);
257 DUMPCORE(HDMI_CORE_FC_AVICONF1);
258 DUMPCORE(HDMI_CORE_FC_AVICONF2);
259 DUMPCORE(HDMI_CORE_FC_AVIVID);
260 DUMPCORE(HDMI_CORE_FC_PRCONF);
261
262 DUMPCORE(HDMI_CORE_MC_CLKDIS);
263 DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
264 DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
265 DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
266 DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
267
268 DUMPCORE(HDMI_CORE_I2CM_SLAVE);
269 DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
270 DUMPCORE(HDMI_CORE_I2CM_DATAO);
271 DUMPCORE(HDMI_CORE_I2CM_DATAI);
272 DUMPCORE(HDMI_CORE_I2CM_OPERATION);
273 DUMPCORE(HDMI_CORE_I2CM_INT);
274 DUMPCORE(HDMI_CORE_I2CM_CTLINT);
275 DUMPCORE(HDMI_CORE_I2CM_DIV);
276 DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
277 DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
278 DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
279 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
280 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
281 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
282 DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
283 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
284 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
285 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
286 DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
287 DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
288 }
289
290 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
291 struct hdmi_config *cfg)
292 {
293 DSSDBG("hdmi_core_init\n");
294
295 video_cfg->v_fc_config.timings = cfg->timings;
296
297 /* video core */
298 video_cfg->data_enable_pol = 1; /* It is always 1*/
299 video_cfg->hblank = cfg->timings.hfront_porch +
300 cfg->timings.hback_porch + cfg->timings.hsync_len;
301 video_cfg->vblank_osc = 0;
302 video_cfg->vblank = cfg->timings.vsync_len + cfg->timings.vfront_porch +
303 cfg->timings.vback_porch;
304 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
305
306 if (cfg->timings.flags & DISPLAY_FLAGS_INTERLACED) {
307 /* set vblank_osc if vblank is fractional */
308 if (video_cfg->vblank % 2 != 0)
309 video_cfg->vblank_osc = 1;
310
311 video_cfg->v_fc_config.timings.vactive /= 2;
312 video_cfg->vblank /= 2;
313 video_cfg->v_fc_config.timings.vfront_porch /= 2;
314 video_cfg->v_fc_config.timings.vsync_len /= 2;
315 video_cfg->v_fc_config.timings.vback_porch /= 2;
316 }
317
318 if (cfg->timings.flags & DISPLAY_FLAGS_DOUBLECLK) {
319 video_cfg->v_fc_config.timings.hactive *= 2;
320 video_cfg->hblank *= 2;
321 video_cfg->v_fc_config.timings.hfront_porch *= 2;
322 video_cfg->v_fc_config.timings.hsync_len *= 2;
323 video_cfg->v_fc_config.timings.hback_porch *= 2;
324 }
325 }
326
327 /* DSS_HDMI_CORE_VIDEO_CONFIG */
328 static void hdmi_core_video_config(struct hdmi_core_data *core,
329 struct hdmi_core_vid_config *cfg)
330 {
331 void __iomem *base = core->base;
332 struct videomode *ovt = &cfg->v_fc_config.timings;
333 unsigned char r = 0;
334 bool vsync_pol, hsync_pol;
335
336 vsync_pol = !!(ovt->flags & DISPLAY_FLAGS_VSYNC_HIGH);
337 hsync_pol = !!(ovt->flags & DISPLAY_FLAGS_HSYNC_HIGH);
338
339 /* Set hsync, vsync and data-enable polarity */
340 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
341 r = FLD_MOD(r, vsync_pol, 6, 6);
342 r = FLD_MOD(r, hsync_pol, 5, 5);
343 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
344 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
345 r = FLD_MOD(r, !!(ovt->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
346 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
347
348 /* set x resolution */
349 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, ovt->hactive >> 8, 4, 0);
350 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, ovt->hactive & 0xFF, 7, 0);
351
352 /* set y resolution */
353 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, ovt->vactive >> 8, 4, 0);
354 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, ovt->vactive & 0xFF, 7, 0);
355
356 /* set horizontal blanking pixels */
357 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
358 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
359
360 /* set vertial blanking pixels */
361 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
362
363 /* set horizontal sync offset */
364 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, ovt->hfront_porch >> 8,
365 4, 0);
366 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, ovt->hfront_porch & 0xFF,
367 7, 0);
368
369 /* set vertical sync offset */
370 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, ovt->vfront_porch, 7, 0);
371
372 /* set horizontal sync pulse width */
373 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (ovt->hsync_len >> 8),
374 1, 0);
375 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, ovt->hsync_len & 0xFF,
376 7, 0);
377
378 /* set vertical sync pulse width */
379 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, ovt->vsync_len, 5, 0);
380
381 /* select DVI mode */
382 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
383 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
384
385 if (ovt->flags & DISPLAY_FLAGS_DOUBLECLK)
386 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
387 else
388 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
389 }
390
391 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
392 {
393 void __iomem *base = core->base;
394 int clr_depth = 0; /* 24 bit color depth */
395
396 /* COLOR_DEPTH */
397 REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
398 /* BYPASS_EN */
399 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
400 /* PP_EN */
401 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
402 /* YCC422_EN */
403 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
404 /* PP_STUFFING */
405 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
406 /* YCC422_STUFFING */
407 REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
408 /* OUTPUT_SELECTOR */
409 REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
410 }
411
412 static void hdmi_core_config_csc(struct hdmi_core_data *core)
413 {
414 int clr_depth = 0; /* 24 bit color depth */
415
416 /* CSC_COLORDEPTH */
417 REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
418 }
419
420 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
421 {
422 int video_mapping = 1; /* for 24 bit color depth */
423
424 /* VIDEO_MAPPING */
425 REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
426 }
427
428 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
429 struct hdmi_avi_infoframe *frame)
430 {
431 void __iomem *base = core->base;
432 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
433 u8 *ptr;
434 unsigned y, a, b, s;
435 unsigned c, m, r;
436 unsigned itc, ec, q, sc;
437 unsigned vic;
438 unsigned yq, cn, pr;
439
440 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
441
442 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
443 HDMI_INFOFRAME_SIZE(AVI), false);
444
445 ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
446
447 y = (ptr[0] >> 5) & 0x3;
448 a = (ptr[0] >> 4) & 0x1;
449 b = (ptr[0] >> 2) & 0x3;
450 s = (ptr[0] >> 0) & 0x3;
451
452 c = (ptr[1] >> 6) & 0x3;
453 m = (ptr[1] >> 4) & 0x3;
454 r = (ptr[1] >> 0) & 0xf;
455
456 itc = (ptr[2] >> 7) & 0x1;
457 ec = (ptr[2] >> 4) & 0x7;
458 q = (ptr[2] >> 2) & 0x3;
459 sc = (ptr[2] >> 0) & 0x3;
460
461 vic = ptr[3];
462
463 yq = (ptr[4] >> 6) & 0x3;
464 cn = (ptr[4] >> 4) & 0x3;
465 pr = (ptr[4] >> 0) & 0xf;
466
467 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
468 (a << 6) | (s << 4) | (b << 2) | (y << 0));
469
470 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
471 (c << 6) | (m << 4) | (r << 0));
472
473 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
474 (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
475
476 hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
477
478 hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
479 (yq << 2) | (cn << 0));
480
481 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
482 }
483
484 static void hdmi_core_csc_config(struct hdmi_core_data *core,
485 struct csc_table csc_coeff)
486 {
487 void __iomem *base = core->base;
488
489 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
490 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
491 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
492 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
493 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
494 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
495 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
496 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
497 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
498 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
499 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
500 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
501 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
502 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
503 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
504 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
505 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
506 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
507 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
508 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
509 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
510 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
511 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
512 REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
513
514 REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
515 }
516
517 static void hdmi_core_configure_range(struct hdmi_core_data *core)
518 {
519 struct csc_table csc_coeff = { 0 };
520
521 /* support limited range with 24 bit color depth for now */
522 csc_coeff = csc_table_deepcolor[0];
523
524 hdmi_core_csc_config(core, csc_coeff);
525 }
526
527 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
528 {
529 void __iomem *base = core->base;
530
531 DSSDBG("hdmi_core_enable_video_path\n");
532
533 REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
534 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
535 REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
536 REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
537 REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
538 REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
539 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
540 REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
541 }
542
543 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
544 {
545 void __iomem *base = core->base;
546
547 /* Master IRQ mask */
548 REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
549
550 /* Mask all the interrupts in HDMI core */
551
552 REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
553 REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
554 REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
555 REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
556
557 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
558 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
559
560 REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
561
562 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
563 REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
564 REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
565
566 REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
567
568 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
569
570 /* Clear all the current interrupt bits */
571
572 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
573 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
574 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
575 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
576
577 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
578
579 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
580
581 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
582
583 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
584 }
585
586 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
587 {
588 /* Unmute interrupts */
589 REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
590 }
591
592 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
593 {
594 void __iomem *base = core->base;
595
596 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
597 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
598 REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
599 REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
600 REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
601 REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
602 REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
603 REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
604 REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
605
606 return 0;
607 }
608
609 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
610 struct hdmi_config *cfg)
611 {
612 struct videomode video_timing;
613 struct hdmi_video_format video_format;
614 struct hdmi_core_vid_config v_core_cfg;
615
616 hdmi_core_mask_interrupts(core);
617
618 hdmi_core_init(&v_core_cfg, cfg);
619
620 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
621
622 hdmi_wp_video_config_timing(wp, &video_timing);
623
624 /* video config */
625 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
626
627 hdmi_wp_video_config_format(wp, &video_format);
628
629 hdmi_wp_video_config_interface(wp, &video_timing);
630
631 /* support limited range with 24 bit color depth for now */
632 hdmi_core_configure_range(core);
633 cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
634
635 /*
636 * configure core video part, set software reset in the core
637 */
638 v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
639
640 hdmi_core_video_config(core, &v_core_cfg);
641
642 hdmi_core_config_video_packetizer(core);
643 hdmi_core_config_csc(core);
644 hdmi_core_config_video_sampler(core);
645
646 if (cfg->hdmi_dvi_mode == HDMI_HDMI)
647 hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
648
649 hdmi_core_enable_video_path(core);
650
651 hdmi_core_enable_interrupts(core);
652 }
653
654 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
655 struct hdmi_core_audio_config *cfg)
656 {
657 void __iomem *base = core->base;
658 u8 val;
659
660 /* Mute audio before configuring */
661 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
662
663 /* Set the N parameter */
664 REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
665 REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
666 REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
667
668 /*
669 * CTS manual mode. Automatic mode is not supported when using audio
670 * parallel interface.
671 */
672 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
673 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
674 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
675 REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
676
677 /* Layout of Audio Sample Packets: 2-channel or multichannels */
678 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
679 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
680 else
681 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
682
683 /* Configure IEC-609580 Validity bits */
684 /* Channel 0 is valid */
685 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
686 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
687
688 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
689 val = 1;
690 else
691 val = 0;
692
693 /* Channels 1, 2 setting */
694 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
695 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
696 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
697 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
698 /* Channel 3 setting */
699 if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
700 val = 1;
701 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
702 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
703
704 /* Configure IEC-60958 User bits */
705 /* TODO: should be set by user. */
706 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
707
708 /* Configure IEC-60958 Channel Status word */
709 /* CGMSA */
710 val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
711 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
712
713 /* Copyright */
714 val = (cfg->iec60958_cfg->status[0] &
715 IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
716 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
717
718 /* Category */
719 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
720 cfg->iec60958_cfg->status[1]);
721
722 /* PCM audio mode */
723 val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
724 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
725
726 /* Source number */
727 val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
728 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
729
730 /* Channel number right 0 */
731 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
732 /* Channel number right 1*/
733 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
734 /* Channel number right 2 */
735 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
736 /* Channel number right 3*/
737 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
738 /* Channel number left 0 */
739 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
740 /* Channel number left 1*/
741 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
742 /* Channel number left 2 */
743 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
744 /* Channel number left 3*/
745 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
746
747 /* Clock accuracy and sample rate */
748 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
749 cfg->iec60958_cfg->status[3]);
750
751 /* Original sample rate and word length */
752 hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
753 cfg->iec60958_cfg->status[4]);
754
755 /* Enable FIFO empty and full interrupts */
756 REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
757
758 /* Configure GPA */
759 /* select HBR/SPDIF interfaces */
760 if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
761 /* select HBR/SPDIF interfaces */
762 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
763 /* enable two channels in GPA */
764 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
765 } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
766 /* select HBR/SPDIF interfaces */
767 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
768 /* enable six channels in GPA */
769 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
770 } else {
771 /* select HBR/SPDIF interfaces */
772 REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
773 /* enable eight channels in GPA */
774 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
775 }
776
777 /* disable HBR */
778 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
779 /* enable PCUV */
780 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
781 /* enable GPA FIFO full and empty mask */
782 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
783 /* set polarity of GPA FIFO empty interrupts */
784 REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
785
786 /* unmute audio */
787 REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
788 }
789
790 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
791 struct snd_cea_861_aud_if *info_aud)
792 {
793 void __iomem *base = core->base;
794
795 /* channel count and coding type fields in AUDICONF0 are swapped */
796 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
797 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
798 (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
799
800 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
801 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
802 hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
803 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
804 (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
805 }
806
807 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
808 struct omap_dss_audio *audio, u32 pclk)
809 {
810 struct hdmi_audio_format audio_format;
811 struct hdmi_audio_dma audio_dma;
812 struct hdmi_core_audio_config core_cfg;
813 int err, n, cts, channel_count;
814 unsigned int fs_nr;
815 bool word_length_16b = false;
816
817 if (!audio || !audio->iec || !audio->cea || !core)
818 return -EINVAL;
819
820 core_cfg.iec60958_cfg = audio->iec;
821
822 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
823 (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
824 word_length_16b = true;
825
826 /* only 16-bit word length supported atm */
827 if (!word_length_16b)
828 return -EINVAL;
829
830 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
831 case IEC958_AES3_CON_FS_32000:
832 fs_nr = 32000;
833 break;
834 case IEC958_AES3_CON_FS_44100:
835 fs_nr = 44100;
836 break;
837 case IEC958_AES3_CON_FS_48000:
838 fs_nr = 48000;
839 break;
840 case IEC958_AES3_CON_FS_88200:
841 fs_nr = 88200;
842 break;
843 case IEC958_AES3_CON_FS_96000:
844 fs_nr = 96000;
845 break;
846 case IEC958_AES3_CON_FS_176400:
847 fs_nr = 176400;
848 break;
849 case IEC958_AES3_CON_FS_192000:
850 fs_nr = 192000;
851 break;
852 default:
853 return -EINVAL;
854 }
855
856 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
857 core_cfg.n = n;
858 core_cfg.cts = cts;
859
860 /* Audio channels settings */
861 channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
862 + 1;
863
864 if (channel_count == 2)
865 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
866 else if (channel_count == 6)
867 core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
868 else
869 core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
870
871 /* DMA settings */
872 if (word_length_16b)
873 audio_dma.transfer_size = 0x10;
874 else
875 audio_dma.transfer_size = 0x20;
876 audio_dma.block_size = 0xC0;
877 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
878 audio_dma.fifo_threshold = 0x20; /* in number of samples */
879
880 /* audio FIFO format settings for 16-bit samples*/
881 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
882 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
883 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
884 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
885
886 /* only LPCM atm */
887 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
888
889 /* only allowed option */
890 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
891
892 /* disable start/stop signals of IEC 60958 blocks */
893 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
894
895 /* configure DMA and audio FIFO format*/
896 hdmi_wp_audio_config_dma(wp, &audio_dma);
897 hdmi_wp_audio_config_format(wp, &audio_format);
898
899 /* configure the core */
900 hdmi5_core_audio_config(core, &core_cfg);
901
902 /* configure CEA 861 audio infoframe */
903 hdmi5_core_audio_infoframe_cfg(core, audio->cea);
904
905 return 0;
906 }
907
908 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
909 {
910 struct resource *res;
911
912 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
913 if (!res) {
914 DSSERR("can't get CORE IORESOURCE_MEM HDMI\n");
915 return -EINVAL;
916 }
917
918 core->base = devm_ioremap_resource(&pdev->dev, res);
919 if (IS_ERR(core->base)) {
920 DSSERR("can't ioremap HDMI core\n");
921 return PTR_ERR(core->base);
922 }
923
924 return 0;
925 }
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