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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / omapdrm / dss / omapdss.h
1 /*
2 * Copyright (C) 2016 Texas Instruments
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __OMAP_DRM_DSS_H
19 #define __OMAP_DRM_DSS_H
20
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25 #include <video/videomode.h>
26 #include <linux/platform_data/omapdss.h>
27 #include <uapi/drm/drm_mode.h>
28
29 #define DISPC_IRQ_FRAMEDONE (1 << 0)
30 #define DISPC_IRQ_VSYNC (1 << 1)
31 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
32 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
33 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
34 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
35 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
36 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
37 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
38 #define DISPC_IRQ_OCP_ERR (1 << 9)
39 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
40 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
41 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
42 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
43 #define DISPC_IRQ_SYNC_LOST (1 << 14)
44 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
45 #define DISPC_IRQ_WAKEUP (1 << 16)
46 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
47 #define DISPC_IRQ_VSYNC2 (1 << 18)
48 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
49 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
50 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
51 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
52 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
53 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
54 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
55 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
56 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
57 #define DISPC_IRQ_VSYNC3 (1 << 28)
58 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
59 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
60
61 struct omap_dss_device;
62 struct omap_overlay_manager;
63 struct dss_lcd_mgr_config;
64 struct snd_aes_iec958;
65 struct snd_cea_861_aud_if;
66 struct hdmi_avi_infoframe;
67
68 enum omap_display_type {
69 OMAP_DISPLAY_TYPE_NONE = 0,
70 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
71 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
72 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
73 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
74 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
75 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
76 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
77 };
78
79 enum omap_plane {
80 OMAP_DSS_GFX = 0,
81 OMAP_DSS_VIDEO1 = 1,
82 OMAP_DSS_VIDEO2 = 2,
83 OMAP_DSS_VIDEO3 = 3,
84 OMAP_DSS_WB = 4,
85 };
86
87 enum omap_channel {
88 OMAP_DSS_CHANNEL_LCD = 0,
89 OMAP_DSS_CHANNEL_DIGIT = 1,
90 OMAP_DSS_CHANNEL_LCD2 = 2,
91 OMAP_DSS_CHANNEL_LCD3 = 3,
92 OMAP_DSS_CHANNEL_WB = 4,
93 };
94
95 enum omap_color_mode {
96 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
97 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
98 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
99 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
100 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
101 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
102 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
103 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
104 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
105 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
106 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
107 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
108 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
109 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
110 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
111 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
112 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
113 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
114 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
115 };
116
117 enum omap_dss_load_mode {
118 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
119 OMAP_DSS_LOAD_CLUT_ONLY = 1,
120 OMAP_DSS_LOAD_FRAME_ONLY = 2,
121 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
122 };
123
124 enum omap_dss_trans_key_type {
125 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
126 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
127 };
128
129 enum omap_rfbi_te_mode {
130 OMAP_DSS_RFBI_TE_MODE_1 = 1,
131 OMAP_DSS_RFBI_TE_MODE_2 = 2,
132 };
133
134 enum omap_dss_signal_level {
135 OMAPDSS_SIG_ACTIVE_LOW,
136 OMAPDSS_SIG_ACTIVE_HIGH,
137 };
138
139 enum omap_dss_signal_edge {
140 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
141 OMAPDSS_DRIVE_SIG_RISING_EDGE,
142 };
143
144 enum omap_dss_venc_type {
145 OMAP_DSS_VENC_TYPE_COMPOSITE,
146 OMAP_DSS_VENC_TYPE_SVIDEO,
147 };
148
149 enum omap_dss_dsi_pixel_format {
150 OMAP_DSS_DSI_FMT_RGB888,
151 OMAP_DSS_DSI_FMT_RGB666,
152 OMAP_DSS_DSI_FMT_RGB666_PACKED,
153 OMAP_DSS_DSI_FMT_RGB565,
154 };
155
156 enum omap_dss_dsi_mode {
157 OMAP_DSS_DSI_CMD_MODE = 0,
158 OMAP_DSS_DSI_VIDEO_MODE,
159 };
160
161 enum omap_display_caps {
162 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
163 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
164 };
165
166 enum omap_dss_display_state {
167 OMAP_DSS_DISPLAY_DISABLED = 0,
168 OMAP_DSS_DISPLAY_ACTIVE,
169 };
170
171 enum omap_dss_rotation_type {
172 OMAP_DSS_ROT_DMA = 1 << 0,
173 OMAP_DSS_ROT_VRFB = 1 << 1,
174 OMAP_DSS_ROT_TILER = 1 << 2,
175 };
176
177 /* clockwise rotation angle */
178 enum omap_dss_rotation_angle {
179 OMAP_DSS_ROT_0 = 0,
180 OMAP_DSS_ROT_90 = 1,
181 OMAP_DSS_ROT_180 = 2,
182 OMAP_DSS_ROT_270 = 3,
183 };
184
185 enum omap_overlay_caps {
186 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
187 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
188 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
189 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
190 OMAP_DSS_OVL_CAP_POS = 1 << 4,
191 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
192 };
193
194 enum omap_overlay_manager_caps {
195 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
196 };
197
198 enum omap_dss_clk_source {
199 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
200 * OMAP4: DSS_FCLK */
201 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
202 * OMAP4: PLL1_CLK1 */
203 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
204 * OMAP4: PLL1_CLK2 */
205 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
206 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
207 };
208
209 enum omap_hdmi_flags {
210 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
211 };
212
213 enum omap_dss_output_id {
214 OMAP_DSS_OUTPUT_DPI = 1 << 0,
215 OMAP_DSS_OUTPUT_DBI = 1 << 1,
216 OMAP_DSS_OUTPUT_SDI = 1 << 2,
217 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
218 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
219 OMAP_DSS_OUTPUT_VENC = 1 << 5,
220 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
221 };
222
223 /* RFBI */
224
225 struct rfbi_timings {
226 int cs_on_time;
227 int cs_off_time;
228 int we_on_time;
229 int we_off_time;
230 int re_on_time;
231 int re_off_time;
232 int we_cycle_time;
233 int re_cycle_time;
234 int cs_pulse_width;
235 int access_time;
236
237 int clk_div;
238
239 u32 tim[5]; /* set by rfbi_convert_timings() */
240
241 int converted;
242 };
243
244 /* DSI */
245
246 enum omap_dss_dsi_trans_mode {
247 /* Sync Pulses: both sync start and end packets sent */
248 OMAP_DSS_DSI_PULSE_MODE,
249 /* Sync Events: only sync start packets sent */
250 OMAP_DSS_DSI_EVENT_MODE,
251 /* Burst: only sync start packets sent, pixels are time compressed */
252 OMAP_DSS_DSI_BURST_MODE,
253 };
254
255 struct omap_dss_dsi_videomode_timings {
256 unsigned long hsclk;
257
258 unsigned ndl;
259 unsigned bitspp;
260
261 /* pixels */
262 u16 hact;
263 /* lines */
264 u16 vact;
265
266 /* DSI video mode blanking data */
267 /* Unit: byte clock cycles */
268 u16 hss;
269 u16 hsa;
270 u16 hse;
271 u16 hfp;
272 u16 hbp;
273 /* Unit: line clocks */
274 u16 vsa;
275 u16 vfp;
276 u16 vbp;
277
278 /* DSI blanking modes */
279 int blanking_mode;
280 int hsa_blanking_mode;
281 int hbp_blanking_mode;
282 int hfp_blanking_mode;
283
284 enum omap_dss_dsi_trans_mode trans_mode;
285
286 bool ddr_clk_always_on;
287 int window_sync;
288 };
289
290 struct omap_dss_dsi_config {
291 enum omap_dss_dsi_mode mode;
292 enum omap_dss_dsi_pixel_format pixel_format;
293 const struct videomode *vm;
294
295 unsigned long hs_clk_min, hs_clk_max;
296 unsigned long lp_clk_min, lp_clk_max;
297
298 bool ddr_clk_always_on;
299 enum omap_dss_dsi_trans_mode trans_mode;
300 };
301
302 /* Hardcoded videomodes for tv. Venc only uses these to
303 * identify the mode, and does not actually use the configs
304 * itself. However, the configs should be something that
305 * a normal monitor can also show */
306 extern const struct videomode omap_dss_pal_vm;
307 extern const struct videomode omap_dss_ntsc_vm;
308
309 struct omap_dss_cpr_coefs {
310 s16 rr, rg, rb;
311 s16 gr, gg, gb;
312 s16 br, bg, bb;
313 };
314
315 struct omap_overlay_info {
316 dma_addr_t paddr;
317 dma_addr_t p_uv_addr; /* for NV12 format */
318 u16 screen_width;
319 u16 width;
320 u16 height;
321 enum omap_color_mode color_mode;
322 u8 rotation;
323 enum omap_dss_rotation_type rotation_type;
324 bool mirror;
325
326 u16 pos_x;
327 u16 pos_y;
328 u16 out_width; /* if 0, out_width == width */
329 u16 out_height; /* if 0, out_height == height */
330 u8 global_alpha;
331 u8 pre_mult_alpha;
332 u8 zorder;
333 };
334
335 struct omap_overlay {
336 struct kobject kobj;
337 struct list_head list;
338
339 /* static fields */
340 const char *name;
341 enum omap_plane id;
342 enum omap_color_mode supported_modes;
343 enum omap_overlay_caps caps;
344
345 /* dynamic fields */
346 struct omap_overlay_manager *manager;
347
348 /*
349 * The following functions do not block:
350 *
351 * is_enabled
352 * set_overlay_info
353 * get_overlay_info
354 *
355 * The rest of the functions may block and cannot be called from
356 * interrupt context
357 */
358
359 int (*enable)(struct omap_overlay *ovl);
360 int (*disable)(struct omap_overlay *ovl);
361 bool (*is_enabled)(struct omap_overlay *ovl);
362
363 int (*set_manager)(struct omap_overlay *ovl,
364 struct omap_overlay_manager *mgr);
365 int (*unset_manager)(struct omap_overlay *ovl);
366
367 int (*set_overlay_info)(struct omap_overlay *ovl,
368 struct omap_overlay_info *info);
369 void (*get_overlay_info)(struct omap_overlay *ovl,
370 struct omap_overlay_info *info);
371
372 int (*wait_for_go)(struct omap_overlay *ovl);
373
374 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
375 };
376
377 struct omap_overlay_manager_info {
378 u32 default_color;
379
380 enum omap_dss_trans_key_type trans_key_type;
381 u32 trans_key;
382 bool trans_enabled;
383
384 bool partial_alpha_enabled;
385
386 bool cpr_enable;
387 struct omap_dss_cpr_coefs cpr_coefs;
388 };
389
390 struct omap_overlay_manager {
391 struct kobject kobj;
392
393 /* static fields */
394 const char *name;
395 enum omap_channel id;
396 enum omap_overlay_manager_caps caps;
397 struct list_head overlays;
398 enum omap_display_type supported_displays;
399 enum omap_dss_output_id supported_outputs;
400
401 /* dynamic fields */
402 struct omap_dss_device *output;
403
404 /*
405 * The following functions do not block:
406 *
407 * set_manager_info
408 * get_manager_info
409 * apply
410 *
411 * The rest of the functions may block and cannot be called from
412 * interrupt context
413 */
414
415 int (*set_output)(struct omap_overlay_manager *mgr,
416 struct omap_dss_device *output);
417 int (*unset_output)(struct omap_overlay_manager *mgr);
418
419 int (*set_manager_info)(struct omap_overlay_manager *mgr,
420 struct omap_overlay_manager_info *info);
421 void (*get_manager_info)(struct omap_overlay_manager *mgr,
422 struct omap_overlay_manager_info *info);
423
424 int (*apply)(struct omap_overlay_manager *mgr);
425 int (*wait_for_go)(struct omap_overlay_manager *mgr);
426 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
427
428 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
429 };
430
431 /* 22 pins means 1 clk lane and 10 data lanes */
432 #define OMAP_DSS_MAX_DSI_PINS 22
433
434 struct omap_dsi_pin_config {
435 int num_pins;
436 /*
437 * pin numbers in the following order:
438 * clk+, clk-
439 * data1+, data1-
440 * data2+, data2-
441 * ...
442 */
443 int pins[OMAP_DSS_MAX_DSI_PINS];
444 };
445
446 struct omap_dss_writeback_info {
447 u32 paddr;
448 u32 p_uv_addr;
449 u16 buf_width;
450 u16 width;
451 u16 height;
452 enum omap_color_mode color_mode;
453 u8 rotation;
454 enum omap_dss_rotation_type rotation_type;
455 bool mirror;
456 u8 pre_mult_alpha;
457 };
458
459 struct omapdss_dpi_ops {
460 int (*connect)(struct omap_dss_device *dssdev,
461 struct omap_dss_device *dst);
462 void (*disconnect)(struct omap_dss_device *dssdev,
463 struct omap_dss_device *dst);
464
465 int (*enable)(struct omap_dss_device *dssdev);
466 void (*disable)(struct omap_dss_device *dssdev);
467
468 int (*check_timings)(struct omap_dss_device *dssdev,
469 struct videomode *vm);
470 void (*set_timings)(struct omap_dss_device *dssdev,
471 struct videomode *vm);
472 void (*get_timings)(struct omap_dss_device *dssdev,
473 struct videomode *vm);
474
475 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
476 };
477
478 struct omapdss_sdi_ops {
479 int (*connect)(struct omap_dss_device *dssdev,
480 struct omap_dss_device *dst);
481 void (*disconnect)(struct omap_dss_device *dssdev,
482 struct omap_dss_device *dst);
483
484 int (*enable)(struct omap_dss_device *dssdev);
485 void (*disable)(struct omap_dss_device *dssdev);
486
487 int (*check_timings)(struct omap_dss_device *dssdev,
488 struct videomode *vm);
489 void (*set_timings)(struct omap_dss_device *dssdev,
490 struct videomode *vm);
491 void (*get_timings)(struct omap_dss_device *dssdev,
492 struct videomode *vm);
493
494 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
495 };
496
497 struct omapdss_dvi_ops {
498 int (*connect)(struct omap_dss_device *dssdev,
499 struct omap_dss_device *dst);
500 void (*disconnect)(struct omap_dss_device *dssdev,
501 struct omap_dss_device *dst);
502
503 int (*enable)(struct omap_dss_device *dssdev);
504 void (*disable)(struct omap_dss_device *dssdev);
505
506 int (*check_timings)(struct omap_dss_device *dssdev,
507 struct videomode *vm);
508 void (*set_timings)(struct omap_dss_device *dssdev,
509 struct videomode *vm);
510 void (*get_timings)(struct omap_dss_device *dssdev,
511 struct videomode *vm);
512 };
513
514 struct omapdss_atv_ops {
515 int (*connect)(struct omap_dss_device *dssdev,
516 struct omap_dss_device *dst);
517 void (*disconnect)(struct omap_dss_device *dssdev,
518 struct omap_dss_device *dst);
519
520 int (*enable)(struct omap_dss_device *dssdev);
521 void (*disable)(struct omap_dss_device *dssdev);
522
523 int (*check_timings)(struct omap_dss_device *dssdev,
524 struct videomode *vm);
525 void (*set_timings)(struct omap_dss_device *dssdev,
526 struct videomode *vm);
527 void (*get_timings)(struct omap_dss_device *dssdev,
528 struct videomode *vm);
529
530 void (*set_type)(struct omap_dss_device *dssdev,
531 enum omap_dss_venc_type type);
532 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
533 bool invert_polarity);
534
535 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
536 u32 (*get_wss)(struct omap_dss_device *dssdev);
537 };
538
539 struct omapdss_hdmi_ops {
540 int (*connect)(struct omap_dss_device *dssdev,
541 struct omap_dss_device *dst);
542 void (*disconnect)(struct omap_dss_device *dssdev,
543 struct omap_dss_device *dst);
544
545 int (*enable)(struct omap_dss_device *dssdev);
546 void (*disable)(struct omap_dss_device *dssdev);
547
548 int (*check_timings)(struct omap_dss_device *dssdev,
549 struct videomode *vm);
550 void (*set_timings)(struct omap_dss_device *dssdev,
551 struct videomode *vm);
552 void (*get_timings)(struct omap_dss_device *dssdev,
553 struct videomode *vm);
554
555 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
556 bool (*detect)(struct omap_dss_device *dssdev);
557
558 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
559 int (*set_infoframe)(struct omap_dss_device *dssdev,
560 const struct hdmi_avi_infoframe *avi);
561 };
562
563 struct omapdss_dsi_ops {
564 int (*connect)(struct omap_dss_device *dssdev,
565 struct omap_dss_device *dst);
566 void (*disconnect)(struct omap_dss_device *dssdev,
567 struct omap_dss_device *dst);
568
569 int (*enable)(struct omap_dss_device *dssdev);
570 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
571 bool enter_ulps);
572
573 /* bus configuration */
574 int (*set_config)(struct omap_dss_device *dssdev,
575 const struct omap_dss_dsi_config *cfg);
576 int (*configure_pins)(struct omap_dss_device *dssdev,
577 const struct omap_dsi_pin_config *pin_cfg);
578
579 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
580 bool enable);
581 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
582
583 int (*update)(struct omap_dss_device *dssdev, int channel,
584 void (*callback)(int, void *), void *data);
585
586 void (*bus_lock)(struct omap_dss_device *dssdev);
587 void (*bus_unlock)(struct omap_dss_device *dssdev);
588
589 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
590 void (*disable_video_output)(struct omap_dss_device *dssdev,
591 int channel);
592
593 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
594 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
595 int vc_id);
596 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
597
598 /* data transfer */
599 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
600 u8 *data, int len);
601 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
602 u8 *data, int len);
603 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
604 u8 *data, int len);
605
606 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
607 u8 *data, int len);
608 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
609 u8 *data, int len);
610 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
611 u8 *reqdata, int reqlen,
612 u8 *data, int len);
613
614 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
615
616 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
617 int channel, u16 plen);
618 };
619
620 struct omap_dss_device {
621 struct kobject kobj;
622 struct device *dev;
623
624 struct module *owner;
625
626 struct list_head panel_list;
627
628 /* alias in the form of "display%d" */
629 char alias[16];
630
631 enum omap_display_type type;
632 enum omap_display_type output_type;
633
634 union {
635 struct {
636 u8 data_lines;
637 } dpi;
638
639 struct {
640 u8 channel;
641 u8 data_lines;
642 } rfbi;
643
644 struct {
645 u8 datapairs;
646 } sdi;
647
648 struct {
649 int module;
650 } dsi;
651
652 struct {
653 enum omap_dss_venc_type type;
654 bool invert_polarity;
655 } venc;
656 } phy;
657
658 struct {
659 struct videomode vm;
660
661 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
662 enum omap_dss_dsi_mode dsi_mode;
663 } panel;
664
665 struct {
666 u8 pixel_size;
667 struct rfbi_timings rfbi_timings;
668 } ctrl;
669
670 const char *name;
671
672 /* used to match device to driver */
673 const char *driver_name;
674
675 void *data;
676
677 struct omap_dss_driver *driver;
678
679 union {
680 const struct omapdss_dpi_ops *dpi;
681 const struct omapdss_sdi_ops *sdi;
682 const struct omapdss_dvi_ops *dvi;
683 const struct omapdss_hdmi_ops *hdmi;
684 const struct omapdss_atv_ops *atv;
685 const struct omapdss_dsi_ops *dsi;
686 } ops;
687
688 /* helper variable for driver suspend/resume */
689 bool activate_after_resume;
690
691 enum omap_display_caps caps;
692
693 struct omap_dss_device *src;
694
695 enum omap_dss_display_state state;
696
697 /* OMAP DSS output specific fields */
698
699 struct list_head list;
700
701 /* DISPC channel for this output */
702 enum omap_channel dispc_channel;
703 bool dispc_channel_connected;
704
705 /* output instance */
706 enum omap_dss_output_id id;
707
708 /* the port number in the DT node */
709 int port_num;
710
711 /* dynamic fields */
712 struct omap_overlay_manager *manager;
713
714 struct omap_dss_device *dst;
715 };
716
717 struct omap_dss_driver {
718 int (*probe)(struct omap_dss_device *);
719 void (*remove)(struct omap_dss_device *);
720
721 int (*connect)(struct omap_dss_device *dssdev);
722 void (*disconnect)(struct omap_dss_device *dssdev);
723
724 int (*enable)(struct omap_dss_device *display);
725 void (*disable)(struct omap_dss_device *display);
726 int (*run_test)(struct omap_dss_device *display, int test);
727
728 int (*update)(struct omap_dss_device *dssdev,
729 u16 x, u16 y, u16 w, u16 h);
730 int (*sync)(struct omap_dss_device *dssdev);
731
732 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
733 int (*get_te)(struct omap_dss_device *dssdev);
734
735 u8 (*get_rotate)(struct omap_dss_device *dssdev);
736 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
737
738 bool (*get_mirror)(struct omap_dss_device *dssdev);
739 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
740
741 int (*memory_read)(struct omap_dss_device *dssdev,
742 void *buf, size_t size,
743 u16 x, u16 y, u16 w, u16 h);
744
745 void (*get_resolution)(struct omap_dss_device *dssdev,
746 u16 *xres, u16 *yres);
747 void (*get_dimensions)(struct omap_dss_device *dssdev,
748 u32 *width, u32 *height);
749 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
750
751 int (*check_timings)(struct omap_dss_device *dssdev,
752 struct videomode *vm);
753 void (*set_timings)(struct omap_dss_device *dssdev,
754 struct videomode *vm);
755 void (*get_timings)(struct omap_dss_device *dssdev,
756 struct videomode *vm);
757
758 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
759 u32 (*get_wss)(struct omap_dss_device *dssdev);
760
761 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
762 bool (*detect)(struct omap_dss_device *dssdev);
763
764 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
765 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
766 const struct hdmi_avi_infoframe *avi);
767 };
768
769 enum omapdss_version omapdss_get_version(void);
770 bool omapdss_is_initialized(void);
771
772 int omap_dss_register_driver(struct omap_dss_driver *);
773 void omap_dss_unregister_driver(struct omap_dss_driver *);
774
775 int omapdss_register_display(struct omap_dss_device *dssdev);
776 void omapdss_unregister_display(struct omap_dss_device *dssdev);
777
778 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
779 void omap_dss_put_device(struct omap_dss_device *dssdev);
780 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
781 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
782 struct omap_dss_device *omap_dss_find_device(void *data,
783 int (*match)(struct omap_dss_device *dssdev, void *data));
784 const char *omapdss_get_default_display_name(void);
785
786 int dss_feat_get_num_mgrs(void);
787 int dss_feat_get_num_ovls(void);
788 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
789
790
791
792 int omap_dss_get_num_overlay_managers(void);
793 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
794
795 int omap_dss_get_num_overlays(void);
796 struct omap_overlay *omap_dss_get_overlay(int num);
797
798 int omapdss_register_output(struct omap_dss_device *output);
799 void omapdss_unregister_output(struct omap_dss_device *output);
800 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
801 struct omap_dss_device *omap_dss_find_output(const char *name);
802 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
803 int omapdss_output_set_device(struct omap_dss_device *out,
804 struct omap_dss_device *dssdev);
805 int omapdss_output_unset_device(struct omap_dss_device *out);
806
807 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
808 struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
809
810 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
811 u16 *xres, u16 *yres);
812 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
813 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
814 struct videomode *vm);
815
816 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
817 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
818 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
819
820 int omapdss_compat_init(void);
821 void omapdss_compat_uninit(void);
822
823 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
824 {
825 return dssdev->src;
826 }
827
828 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
829 {
830 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
831 }
832
833 struct device_node *
834 omapdss_of_get_next_port(const struct device_node *parent,
835 struct device_node *prev);
836
837 struct device_node *
838 omapdss_of_get_next_endpoint(const struct device_node *parent,
839 struct device_node *prev);
840
841 struct device_node *
842 omapdss_of_get_first_endpoint(const struct device_node *parent);
843
844 struct omap_dss_device *
845 omapdss_of_find_source_for_first_ep(struct device_node *node);
846
847 void omapdss_set_is_initialized(bool set);
848
849 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
850 u32 dss_of_port_get_port_number(struct device_node *port);
851
852 struct dss_mgr_ops {
853 int (*connect)(enum omap_channel channel,
854 struct omap_dss_device *dst);
855 void (*disconnect)(enum omap_channel channel,
856 struct omap_dss_device *dst);
857
858 void (*start_update)(enum omap_channel channel);
859 int (*enable)(enum omap_channel channel);
860 void (*disable)(enum omap_channel channel);
861 void (*set_timings)(enum omap_channel channel,
862 const struct videomode *vm);
863 void (*set_lcd_config)(enum omap_channel channel,
864 const struct dss_lcd_mgr_config *config);
865 int (*register_framedone_handler)(enum omap_channel channel,
866 void (*handler)(void *), void *data);
867 void (*unregister_framedone_handler)(enum omap_channel channel,
868 void (*handler)(void *), void *data);
869 };
870
871 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
872 void dss_uninstall_mgr_ops(void);
873
874 int dss_mgr_connect(enum omap_channel channel,
875 struct omap_dss_device *dst);
876 void dss_mgr_disconnect(enum omap_channel channel,
877 struct omap_dss_device *dst);
878 void dss_mgr_set_timings(enum omap_channel channel,
879 const struct videomode *vm);
880 void dss_mgr_set_lcd_config(enum omap_channel channel,
881 const struct dss_lcd_mgr_config *config);
882 int dss_mgr_enable(enum omap_channel channel);
883 void dss_mgr_disable(enum omap_channel channel);
884 void dss_mgr_start_update(enum omap_channel channel);
885 int dss_mgr_register_framedone_handler(enum omap_channel channel,
886 void (*handler)(void *), void *data);
887 void dss_mgr_unregister_framedone_handler(enum omap_channel channel,
888 void (*handler)(void *), void *data);
889
890 /* dispc ops */
891
892 struct dispc_ops {
893 u32 (*read_irqstatus)(void);
894 void (*clear_irqstatus)(u32 mask);
895 u32 (*read_irqenable)(void);
896 void (*write_irqenable)(u32 mask);
897
898 int (*request_irq)(irq_handler_t handler, void *dev_id);
899 void (*free_irq)(void *dev_id);
900
901 int (*runtime_get)(void);
902 void (*runtime_put)(void);
903
904 int (*get_num_ovls)(void);
905 int (*get_num_mgrs)(void);
906
907 void (*mgr_enable)(enum omap_channel channel, bool enable);
908 bool (*mgr_is_enabled)(enum omap_channel channel);
909 u32 (*mgr_get_vsync_irq)(enum omap_channel channel);
910 u32 (*mgr_get_framedone_irq)(enum omap_channel channel);
911 u32 (*mgr_get_sync_lost_irq)(enum omap_channel channel);
912 bool (*mgr_go_busy)(enum omap_channel channel);
913 void (*mgr_go)(enum omap_channel channel);
914 void (*mgr_set_lcd_config)(enum omap_channel channel,
915 const struct dss_lcd_mgr_config *config);
916 void (*mgr_set_timings)(enum omap_channel channel,
917 const struct videomode *vm);
918 void (*mgr_setup)(enum omap_channel channel,
919 const struct omap_overlay_manager_info *info);
920 enum omap_dss_output_id (*mgr_get_supported_outputs)(enum omap_channel channel);
921 u32 (*mgr_gamma_size)(enum omap_channel channel);
922 void (*mgr_set_gamma)(enum omap_channel channel,
923 const struct drm_color_lut *lut,
924 unsigned int length);
925
926 int (*ovl_enable)(enum omap_plane plane, bool enable);
927 bool (*ovl_enabled)(enum omap_plane plane);
928 void (*ovl_set_channel_out)(enum omap_plane plane,
929 enum omap_channel channel);
930 int (*ovl_setup)(enum omap_plane plane, const struct omap_overlay_info *oi,
931 const struct videomode *vm, bool mem_to_mem);
932
933 enum omap_color_mode (*ovl_get_color_modes)(enum omap_plane plane);
934 };
935
936 void dispc_set_ops(const struct dispc_ops *o);
937 const struct dispc_ops *dispc_get_ops(void);
938
939 #endif /* __OMAP_DRM_DSS_H */
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