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git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/gpu/drm/omapdrm/dss/pll.c
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #define DSS_SUBSYS_NAME "PLL"
19 #include <linux/delay.h>
20 #include <linux/clk.h>
22 #include <linux/kernel.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sched.h>
29 #define PLL_CONTROL 0x0000
30 #define PLL_STATUS 0x0004
32 #define PLL_CONFIGURATION1 0x000C
33 #define PLL_CONFIGURATION2 0x0010
34 #define PLL_CONFIGURATION3 0x0014
35 #define PLL_SSC_CONFIGURATION1 0x0018
36 #define PLL_SSC_CONFIGURATION2 0x001C
37 #define PLL_CONFIGURATION4 0x0020
39 int dss_pll_register(struct dss_device
*dss
, struct dss_pll
*pll
)
43 for (i
= 0; i
< ARRAY_SIZE(dss
->plls
); ++i
) {
54 void dss_pll_unregister(struct dss_pll
*pll
)
56 struct dss_device
*dss
= pll
->dss
;
59 for (i
= 0; i
< ARRAY_SIZE(dss
->plls
); ++i
) {
60 if (dss
->plls
[i
] == pll
) {
68 struct dss_pll
*dss_pll_find(struct dss_device
*dss
, const char *name
)
72 for (i
= 0; i
< ARRAY_SIZE(dss
->plls
); ++i
) {
73 if (dss
->plls
[i
] && strcmp(dss
->plls
[i
]->name
, name
) == 0)
80 struct dss_pll
*dss_pll_find_by_src(struct dss_device
*dss
,
81 enum dss_clk_source src
)
90 case DSS_CLK_SRC_HDMI_PLL
:
91 return dss_pll_find(dss
, "hdmi");
93 case DSS_CLK_SRC_PLL1_1
:
94 case DSS_CLK_SRC_PLL1_2
:
95 case DSS_CLK_SRC_PLL1_3
:
96 pll
= dss_pll_find(dss
, "dsi0");
98 pll
= dss_pll_find(dss
, "video0");
101 case DSS_CLK_SRC_PLL2_1
:
102 case DSS_CLK_SRC_PLL2_2
:
103 case DSS_CLK_SRC_PLL2_3
:
104 pll
= dss_pll_find(dss
, "dsi1");
106 pll
= dss_pll_find(dss
, "video1");
111 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src
)
114 case DSS_CLK_SRC_HDMI_PLL
:
117 case DSS_CLK_SRC_PLL1_1
:
118 case DSS_CLK_SRC_PLL2_1
:
121 case DSS_CLK_SRC_PLL1_2
:
122 case DSS_CLK_SRC_PLL2_2
:
125 case DSS_CLK_SRC_PLL1_3
:
126 case DSS_CLK_SRC_PLL2_3
:
134 int dss_pll_enable(struct dss_pll
*pll
)
138 r
= clk_prepare_enable(pll
->clkin
);
142 if (pll
->regulator
) {
143 r
= regulator_enable(pll
->regulator
);
148 r
= pll
->ops
->enable(pll
);
156 regulator_disable(pll
->regulator
);
158 clk_disable_unprepare(pll
->clkin
);
162 void dss_pll_disable(struct dss_pll
*pll
)
164 pll
->ops
->disable(pll
);
167 regulator_disable(pll
->regulator
);
169 clk_disable_unprepare(pll
->clkin
);
171 memset(&pll
->cinfo
, 0, sizeof(pll
->cinfo
));
174 int dss_pll_set_config(struct dss_pll
*pll
, const struct dss_pll_clock_info
*cinfo
)
178 r
= pll
->ops
->set_config(pll
, cinfo
);
187 bool dss_pll_hsdiv_calc_a(const struct dss_pll
*pll
, unsigned long clkdco
,
188 unsigned long out_min
, unsigned long out_max
,
189 dss_hsdiv_calc_func func
, void *data
)
191 const struct dss_pll_hw
*hw
= pll
->hw
;
192 int m
, m_start
, m_stop
;
195 out_min
= out_min
? out_min
: 1;
196 out_max
= out_max
? out_max
: ULONG_MAX
;
198 m_start
= max(DIV_ROUND_UP(clkdco
, out_max
), 1ul);
200 m_stop
= min((unsigned)(clkdco
/ out_min
), hw
->mX_max
);
202 for (m
= m_start
; m
<= m_stop
; ++m
) {
205 if (func(m
, out
, data
))
213 * clkdco = clkin / n * m * 2
214 * clkoutX = clkdco / mX
216 bool dss_pll_calc_a(const struct dss_pll
*pll
, unsigned long clkin
,
217 unsigned long pll_min
, unsigned long pll_max
,
218 dss_pll_calc_func func
, void *data
)
220 const struct dss_pll_hw
*hw
= pll
->hw
;
221 int n
, n_start
, n_stop
, n_inc
;
222 int m
, m_start
, m_stop
, m_inc
;
223 unsigned long fint
, clkdco
;
224 unsigned long pll_hw_max
;
225 unsigned long fint_hw_min
, fint_hw_max
;
227 pll_hw_max
= hw
->clkdco_max
;
229 fint_hw_min
= hw
->fint_min
;
230 fint_hw_max
= hw
->fint_max
;
232 n_start
= max(DIV_ROUND_UP(clkin
, fint_hw_max
), 1ul);
233 n_stop
= min((unsigned)(clkin
/ fint_hw_min
), hw
->n_max
);
236 if (hw
->errata_i886
) {
237 swap(n_start
, n_stop
);
241 pll_max
= pll_max
? pll_max
: ULONG_MAX
;
243 for (n
= n_start
; n
!= n_stop
; n
+= n_inc
) {
246 m_start
= max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min
, fint
), 2),
248 m_stop
= min3((unsigned)(pll_max
/ fint
/ 2),
249 (unsigned)(pll_hw_max
/ fint
/ 2),
253 if (hw
->errata_i886
) {
254 swap(m_start
, m_stop
);
258 for (m
= m_start
; m
!= m_stop
; m
+= m_inc
) {
259 clkdco
= 2 * m
* fint
;
261 if (func(n
, m
, fint
, clkdco
, data
))
270 * This calculates a PLL config that will provide the target_clkout rate
271 * for clkout. Additionally clkdco rate will be the same as clkout rate
272 * when clkout rate is >= min_clkdco.
274 * clkdco = clkin / n * m + clkin / n * mf / 262144
275 * clkout = clkdco / m2
277 bool dss_pll_calc_b(const struct dss_pll
*pll
, unsigned long clkin
,
278 unsigned long target_clkout
, struct dss_pll_clock_info
*cinfo
)
280 unsigned long fint
, clkdco
, clkout
;
281 unsigned long target_clkdco
;
282 unsigned long min_dco
;
283 unsigned int n
, m
, mf
, m2
, sd
;
284 const struct dss_pll_hw
*hw
= pll
->hw
;
286 DSSDBG("clkin %lu, target clkout %lu\n", clkin
, target_clkout
);
289 n
= DIV_ROUND_UP(clkin
, hw
->fint_max
);
292 /* adjust m2 so that the clkdco will be high enough */
293 min_dco
= roundup(hw
->clkdco_min
, fint
);
294 m2
= DIV_ROUND_UP(min_dco
, target_clkout
);
298 target_clkdco
= target_clkout
* m2
;
299 m
= target_clkdco
/ fint
;
303 /* adjust clkdco with fractional mf */
304 if (WARN_ON(target_clkdco
- clkdco
> fint
))
307 mf
= (u32
)div_u64(262144ull * (target_clkdco
- clkdco
), fint
);
310 clkdco
+= (u32
)div_u64((u64
)mf
* fint
, 262144);
312 clkout
= clkdco
/ m2
;
315 sd
= DIV_ROUND_UP(fint
* m
, 250000000);
317 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
319 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint
, clkdco
, clkout
);
328 cinfo
->clkdco
= clkdco
;
329 cinfo
->clkout
[0] = clkout
;
334 static int wait_for_bit_change(void __iomem
*reg
, int bitnum
, int value
)
336 unsigned long timeout
;
340 /* first busyloop to see if the bit changes right away */
343 if (FLD_GET(readl_relaxed(reg
), bitnum
, bitnum
) == value
)
347 /* then loop for 500ms, sleeping for 1ms in between */
348 timeout
= jiffies
+ msecs_to_jiffies(500);
349 while (time_before(jiffies
, timeout
)) {
350 if (FLD_GET(readl_relaxed(reg
), bitnum
, bitnum
) == value
)
353 wait
= ns_to_ktime(1000 * 1000);
354 set_current_state(TASK_UNINTERRUPTIBLE
);
355 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
361 int dss_pll_wait_reset_done(struct dss_pll
*pll
)
363 void __iomem
*base
= pll
->base
;
365 if (wait_for_bit_change(base
+ PLL_STATUS
, 0, 1) != 1)
371 static int dss_wait_hsdiv_ack(struct dss_pll
*pll
, u32 hsdiv_ack_mask
)
376 u32 v
= readl_relaxed(pll
->base
+ PLL_STATUS
);
378 if (v
== hsdiv_ack_mask
)
385 static bool pll_is_locked(u32 stat
)
388 * Required value for each bitfield listed below
390 * PLL_STATUS[6] = 0 PLL_BYPASS
391 * PLL_STATUS[5] = 0 PLL_HIGHJITTER
393 * PLL_STATUS[3] = 0 PLL_LOSSREF
394 * PLL_STATUS[2] = 0 PLL_RECAL
395 * PLL_STATUS[1] = 1 PLL_LOCK
396 * PLL_STATUS[0] = 1 PLL_CTRL_RESET_DONE
398 return ((stat
& 0x6f) == 0x3);
401 int dss_pll_write_config_type_a(struct dss_pll
*pll
,
402 const struct dss_pll_clock_info
*cinfo
)
404 const struct dss_pll_hw
*hw
= pll
->hw
;
405 void __iomem
*base
= pll
->base
;
410 if (hw
->has_stopmode
)
411 l
= FLD_MOD(l
, 1, 0, 0); /* PLL_STOPMODE */
412 l
= FLD_MOD(l
, cinfo
->n
- 1, hw
->n_msb
, hw
->n_lsb
); /* PLL_REGN */
413 l
= FLD_MOD(l
, cinfo
->m
, hw
->m_msb
, hw
->m_lsb
); /* PLL_REGM */
415 l
= FLD_MOD(l
, cinfo
->mX
[0] ? cinfo
->mX
[0] - 1 : 0,
416 hw
->mX_msb
[0], hw
->mX_lsb
[0]);
418 l
= FLD_MOD(l
, cinfo
->mX
[1] ? cinfo
->mX
[1] - 1 : 0,
419 hw
->mX_msb
[1], hw
->mX_lsb
[1]);
420 writel_relaxed(l
, base
+ PLL_CONFIGURATION1
);
424 l
= FLD_MOD(l
, cinfo
->mX
[2] ? cinfo
->mX
[2] - 1 : 0,
425 hw
->mX_msb
[2], hw
->mX_lsb
[2]);
427 l
= FLD_MOD(l
, cinfo
->mX
[3] ? cinfo
->mX
[3] - 1 : 0,
428 hw
->mX_msb
[3], hw
->mX_lsb
[3]);
429 writel_relaxed(l
, base
+ PLL_CONFIGURATION3
);
431 l
= readl_relaxed(base
+ PLL_CONFIGURATION2
);
432 if (hw
->has_freqsel
) {
433 u32 f
= cinfo
->fint
< 1000000 ? 0x3 :
434 cinfo
->fint
< 1250000 ? 0x4 :
435 cinfo
->fint
< 1500000 ? 0x5 :
436 cinfo
->fint
< 1750000 ? 0x6 :
439 l
= FLD_MOD(l
, f
, 4, 1); /* PLL_FREQSEL */
440 } else if (hw
->has_selfreqdco
) {
441 u32 f
= cinfo
->clkdco
< hw
->clkdco_low
? 0x2 : 0x4;
443 l
= FLD_MOD(l
, f
, 3, 1); /* PLL_SELFREQDCO */
445 l
= FLD_MOD(l
, 1, 13, 13); /* PLL_REFEN */
446 l
= FLD_MOD(l
, 0, 14, 14); /* PHY_CLKINEN */
447 l
= FLD_MOD(l
, 0, 16, 16); /* M4_CLOCK_EN */
448 l
= FLD_MOD(l
, 0, 18, 18); /* M5_CLOCK_EN */
449 l
= FLD_MOD(l
, 1, 20, 20); /* HSDIVBYPASS */
451 l
= FLD_MOD(l
, 3, 22, 21); /* REFSEL = sysclk */
452 l
= FLD_MOD(l
, 0, 23, 23); /* M6_CLOCK_EN */
453 l
= FLD_MOD(l
, 0, 25, 25); /* M7_CLOCK_EN */
454 writel_relaxed(l
, base
+ PLL_CONFIGURATION2
);
456 if (hw
->errata_i932
) {
459 const u32 max_lock_retries
= 20;
462 * Calculate wait time for PLL LOCK
463 * 1000 REFCLK cycles in us.
465 sleep_time
= DIV_ROUND_UP(1000*1000*1000, cinfo
->fint
);
467 for (cnt
= 0; cnt
< max_lock_retries
; cnt
++) {
468 writel_relaxed(1, base
+ PLL_GO
); /* PLL_GO */
471 * read the register back to ensure the write is
474 readl_relaxed(base
+ PLL_GO
);
476 usleep_range(sleep_time
, sleep_time
+ 5);
477 l
= readl_relaxed(base
+ PLL_STATUS
);
479 if (pll_is_locked(l
) &&
480 !(readl_relaxed(base
+ PLL_GO
) & 0x1))
485 if (cnt
== max_lock_retries
) {
486 DSSERR("cannot lock PLL\n");
491 writel_relaxed(1, base
+ PLL_GO
); /* PLL_GO */
493 if (wait_for_bit_change(base
+ PLL_GO
, 0, 0) != 0) {
494 DSSERR("DSS DPLL GO bit not going down.\n");
499 if (wait_for_bit_change(base
+ PLL_STATUS
, 1, 1) != 1) {
500 DSSERR("cannot lock DSS DPLL\n");
506 l
= readl_relaxed(base
+ PLL_CONFIGURATION2
);
507 l
= FLD_MOD(l
, 1, 14, 14); /* PHY_CLKINEN */
508 l
= FLD_MOD(l
, cinfo
->mX
[0] ? 1 : 0, 16, 16); /* M4_CLOCK_EN */
509 l
= FLD_MOD(l
, cinfo
->mX
[1] ? 1 : 0, 18, 18); /* M5_CLOCK_EN */
510 l
= FLD_MOD(l
, 0, 20, 20); /* HSDIVBYPASS */
511 l
= FLD_MOD(l
, cinfo
->mX
[2] ? 1 : 0, 23, 23); /* M6_CLOCK_EN */
512 l
= FLD_MOD(l
, cinfo
->mX
[3] ? 1 : 0, 25, 25); /* M7_CLOCK_EN */
513 writel_relaxed(l
, base
+ PLL_CONFIGURATION2
);
515 r
= dss_wait_hsdiv_ack(pll
,
516 (cinfo
->mX
[0] ? BIT(7) : 0) |
517 (cinfo
->mX
[1] ? BIT(8) : 0) |
518 (cinfo
->mX
[2] ? BIT(10) : 0) |
519 (cinfo
->mX
[3] ? BIT(11) : 0));
521 DSSERR("failed to enable HSDIV clocks\n");
529 int dss_pll_write_config_type_b(struct dss_pll
*pll
,
530 const struct dss_pll_clock_info
*cinfo
)
532 const struct dss_pll_hw
*hw
= pll
->hw
;
533 void __iomem
*base
= pll
->base
;
537 l
= FLD_MOD(l
, cinfo
->m
, 20, 9); /* PLL_REGM */
538 l
= FLD_MOD(l
, cinfo
->n
- 1, 8, 1); /* PLL_REGN */
539 writel_relaxed(l
, base
+ PLL_CONFIGURATION1
);
541 l
= readl_relaxed(base
+ PLL_CONFIGURATION2
);
542 l
= FLD_MOD(l
, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
543 l
= FLD_MOD(l
, 0x1, 13, 13); /* PLL_REFEN */
544 l
= FLD_MOD(l
, 0x0, 14, 14); /* PHY_CLKINEN */
546 l
= FLD_MOD(l
, 0x3, 22, 21); /* REFSEL = SYSCLK */
549 if (cinfo
->clkdco
> hw
->clkdco_low
)
550 l
= FLD_MOD(l
, 0x4, 3, 1);
552 l
= FLD_MOD(l
, 0x2, 3, 1);
553 writel_relaxed(l
, base
+ PLL_CONFIGURATION2
);
555 l
= readl_relaxed(base
+ PLL_CONFIGURATION3
);
556 l
= FLD_MOD(l
, cinfo
->sd
, 17, 10); /* PLL_REGSD */
557 writel_relaxed(l
, base
+ PLL_CONFIGURATION3
);
559 l
= readl_relaxed(base
+ PLL_CONFIGURATION4
);
560 l
= FLD_MOD(l
, cinfo
->mX
[0], 24, 18); /* PLL_REGM2 */
561 l
= FLD_MOD(l
, cinfo
->mf
, 17, 0); /* PLL_REGM_F */
562 writel_relaxed(l
, base
+ PLL_CONFIGURATION4
);
564 writel_relaxed(1, base
+ PLL_GO
); /* PLL_GO */
566 if (wait_for_bit_change(base
+ PLL_GO
, 0, 0) != 0) {
567 DSSERR("DSS DPLL GO bit not going down.\n");
571 if (wait_for_bit_change(base
+ PLL_STATUS
, 1, 1) != 1) {
572 DSSERR("cannot lock DSS DPLL\n");