2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/iopoll.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
58 const struct drm_display_mode
*modes
;
59 unsigned int num_modes
;
60 const struct display_timing
*timings
;
61 unsigned int num_timings
;
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
89 unsigned int hpd_absent_delay
;
92 unsigned int unprepare
;
100 struct panel_simple
{
101 struct drm_panel base
;
106 const struct panel_desc
*desc
;
108 struct regulator
*supply
;
109 struct i2c_adapter
*ddc
;
111 struct gpio_desc
*enable_gpio
;
112 struct gpio_desc
*hpd_gpio
;
114 struct drm_display_mode override_mode
;
117 static inline struct panel_simple
*to_panel_simple(struct drm_panel
*panel
)
119 return container_of(panel
, struct panel_simple
, base
);
122 static unsigned int panel_simple_get_timings_modes(struct panel_simple
*panel
,
123 struct drm_connector
*connector
)
125 struct drm_display_mode
*mode
;
126 unsigned int i
, num
= 0;
128 for (i
= 0; i
< panel
->desc
->num_timings
; i
++) {
129 const struct display_timing
*dt
= &panel
->desc
->timings
[i
];
132 videomode_from_timing(dt
, &vm
);
133 mode
= drm_mode_create(connector
->dev
);
135 dev_err(panel
->base
.dev
, "failed to add mode %ux%u\n",
136 dt
->hactive
.typ
, dt
->vactive
.typ
);
140 drm_display_mode_from_videomode(&vm
, mode
);
142 mode
->type
|= DRM_MODE_TYPE_DRIVER
;
144 if (panel
->desc
->num_timings
== 1)
145 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
147 drm_mode_probed_add(connector
, mode
);
154 static unsigned int panel_simple_get_display_modes(struct panel_simple
*panel
,
155 struct drm_connector
*connector
)
157 struct drm_display_mode
*mode
;
158 unsigned int i
, num
= 0;
160 for (i
= 0; i
< panel
->desc
->num_modes
; i
++) {
161 const struct drm_display_mode
*m
= &panel
->desc
->modes
[i
];
163 mode
= drm_mode_duplicate(connector
->dev
, m
);
165 dev_err(panel
->base
.dev
, "failed to add mode %ux%u@%u\n",
166 m
->hdisplay
, m
->vdisplay
, m
->vrefresh
);
170 mode
->type
|= DRM_MODE_TYPE_DRIVER
;
172 if (panel
->desc
->num_modes
== 1)
173 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
175 drm_mode_set_name(mode
);
177 drm_mode_probed_add(connector
, mode
);
184 static int panel_simple_get_non_edid_modes(struct panel_simple
*panel
,
185 struct drm_connector
*connector
)
187 struct drm_display_mode
*mode
;
188 bool has_override
= panel
->override_mode
.type
;
189 unsigned int num
= 0;
195 mode
= drm_mode_duplicate(connector
->dev
,
196 &panel
->override_mode
);
198 drm_mode_probed_add(connector
, mode
);
201 dev_err(panel
->base
.dev
, "failed to add override mode\n");
205 /* Only add timings if override was not there or failed to validate */
206 if (num
== 0 && panel
->desc
->num_timings
)
207 num
= panel_simple_get_timings_modes(panel
, connector
);
210 * Only add fixed modes if timings/override added no mode.
212 * We should only ever have either the display timings specified
213 * or a fixed mode. Anything else is rather bogus.
215 WARN_ON(panel
->desc
->num_timings
&& panel
->desc
->num_modes
);
217 num
= panel_simple_get_display_modes(panel
, connector
);
219 connector
->display_info
.bpc
= panel
->desc
->bpc
;
220 connector
->display_info
.width_mm
= panel
->desc
->size
.width
;
221 connector
->display_info
.height_mm
= panel
->desc
->size
.height
;
222 if (panel
->desc
->bus_format
)
223 drm_display_info_set_bus_formats(&connector
->display_info
,
224 &panel
->desc
->bus_format
, 1);
225 connector
->display_info
.bus_flags
= panel
->desc
->bus_flags
;
230 static int panel_simple_disable(struct drm_panel
*panel
)
232 struct panel_simple
*p
= to_panel_simple(panel
);
237 if (p
->desc
->delay
.disable
)
238 msleep(p
->desc
->delay
.disable
);
245 static int panel_simple_unprepare(struct drm_panel
*panel
)
247 struct panel_simple
*p
= to_panel_simple(panel
);
252 gpiod_set_value_cansleep(p
->enable_gpio
, 0);
254 regulator_disable(p
->supply
);
256 if (p
->desc
->delay
.unprepare
)
257 msleep(p
->desc
->delay
.unprepare
);
264 static int panel_simple_get_hpd_gpio(struct device
*dev
,
265 struct panel_simple
*p
, bool from_probe
)
269 p
->hpd_gpio
= devm_gpiod_get_optional(dev
, "hpd", GPIOD_IN
);
270 if (IS_ERR(p
->hpd_gpio
)) {
271 err
= PTR_ERR(p
->hpd_gpio
);
274 * If we're called from probe we won't consider '-EPROBE_DEFER'
275 * to be an error--we'll leave the error code in "hpd_gpio".
276 * When we try to use it we'll try again. This allows for
277 * circular dependencies where the component providing the
278 * hpd gpio needs the panel to init before probing.
280 if (err
!= -EPROBE_DEFER
|| !from_probe
) {
281 dev_err(dev
, "failed to get 'hpd' GPIO: %d\n", err
);
289 static int panel_simple_prepare(struct drm_panel
*panel
)
291 struct panel_simple
*p
= to_panel_simple(panel
);
299 err
= regulator_enable(p
->supply
);
301 dev_err(panel
->dev
, "failed to enable supply: %d\n", err
);
305 gpiod_set_value_cansleep(p
->enable_gpio
, 1);
307 delay
= p
->desc
->delay
.prepare
;
309 delay
+= p
->desc
->delay
.hpd_absent_delay
;
314 if (IS_ERR(p
->hpd_gpio
)) {
315 err
= panel_simple_get_hpd_gpio(panel
->dev
, p
, false);
320 err
= readx_poll_timeout(gpiod_get_value_cansleep
, p
->hpd_gpio
,
321 hpd_asserted
, hpd_asserted
,
323 if (hpd_asserted
< 0)
328 "error waiting for hpd GPIO: %d\n", err
);
338 static int panel_simple_enable(struct drm_panel
*panel
)
340 struct panel_simple
*p
= to_panel_simple(panel
);
345 if (p
->desc
->delay
.enable
)
346 msleep(p
->desc
->delay
.enable
);
353 static int panel_simple_get_modes(struct drm_panel
*panel
,
354 struct drm_connector
*connector
)
356 struct panel_simple
*p
= to_panel_simple(panel
);
359 /* probe EDID if a DDC bus is available */
361 struct edid
*edid
= drm_get_edid(connector
, p
->ddc
);
363 drm_connector_update_edid_property(connector
, edid
);
365 num
+= drm_add_edid_modes(connector
, edid
);
370 /* add hard-coded panel modes */
371 num
+= panel_simple_get_non_edid_modes(p
, connector
);
376 static int panel_simple_get_timings(struct drm_panel
*panel
,
377 unsigned int num_timings
,
378 struct display_timing
*timings
)
380 struct panel_simple
*p
= to_panel_simple(panel
);
383 if (p
->desc
->num_timings
< num_timings
)
384 num_timings
= p
->desc
->num_timings
;
387 for (i
= 0; i
< num_timings
; i
++)
388 timings
[i
] = p
->desc
->timings
[i
];
390 return p
->desc
->num_timings
;
393 static const struct drm_panel_funcs panel_simple_funcs
= {
394 .disable
= panel_simple_disable
,
395 .unprepare
= panel_simple_unprepare
,
396 .prepare
= panel_simple_prepare
,
397 .enable
= panel_simple_enable
,
398 .get_modes
= panel_simple_get_modes
,
399 .get_timings
= panel_simple_get_timings
,
402 static struct panel_desc panel_dpi
;
404 static int panel_dpi_probe(struct device
*dev
,
405 struct panel_simple
*panel
)
407 struct display_timing
*timing
;
408 const struct device_node
*np
;
409 struct panel_desc
*desc
;
410 unsigned int bus_flags
;
415 desc
= devm_kzalloc(dev
, sizeof(*desc
), GFP_KERNEL
);
419 timing
= devm_kzalloc(dev
, sizeof(*timing
), GFP_KERNEL
);
423 ret
= of_get_display_timing(np
, "panel-timing", timing
);
425 dev_err(dev
, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
430 desc
->timings
= timing
;
431 desc
->num_timings
= 1;
433 of_property_read_u32(np
, "width-mm", &desc
->size
.width
);
434 of_property_read_u32(np
, "height-mm", &desc
->size
.height
);
436 /* Extract bus_flags from display_timing */
438 vm
.flags
= timing
->flags
;
439 drm_bus_flags_from_videomode(&vm
, &bus_flags
);
440 desc
->bus_flags
= bus_flags
;
442 /* We do not know the connector for the DT node, so guess it */
443 desc
->connector_type
= DRM_MODE_CONNECTOR_DPI
;
450 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
451 (to_check->field.typ >= bounds->field.min && \
452 to_check->field.typ <= bounds->field.max)
453 static void panel_simple_parse_panel_timing_node(struct device
*dev
,
454 struct panel_simple
*panel
,
455 const struct display_timing
*ot
)
457 const struct panel_desc
*desc
= panel
->desc
;
461 if (WARN_ON(desc
->num_modes
)) {
462 dev_err(dev
, "Reject override mode: panel has a fixed mode\n");
465 if (WARN_ON(!desc
->num_timings
)) {
466 dev_err(dev
, "Reject override mode: no timings specified\n");
470 for (i
= 0; i
< panel
->desc
->num_timings
; i
++) {
471 const struct display_timing
*dt
= &panel
->desc
->timings
[i
];
473 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, hactive
) ||
474 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, hfront_porch
) ||
475 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, hback_porch
) ||
476 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, hsync_len
) ||
477 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, vactive
) ||
478 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, vfront_porch
) ||
479 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, vback_porch
) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot
, dt
, vsync_len
))
483 if (ot
->flags
!= dt
->flags
)
486 videomode_from_timing(ot
, &vm
);
487 drm_display_mode_from_videomode(&vm
, &panel
->override_mode
);
488 panel
->override_mode
.type
|= DRM_MODE_TYPE_DRIVER
|
489 DRM_MODE_TYPE_PREFERRED
;
493 if (WARN_ON(!panel
->override_mode
.type
))
494 dev_err(dev
, "Reject override mode: No display_timing found\n");
497 static int panel_simple_probe(struct device
*dev
, const struct panel_desc
*desc
)
499 struct panel_simple
*panel
;
500 struct display_timing dt
;
501 struct device_node
*ddc
;
504 panel
= devm_kzalloc(dev
, sizeof(*panel
), GFP_KERNEL
);
508 panel
->enabled
= false;
509 panel
->prepared
= false;
512 panel
->no_hpd
= of_property_read_bool(dev
->of_node
, "no-hpd");
513 if (!panel
->no_hpd
) {
514 err
= panel_simple_get_hpd_gpio(dev
, panel
, true);
519 panel
->supply
= devm_regulator_get(dev
, "power");
520 if (IS_ERR(panel
->supply
))
521 return PTR_ERR(panel
->supply
);
523 panel
->enable_gpio
= devm_gpiod_get_optional(dev
, "enable",
525 if (IS_ERR(panel
->enable_gpio
)) {
526 err
= PTR_ERR(panel
->enable_gpio
);
527 if (err
!= -EPROBE_DEFER
)
528 dev_err(dev
, "failed to request GPIO: %d\n", err
);
532 ddc
= of_parse_phandle(dev
->of_node
, "ddc-i2c-bus", 0);
534 panel
->ddc
= of_find_i2c_adapter_by_node(ddc
);
538 return -EPROBE_DEFER
;
541 if (desc
== &panel_dpi
) {
542 /* Handle the generic panel-dpi binding */
543 err
= panel_dpi_probe(dev
, panel
);
547 if (!of_get_display_timing(dev
->of_node
, "panel-timing", &dt
))
548 panel_simple_parse_panel_timing_node(dev
, panel
, &dt
);
551 drm_panel_init(&panel
->base
, dev
, &panel_simple_funcs
,
552 desc
->connector_type
);
554 err
= drm_panel_of_backlight(&panel
->base
);
558 err
= drm_panel_add(&panel
->base
);
562 dev_set_drvdata(dev
, panel
);
568 put_device(&panel
->ddc
->dev
);
573 static int panel_simple_remove(struct device
*dev
)
575 struct panel_simple
*panel
= dev_get_drvdata(dev
);
577 drm_panel_remove(&panel
->base
);
578 drm_panel_disable(&panel
->base
);
579 drm_panel_unprepare(&panel
->base
);
582 put_device(&panel
->ddc
->dev
);
587 static void panel_simple_shutdown(struct device
*dev
)
589 struct panel_simple
*panel
= dev_get_drvdata(dev
);
591 drm_panel_disable(&panel
->base
);
592 drm_panel_unprepare(&panel
->base
);
595 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode
= {
598 .hsync_start
= 480 + 2,
599 .hsync_end
= 480 + 2 + 41,
600 .htotal
= 480 + 2 + 41 + 2,
602 .vsync_start
= 272 + 2,
603 .vsync_end
= 272 + 2 + 10,
604 .vtotal
= 272 + 2 + 10 + 2,
606 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
609 static const struct panel_desc ampire_am_480272h3tmqw_t01h
= {
610 .modes
= &ire_am_480272h3tmqw_t01h_mode
,
617 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
620 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode
= {
623 .hsync_start
= 800 + 0,
624 .hsync_end
= 800 + 0 + 255,
625 .htotal
= 800 + 0 + 255 + 0,
627 .vsync_start
= 480 + 2,
628 .vsync_end
= 480 + 2 + 45,
629 .vtotal
= 480 + 2 + 45 + 0,
631 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
634 static const struct panel_desc ampire_am800480r3tmqwa1h
= {
635 .modes
= &ire_am800480r3tmqwa1h_mode
,
642 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
645 static const struct display_timing santek_st0700i5y_rbslw_f_timing
= {
646 .pixelclock
= { 26400000, 33300000, 46800000 },
647 .hactive
= { 800, 800, 800 },
648 .hfront_porch
= { 16, 210, 354 },
649 .hback_porch
= { 45, 36, 6 },
650 .hsync_len
= { 1, 10, 40 },
651 .vactive
= { 480, 480, 480 },
652 .vfront_porch
= { 7, 22, 147 },
653 .vback_porch
= { 22, 13, 3 },
654 .vsync_len
= { 1, 10, 20 },
655 .flags
= DISPLAY_FLAGS_HSYNC_LOW
| DISPLAY_FLAGS_VSYNC_LOW
|
656 DISPLAY_FLAGS_DE_HIGH
| DISPLAY_FLAGS_PIXDATA_POSEDGE
659 static const struct panel_desc armadeus_st0700_adapt
= {
660 .timings
= &santek_st0700i5y_rbslw_f_timing
,
667 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
668 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_POSEDGE
,
671 static const struct drm_display_mode auo_b101aw03_mode
= {
674 .hsync_start
= 1024 + 156,
675 .hsync_end
= 1024 + 156 + 8,
676 .htotal
= 1024 + 156 + 8 + 156,
678 .vsync_start
= 600 + 16,
679 .vsync_end
= 600 + 16 + 6,
680 .vtotal
= 600 + 16 + 6 + 16,
684 static const struct panel_desc auo_b101aw03
= {
685 .modes
= &auo_b101aw03_mode
,
694 static const struct display_timing auo_b101ean01_timing
= {
695 .pixelclock
= { 65300000, 72500000, 75000000 },
696 .hactive
= { 1280, 1280, 1280 },
697 .hfront_porch
= { 18, 119, 119 },
698 .hback_porch
= { 21, 21, 21 },
699 .hsync_len
= { 32, 32, 32 },
700 .vactive
= { 800, 800, 800 },
701 .vfront_porch
= { 4, 4, 4 },
702 .vback_porch
= { 8, 8, 8 },
703 .vsync_len
= { 18, 20, 20 },
706 static const struct panel_desc auo_b101ean01
= {
707 .timings
= &auo_b101ean01_timing
,
716 static const struct drm_display_mode auo_b101xtn01_mode
= {
719 .hsync_start
= 1366 + 20,
720 .hsync_end
= 1366 + 20 + 70,
721 .htotal
= 1366 + 20 + 70,
723 .vsync_start
= 768 + 14,
724 .vsync_end
= 768 + 14 + 42,
725 .vtotal
= 768 + 14 + 42,
727 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
730 static const struct panel_desc auo_b101xtn01
= {
731 .modes
= &auo_b101xtn01_mode
,
740 static const struct drm_display_mode auo_b116xak01_mode
= {
743 .hsync_start
= 1366 + 48,
744 .hsync_end
= 1366 + 48 + 32,
745 .htotal
= 1366 + 48 + 32 + 10,
747 .vsync_start
= 768 + 4,
748 .vsync_end
= 768 + 4 + 6,
749 .vtotal
= 768 + 4 + 6 + 15,
751 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
754 static const struct panel_desc auo_b116xak01
= {
755 .modes
= &auo_b116xak01_mode
,
763 .hpd_absent_delay
= 200,
765 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
766 .connector_type
= DRM_MODE_CONNECTOR_eDP
,
769 static const struct drm_display_mode auo_b116xw03_mode
= {
772 .hsync_start
= 1366 + 40,
773 .hsync_end
= 1366 + 40 + 40,
774 .htotal
= 1366 + 40 + 40 + 32,
776 .vsync_start
= 768 + 10,
777 .vsync_end
= 768 + 10 + 12,
778 .vtotal
= 768 + 10 + 12 + 6,
782 static const struct panel_desc auo_b116xw03
= {
783 .modes
= &auo_b116xw03_mode
,
792 static const struct drm_display_mode auo_b133xtn01_mode
= {
795 .hsync_start
= 1366 + 48,
796 .hsync_end
= 1366 + 48 + 32,
797 .htotal
= 1366 + 48 + 32 + 20,
799 .vsync_start
= 768 + 3,
800 .vsync_end
= 768 + 3 + 6,
801 .vtotal
= 768 + 3 + 6 + 13,
805 static const struct panel_desc auo_b133xtn01
= {
806 .modes
= &auo_b133xtn01_mode
,
815 static const struct drm_display_mode auo_b133htn01_mode
= {
818 .hsync_start
= 1920 + 172,
819 .hsync_end
= 1920 + 172 + 80,
820 .htotal
= 1920 + 172 + 80 + 60,
822 .vsync_start
= 1080 + 25,
823 .vsync_end
= 1080 + 25 + 10,
824 .vtotal
= 1080 + 25 + 10 + 10,
828 static const struct panel_desc auo_b133htn01
= {
829 .modes
= &auo_b133htn01_mode
,
843 static const struct display_timing auo_g070vvn01_timings
= {
844 .pixelclock
= { 33300000, 34209000, 45000000 },
845 .hactive
= { 800, 800, 800 },
846 .hfront_porch
= { 20, 40, 200 },
847 .hback_porch
= { 87, 40, 1 },
848 .hsync_len
= { 1, 48, 87 },
849 .vactive
= { 480, 480, 480 },
850 .vfront_porch
= { 5, 13, 200 },
851 .vback_porch
= { 31, 31, 29 },
852 .vsync_len
= { 1, 1, 3 },
855 static const struct panel_desc auo_g070vvn01
= {
856 .timings
= &auo_g070vvn01_timings
,
871 static const struct drm_display_mode auo_g101evn010_mode
= {
874 .hsync_start
= 1280 + 82,
875 .hsync_end
= 1280 + 82 + 2,
876 .htotal
= 1280 + 82 + 2 + 84,
878 .vsync_start
= 800 + 8,
879 .vsync_end
= 800 + 8 + 2,
880 .vtotal
= 800 + 8 + 2 + 6,
884 static const struct panel_desc auo_g101evn010
= {
885 .modes
= &auo_g101evn010_mode
,
892 .bus_format
= MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
,
893 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
896 static const struct drm_display_mode auo_g104sn02_mode
= {
899 .hsync_start
= 800 + 40,
900 .hsync_end
= 800 + 40 + 216,
901 .htotal
= 800 + 40 + 216 + 128,
903 .vsync_start
= 600 + 10,
904 .vsync_end
= 600 + 10 + 35,
905 .vtotal
= 600 + 10 + 35 + 2,
909 static const struct panel_desc auo_g104sn02
= {
910 .modes
= &auo_g104sn02_mode
,
919 static const struct drm_display_mode auo_g121ean01_mode
= {
922 .hsync_start
= 1280 + 58,
923 .hsync_end
= 1280 + 58 + 8,
924 .htotal
= 1280 + 58 + 8 + 70,
926 .vsync_start
= 800 + 6,
927 .vsync_end
= 800 + 6 + 4,
928 .vtotal
= 800 + 6 + 4 + 10,
932 static const struct panel_desc auo_g121ean01
= {
933 .modes
= &auo_g121ean01_mode
,
940 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
941 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
944 static const struct display_timing auo_g133han01_timings
= {
945 .pixelclock
= { 134000000, 141200000, 149000000 },
946 .hactive
= { 1920, 1920, 1920 },
947 .hfront_porch
= { 39, 58, 77 },
948 .hback_porch
= { 59, 88, 117 },
949 .hsync_len
= { 28, 42, 56 },
950 .vactive
= { 1080, 1080, 1080 },
951 .vfront_porch
= { 3, 8, 11 },
952 .vback_porch
= { 5, 14, 19 },
953 .vsync_len
= { 4, 14, 19 },
956 static const struct panel_desc auo_g133han01
= {
957 .timings
= &auo_g133han01_timings
,
970 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA
,
971 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
974 static const struct drm_display_mode auo_g156xtn01_mode
= {
977 .hsync_start
= 1366 + 33,
978 .hsync_end
= 1366 + 33 + 67,
981 .vsync_start
= 768 + 4,
982 .vsync_end
= 768 + 4 + 4,
987 static const struct panel_desc auo_g156xtn01
= {
988 .modes
= &auo_g156xtn01_mode
,
995 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
996 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
999 static const struct display_timing auo_g185han01_timings
= {
1000 .pixelclock
= { 120000000, 144000000, 175000000 },
1001 .hactive
= { 1920, 1920, 1920 },
1002 .hfront_porch
= { 36, 120, 148 },
1003 .hback_porch
= { 24, 88, 108 },
1004 .hsync_len
= { 20, 48, 64 },
1005 .vactive
= { 1080, 1080, 1080 },
1006 .vfront_porch
= { 6, 10, 40 },
1007 .vback_porch
= { 2, 5, 20 },
1008 .vsync_len
= { 2, 5, 20 },
1011 static const struct panel_desc auo_g185han01
= {
1012 .timings
= &auo_g185han01_timings
,
1025 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
1026 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1029 static const struct display_timing auo_g190ean01_timings
= {
1030 .pixelclock
= { 90000000, 108000000, 135000000 },
1031 .hactive
= { 1280, 1280, 1280 },
1032 .hfront_porch
= { 126, 184, 1266 },
1033 .hback_porch
= { 84, 122, 844 },
1034 .hsync_len
= { 70, 102, 704 },
1035 .vactive
= { 1024, 1024, 1024 },
1036 .vfront_porch
= { 4, 26, 76 },
1037 .vback_porch
= { 2, 8, 25 },
1038 .vsync_len
= { 2, 8, 25 },
1041 static const struct panel_desc auo_g190ean01
= {
1042 .timings
= &auo_g190ean01_timings
,
1055 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
1056 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1059 static const struct display_timing auo_p320hvn03_timings
= {
1060 .pixelclock
= { 106000000, 148500000, 164000000 },
1061 .hactive
= { 1920, 1920, 1920 },
1062 .hfront_porch
= { 25, 50, 130 },
1063 .hback_porch
= { 25, 50, 130 },
1064 .hsync_len
= { 20, 40, 105 },
1065 .vactive
= { 1080, 1080, 1080 },
1066 .vfront_porch
= { 8, 17, 150 },
1067 .vback_porch
= { 8, 17, 150 },
1068 .vsync_len
= { 4, 11, 100 },
1071 static const struct panel_desc auo_p320hvn03
= {
1072 .timings
= &auo_p320hvn03_timings
,
1084 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
1085 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1088 static const struct drm_display_mode auo_t215hvn01_mode
= {
1091 .hsync_start
= 1920 + 88,
1092 .hsync_end
= 1920 + 88 + 44,
1093 .htotal
= 1920 + 88 + 44 + 148,
1095 .vsync_start
= 1080 + 4,
1096 .vsync_end
= 1080 + 4 + 5,
1097 .vtotal
= 1080 + 4 + 5 + 36,
1101 static const struct panel_desc auo_t215hvn01
= {
1102 .modes
= &auo_t215hvn01_mode
,
1115 static const struct drm_display_mode avic_tm070ddh03_mode
= {
1118 .hsync_start
= 1024 + 160,
1119 .hsync_end
= 1024 + 160 + 4,
1120 .htotal
= 1024 + 160 + 4 + 156,
1122 .vsync_start
= 600 + 17,
1123 .vsync_end
= 600 + 17 + 1,
1124 .vtotal
= 600 + 17 + 1 + 17,
1128 static const struct panel_desc avic_tm070ddh03
= {
1129 .modes
= &avic_tm070ddh03_mode
,
1143 static const struct drm_display_mode bananapi_s070wv20_ct16_mode
= {
1146 .hsync_start
= 800 + 40,
1147 .hsync_end
= 800 + 40 + 48,
1148 .htotal
= 800 + 40 + 48 + 40,
1150 .vsync_start
= 480 + 13,
1151 .vsync_end
= 480 + 13 + 3,
1152 .vtotal
= 480 + 13 + 3 + 29,
1155 static const struct panel_desc bananapi_s070wv20_ct16
= {
1156 .modes
= &bananapi_s070wv20_ct16_mode
,
1165 static const struct drm_display_mode boe_hv070wsa_mode
= {
1168 .hsync_start
= 1024 + 30,
1169 .hsync_end
= 1024 + 30 + 30,
1170 .htotal
= 1024 + 30 + 30 + 30,
1172 .vsync_start
= 600 + 10,
1173 .vsync_end
= 600 + 10 + 10,
1174 .vtotal
= 600 + 10 + 10 + 10,
1178 static const struct panel_desc boe_hv070wsa
= {
1179 .modes
= &boe_hv070wsa_mode
,
1187 static const struct drm_display_mode boe_nv101wxmn51_modes
[] = {
1191 .hsync_start
= 1280 + 48,
1192 .hsync_end
= 1280 + 48 + 32,
1193 .htotal
= 1280 + 48 + 32 + 80,
1195 .vsync_start
= 800 + 3,
1196 .vsync_end
= 800 + 3 + 5,
1197 .vtotal
= 800 + 3 + 5 + 24,
1203 .hsync_start
= 1280 + 48,
1204 .hsync_end
= 1280 + 48 + 32,
1205 .htotal
= 1280 + 48 + 32 + 80,
1207 .vsync_start
= 800 + 3,
1208 .vsync_end
= 800 + 3 + 5,
1209 .vtotal
= 800 + 3 + 5 + 24,
1214 static const struct panel_desc boe_nv101wxmn51
= {
1215 .modes
= boe_nv101wxmn51_modes
,
1216 .num_modes
= ARRAY_SIZE(boe_nv101wxmn51_modes
),
1229 /* Also used for boe_nv133fhm_n62 */
1230 static const struct drm_display_mode boe_nv133fhm_n61_modes
= {
1233 .hsync_start
= 1920 + 48,
1234 .hsync_end
= 1920 + 48 + 32,
1235 .htotal
= 1920 + 48 + 32 + 200,
1237 .vsync_start
= 1080 + 3,
1238 .vsync_end
= 1080 + 3 + 6,
1239 .vtotal
= 1080 + 3 + 6 + 31,
1243 /* Also used for boe_nv133fhm_n62 */
1244 static const struct panel_desc boe_nv133fhm_n61
= {
1245 .modes
= &boe_nv133fhm_n61_modes
,
1253 .hpd_absent_delay
= 200,
1256 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1257 .bus_flags
= DRM_BUS_FLAG_DATA_MSB_TO_LSB
,
1258 .connector_type
= DRM_MODE_CONNECTOR_eDP
,
1261 static const struct drm_display_mode boe_nv140fhmn49_modes
[] = {
1265 .hsync_start
= 1920 + 48,
1266 .hsync_end
= 1920 + 48 + 32,
1269 .vsync_start
= 1080 + 3,
1270 .vsync_end
= 1080 + 3 + 5,
1276 static const struct panel_desc boe_nv140fhmn49
= {
1277 .modes
= boe_nv140fhmn49_modes
,
1278 .num_modes
= ARRAY_SIZE(boe_nv140fhmn49_modes
),
1289 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
1290 .connector_type
= DRM_MODE_CONNECTOR_eDP
,
1293 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode
= {
1296 .hsync_start
= 480 + 5,
1297 .hsync_end
= 480 + 5 + 5,
1298 .htotal
= 480 + 5 + 5 + 40,
1300 .vsync_start
= 272 + 8,
1301 .vsync_end
= 272 + 8 + 8,
1302 .vtotal
= 272 + 8 + 8 + 8,
1304 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
1307 static const struct panel_desc cdtech_s043wq26h_ct7
= {
1308 .modes
= &cdtech_s043wq26h_ct7_mode
,
1315 .bus_flags
= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
1318 static const struct drm_display_mode cdtech_s070wv95_ct16_mode
= {
1321 .hsync_start
= 800 + 40,
1322 .hsync_end
= 800 + 40 + 40,
1323 .htotal
= 800 + 40 + 40 + 48,
1325 .vsync_start
= 480 + 29,
1326 .vsync_end
= 480 + 29 + 13,
1327 .vtotal
= 480 + 29 + 13 + 3,
1329 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
1332 static const struct panel_desc cdtech_s070wv95_ct16
= {
1333 .modes
= &cdtech_s070wv95_ct16_mode
,
1342 static const struct drm_display_mode chunghwa_claa070wp03xg_mode
= {
1345 .hsync_start
= 800 + 49,
1346 .hsync_end
= 800 + 49 + 33,
1347 .htotal
= 800 + 49 + 33 + 17,
1349 .vsync_start
= 1280 + 1,
1350 .vsync_end
= 1280 + 1 + 7,
1351 .vtotal
= 1280 + 1 + 7 + 15,
1353 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
1356 static const struct panel_desc chunghwa_claa070wp03xg
= {
1357 .modes
= &chunghwa_claa070wp03xg_mode
,
1366 static const struct drm_display_mode chunghwa_claa101wa01a_mode
= {
1369 .hsync_start
= 1366 + 58,
1370 .hsync_end
= 1366 + 58 + 58,
1371 .htotal
= 1366 + 58 + 58 + 58,
1373 .vsync_start
= 768 + 4,
1374 .vsync_end
= 768 + 4 + 4,
1375 .vtotal
= 768 + 4 + 4 + 4,
1379 static const struct panel_desc chunghwa_claa101wa01a
= {
1380 .modes
= &chunghwa_claa101wa01a_mode
,
1389 static const struct drm_display_mode chunghwa_claa101wb01_mode
= {
1392 .hsync_start
= 1366 + 48,
1393 .hsync_end
= 1366 + 48 + 32,
1394 .htotal
= 1366 + 48 + 32 + 20,
1396 .vsync_start
= 768 + 16,
1397 .vsync_end
= 768 + 16 + 8,
1398 .vtotal
= 768 + 16 + 8 + 16,
1402 static const struct panel_desc chunghwa_claa101wb01
= {
1403 .modes
= &chunghwa_claa101wb01_mode
,
1412 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode
= {
1415 .hsync_start
= 800 + 40,
1416 .hsync_end
= 800 + 40 + 128,
1417 .htotal
= 800 + 40 + 128 + 88,
1419 .vsync_start
= 480 + 10,
1420 .vsync_end
= 480 + 10 + 2,
1421 .vtotal
= 480 + 10 + 2 + 33,
1423 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
1426 static const struct panel_desc dataimage_scf0700c48ggu18
= {
1427 .modes
= &dataimage_scf0700c48ggu18_mode
,
1434 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1435 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
1438 static const struct display_timing dlc_dlc0700yzg_1_timing
= {
1439 .pixelclock
= { 45000000, 51200000, 57000000 },
1440 .hactive
= { 1024, 1024, 1024 },
1441 .hfront_porch
= { 100, 106, 113 },
1442 .hback_porch
= { 100, 106, 113 },
1443 .hsync_len
= { 100, 108, 114 },
1444 .vactive
= { 600, 600, 600 },
1445 .vfront_porch
= { 8, 11, 15 },
1446 .vback_porch
= { 8, 11, 15 },
1447 .vsync_len
= { 9, 13, 15 },
1448 .flags
= DISPLAY_FLAGS_DE_HIGH
,
1451 static const struct panel_desc dlc_dlc0700yzg_1
= {
1452 .timings
= &dlc_dlc0700yzg_1_timing
,
1464 .bus_format
= MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
,
1465 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1468 static const struct display_timing dlc_dlc1010gig_timing
= {
1469 .pixelclock
= { 68900000, 71100000, 73400000 },
1470 .hactive
= { 1280, 1280, 1280 },
1471 .hfront_porch
= { 43, 53, 63 },
1472 .hback_porch
= { 43, 53, 63 },
1473 .hsync_len
= { 44, 54, 64 },
1474 .vactive
= { 800, 800, 800 },
1475 .vfront_porch
= { 5, 8, 11 },
1476 .vback_porch
= { 5, 8, 11 },
1477 .vsync_len
= { 5, 7, 11 },
1478 .flags
= DISPLAY_FLAGS_DE_HIGH
,
1481 static const struct panel_desc dlc_dlc1010gig
= {
1482 .timings
= &dlc_dlc1010gig_timing
,
1495 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
1496 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1499 static const struct drm_display_mode edt_et035012dm6_mode
= {
1502 .hsync_start
= 320 + 20,
1503 .hsync_end
= 320 + 20 + 30,
1504 .htotal
= 320 + 20 + 68,
1506 .vsync_start
= 240 + 4,
1507 .vsync_end
= 240 + 4 + 4,
1508 .vtotal
= 240 + 4 + 4 + 14,
1510 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
1513 static const struct panel_desc edt_et035012dm6
= {
1514 .modes
= &edt_et035012dm6_mode
,
1521 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1522 .bus_flags
= DRM_BUS_FLAG_DE_LOW
| DRM_BUS_FLAG_PIXDATA_NEGEDGE
,
1525 static const struct drm_display_mode edt_etm043080dh6gp_mode
= {
1528 .hsync_start
= 480 + 8,
1529 .hsync_end
= 480 + 8 + 4,
1530 .htotal
= 480 + 8 + 4 + 41,
1533 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1538 .vsync_start
= 288 + 2,
1539 .vsync_end
= 288 + 2 + 4,
1540 .vtotal
= 288 + 2 + 4 + 10,
1544 static const struct panel_desc edt_etm043080dh6gp
= {
1545 .modes
= &edt_etm043080dh6gp_mode
,
1552 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
1553 .connector_type
= DRM_MODE_CONNECTOR_DPI
,
1556 static const struct drm_display_mode edt_etm0430g0dh6_mode
= {
1559 .hsync_start
= 480 + 2,
1560 .hsync_end
= 480 + 2 + 41,
1561 .htotal
= 480 + 2 + 41 + 2,
1563 .vsync_start
= 272 + 2,
1564 .vsync_end
= 272 + 2 + 10,
1565 .vtotal
= 272 + 2 + 10 + 2,
1567 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
1570 static const struct panel_desc edt_etm0430g0dh6
= {
1571 .modes
= &edt_etm0430g0dh6_mode
,
1580 static const struct drm_display_mode edt_et057090dhu_mode
= {
1583 .hsync_start
= 640 + 16,
1584 .hsync_end
= 640 + 16 + 30,
1585 .htotal
= 640 + 16 + 30 + 114,
1587 .vsync_start
= 480 + 10,
1588 .vsync_end
= 480 + 10 + 3,
1589 .vtotal
= 480 + 10 + 3 + 32,
1591 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
1594 static const struct panel_desc edt_et057090dhu
= {
1595 .modes
= &edt_et057090dhu_mode
,
1602 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
1603 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE
,
1606 static const struct drm_display_mode edt_etm0700g0dh6_mode
= {
1609 .hsync_start
= 800 + 40,
1610 .hsync_end
= 800 + 40 + 128,
1611 .htotal
= 800 + 40 + 128 + 88,
1613 .vsync_start
= 480 + 10,
1614 .vsync_end
= 480 + 10 + 2,
1615 .vtotal
= 480 + 10 + 2 + 33,
1617 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
1620 static const struct panel_desc edt_etm0700g0dh6
= {
1621 .modes
= &edt_etm0700g0dh6_mode
,
1628 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
1629 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE
,
1632 static const struct panel_desc edt_etm0700g0bdh6
= {
1633 .modes
= &edt_etm0700g0dh6_mode
,
1640 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
1641 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
1644 static const struct display_timing evervision_vgg804821_timing
= {
1645 .pixelclock
= { 27600000, 33300000, 50000000 },
1646 .hactive
= { 800, 800, 800 },
1647 .hfront_porch
= { 40, 66, 70 },
1648 .hback_porch
= { 40, 67, 70 },
1649 .hsync_len
= { 40, 67, 70 },
1650 .vactive
= { 480, 480, 480 },
1651 .vfront_porch
= { 6, 10, 10 },
1652 .vback_porch
= { 7, 11, 11 },
1653 .vsync_len
= { 7, 11, 11 },
1654 .flags
= DISPLAY_FLAGS_HSYNC_HIGH
| DISPLAY_FLAGS_VSYNC_HIGH
|
1655 DISPLAY_FLAGS_DE_HIGH
| DISPLAY_FLAGS_PIXDATA_NEGEDGE
|
1656 DISPLAY_FLAGS_SYNC_NEGEDGE
,
1659 static const struct panel_desc evervision_vgg804821
= {
1660 .timings
= &evervision_vgg804821_timing
,
1667 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1668 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_NEGEDGE
,
1671 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode
= {
1674 .hsync_start
= 800 + 168,
1675 .hsync_end
= 800 + 168 + 64,
1676 .htotal
= 800 + 168 + 64 + 88,
1678 .vsync_start
= 480 + 37,
1679 .vsync_end
= 480 + 37 + 2,
1680 .vtotal
= 480 + 37 + 2 + 8,
1684 static const struct panel_desc foxlink_fl500wvr00_a0t
= {
1685 .modes
= &foxlink_fl500wvr00_a0t_mode
,
1692 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1695 static const struct drm_display_mode frida_frd350h54004_mode
= {
1698 .hsync_start
= 320 + 44,
1699 .hsync_end
= 320 + 44 + 16,
1700 .htotal
= 320 + 44 + 16 + 20,
1702 .vsync_start
= 240 + 2,
1703 .vsync_end
= 240 + 2 + 6,
1704 .vtotal
= 240 + 2 + 6 + 2,
1706 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
1709 static const struct panel_desc frida_frd350h54004
= {
1710 .modes
= &frida_frd350h54004_mode
,
1717 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1718 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_POSEDGE
,
1719 .connector_type
= DRM_MODE_CONNECTOR_DPI
,
1722 static const struct drm_display_mode friendlyarm_hd702e_mode
= {
1725 .hsync_start
= 800 + 20,
1726 .hsync_end
= 800 + 20 + 24,
1727 .htotal
= 800 + 20 + 24 + 20,
1729 .vsync_start
= 1280 + 4,
1730 .vsync_end
= 1280 + 4 + 8,
1731 .vtotal
= 1280 + 4 + 8 + 4,
1733 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
1736 static const struct panel_desc friendlyarm_hd702e
= {
1737 .modes
= &friendlyarm_hd702e_mode
,
1745 static const struct drm_display_mode giantplus_gpg482739qs5_mode
= {
1748 .hsync_start
= 480 + 5,
1749 .hsync_end
= 480 + 5 + 1,
1750 .htotal
= 480 + 5 + 1 + 40,
1752 .vsync_start
= 272 + 8,
1753 .vsync_end
= 272 + 8 + 1,
1754 .vtotal
= 272 + 8 + 1 + 8,
1758 static const struct panel_desc giantplus_gpg482739qs5
= {
1759 .modes
= &giantplus_gpg482739qs5_mode
,
1766 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1769 static const struct display_timing giantplus_gpm940b0_timing
= {
1770 .pixelclock
= { 13500000, 27000000, 27500000 },
1771 .hactive
= { 320, 320, 320 },
1772 .hfront_porch
= { 14, 686, 718 },
1773 .hback_porch
= { 50, 70, 255 },
1774 .hsync_len
= { 1, 1, 1 },
1775 .vactive
= { 240, 240, 240 },
1776 .vfront_porch
= { 1, 1, 179 },
1777 .vback_porch
= { 1, 21, 31 },
1778 .vsync_len
= { 1, 1, 6 },
1779 .flags
= DISPLAY_FLAGS_HSYNC_LOW
| DISPLAY_FLAGS_VSYNC_LOW
,
1782 static const struct panel_desc giantplus_gpm940b0
= {
1783 .timings
= &giantplus_gpm940b0_timing
,
1790 .bus_format
= MEDIA_BUS_FMT_RGB888_3X8
,
1791 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_NEGEDGE
,
1794 static const struct display_timing hannstar_hsd070pww1_timing
= {
1795 .pixelclock
= { 64300000, 71100000, 82000000 },
1796 .hactive
= { 1280, 1280, 1280 },
1797 .hfront_porch
= { 1, 1, 10 },
1798 .hback_porch
= { 1, 1, 10 },
1800 * According to the data sheet, the minimum horizontal blanking interval
1801 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1802 * minimum working horizontal blanking interval to be 60 clocks.
1804 .hsync_len
= { 58, 158, 661 },
1805 .vactive
= { 800, 800, 800 },
1806 .vfront_porch
= { 1, 1, 10 },
1807 .vback_porch
= { 1, 1, 10 },
1808 .vsync_len
= { 1, 21, 203 },
1809 .flags
= DISPLAY_FLAGS_DE_HIGH
,
1812 static const struct panel_desc hannstar_hsd070pww1
= {
1813 .timings
= &hannstar_hsd070pww1_timing
,
1820 .bus_format
= MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
,
1821 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1824 static const struct display_timing hannstar_hsd100pxn1_timing
= {
1825 .pixelclock
= { 55000000, 65000000, 75000000 },
1826 .hactive
= { 1024, 1024, 1024 },
1827 .hfront_porch
= { 40, 40, 40 },
1828 .hback_porch
= { 220, 220, 220 },
1829 .hsync_len
= { 20, 60, 100 },
1830 .vactive
= { 768, 768, 768 },
1831 .vfront_porch
= { 7, 7, 7 },
1832 .vback_porch
= { 21, 21, 21 },
1833 .vsync_len
= { 10, 10, 10 },
1834 .flags
= DISPLAY_FLAGS_DE_HIGH
,
1837 static const struct panel_desc hannstar_hsd100pxn1
= {
1838 .timings
= &hannstar_hsd100pxn1_timing
,
1845 .bus_format
= MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
,
1846 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1849 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode
= {
1852 .hsync_start
= 800 + 85,
1853 .hsync_end
= 800 + 85 + 86,
1854 .htotal
= 800 + 85 + 86 + 85,
1856 .vsync_start
= 480 + 16,
1857 .vsync_end
= 480 + 16 + 13,
1858 .vtotal
= 480 + 16 + 13 + 16,
1862 static const struct panel_desc hitachi_tx23d38vm0caa
= {
1863 .modes
= &hitachi_tx23d38vm0caa_mode
,
1876 static const struct drm_display_mode innolux_at043tn24_mode
= {
1879 .hsync_start
= 480 + 2,
1880 .hsync_end
= 480 + 2 + 41,
1881 .htotal
= 480 + 2 + 41 + 2,
1883 .vsync_start
= 272 + 2,
1884 .vsync_end
= 272 + 2 + 10,
1885 .vtotal
= 272 + 2 + 10 + 2,
1887 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
1890 static const struct panel_desc innolux_at043tn24
= {
1891 .modes
= &innolux_at043tn24_mode
,
1898 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1899 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
1902 static const struct drm_display_mode innolux_at070tn92_mode
= {
1905 .hsync_start
= 800 + 210,
1906 .hsync_end
= 800 + 210 + 20,
1907 .htotal
= 800 + 210 + 20 + 46,
1909 .vsync_start
= 480 + 22,
1910 .vsync_end
= 480 + 22 + 10,
1911 .vtotal
= 480 + 22 + 23 + 10,
1915 static const struct panel_desc innolux_at070tn92
= {
1916 .modes
= &innolux_at070tn92_mode
,
1922 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
1925 static const struct display_timing innolux_g070y2_l01_timing
= {
1926 .pixelclock
= { 28000000, 29500000, 32000000 },
1927 .hactive
= { 800, 800, 800 },
1928 .hfront_porch
= { 61, 91, 141 },
1929 .hback_porch
= { 60, 90, 140 },
1930 .hsync_len
= { 12, 12, 12 },
1931 .vactive
= { 480, 480, 480 },
1932 .vfront_porch
= { 4, 9, 30 },
1933 .vback_porch
= { 4, 8, 28 },
1934 .vsync_len
= { 2, 2, 2 },
1935 .flags
= DISPLAY_FLAGS_DE_HIGH
,
1938 static const struct panel_desc innolux_g070y2_l01
= {
1939 .timings
= &innolux_g070y2_l01_timing
,
1952 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
1953 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1956 static const struct display_timing innolux_g101ice_l01_timing
= {
1957 .pixelclock
= { 60400000, 71100000, 74700000 },
1958 .hactive
= { 1280, 1280, 1280 },
1959 .hfront_porch
= { 41, 80, 100 },
1960 .hback_porch
= { 40, 79, 99 },
1961 .hsync_len
= { 1, 1, 1 },
1962 .vactive
= { 800, 800, 800 },
1963 .vfront_porch
= { 5, 11, 14 },
1964 .vback_porch
= { 4, 11, 14 },
1965 .vsync_len
= { 1, 1, 1 },
1966 .flags
= DISPLAY_FLAGS_DE_HIGH
,
1969 static const struct panel_desc innolux_g101ice_l01
= {
1970 .timings
= &innolux_g101ice_l01_timing
,
1981 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
1982 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
1985 static const struct display_timing innolux_g121i1_l01_timing
= {
1986 .pixelclock
= { 67450000, 71000000, 74550000 },
1987 .hactive
= { 1280, 1280, 1280 },
1988 .hfront_porch
= { 40, 80, 160 },
1989 .hback_porch
= { 39, 79, 159 },
1990 .hsync_len
= { 1, 1, 1 },
1991 .vactive
= { 800, 800, 800 },
1992 .vfront_porch
= { 5, 11, 100 },
1993 .vback_porch
= { 4, 11, 99 },
1994 .vsync_len
= { 1, 1, 1 },
1997 static const struct panel_desc innolux_g121i1_l01
= {
1998 .timings
= &innolux_g121i1_l01_timing
,
2009 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2010 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2013 static const struct drm_display_mode innolux_g121x1_l03_mode
= {
2016 .hsync_start
= 1024 + 0,
2017 .hsync_end
= 1024 + 1,
2018 .htotal
= 1024 + 0 + 1 + 320,
2020 .vsync_start
= 768 + 38,
2021 .vsync_end
= 768 + 38 + 1,
2022 .vtotal
= 768 + 38 + 1 + 0,
2024 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
2027 static const struct panel_desc innolux_g121x1_l03
= {
2028 .modes
= &innolux_g121x1_l03_mode
,
2043 * Datasheet specifies that at 60 Hz refresh rate:
2044 * - total horizontal time: { 1506, 1592, 1716 }
2045 * - total vertical time: { 788, 800, 868 }
2047 * ...but doesn't go into exactly how that should be split into a front
2048 * porch, back porch, or sync length. For now we'll leave a single setting
2049 * here which allows a bit of tweaking of the pixel clock at the expense of
2052 static const struct display_timing innolux_n116bge_timing
= {
2053 .pixelclock
= { 72600000, 76420000, 80240000 },
2054 .hactive
= { 1366, 1366, 1366 },
2055 .hfront_porch
= { 136, 136, 136 },
2056 .hback_porch
= { 60, 60, 60 },
2057 .hsync_len
= { 30, 30, 30 },
2058 .vactive
= { 768, 768, 768 },
2059 .vfront_porch
= { 8, 8, 8 },
2060 .vback_porch
= { 12, 12, 12 },
2061 .vsync_len
= { 12, 12, 12 },
2062 .flags
= DISPLAY_FLAGS_VSYNC_LOW
| DISPLAY_FLAGS_HSYNC_LOW
,
2065 static const struct panel_desc innolux_n116bge
= {
2066 .timings
= &innolux_n116bge_timing
,
2075 static const struct drm_display_mode innolux_n156bge_l21_mode
= {
2078 .hsync_start
= 1366 + 16,
2079 .hsync_end
= 1366 + 16 + 34,
2080 .htotal
= 1366 + 16 + 34 + 50,
2082 .vsync_start
= 768 + 2,
2083 .vsync_end
= 768 + 2 + 6,
2084 .vtotal
= 768 + 2 + 6 + 12,
2088 static const struct panel_desc innolux_n156bge_l21
= {
2089 .modes
= &innolux_n156bge_l21_mode
,
2098 static const struct drm_display_mode innolux_p120zdg_bf1_mode
= {
2101 .hsync_start
= 2160 + 48,
2102 .hsync_end
= 2160 + 48 + 32,
2103 .htotal
= 2160 + 48 + 32 + 80,
2105 .vsync_start
= 1440 + 3,
2106 .vsync_end
= 1440 + 3 + 10,
2107 .vtotal
= 1440 + 3 + 10 + 27,
2109 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
2112 static const struct panel_desc innolux_p120zdg_bf1
= {
2113 .modes
= &innolux_p120zdg_bf1_mode
,
2121 .hpd_absent_delay
= 200,
2126 static const struct drm_display_mode innolux_zj070na_01p_mode
= {
2129 .hsync_start
= 1024 + 128,
2130 .hsync_end
= 1024 + 128 + 64,
2131 .htotal
= 1024 + 128 + 64 + 128,
2133 .vsync_start
= 600 + 16,
2134 .vsync_end
= 600 + 16 + 4,
2135 .vtotal
= 600 + 16 + 4 + 16,
2139 static const struct panel_desc innolux_zj070na_01p
= {
2140 .modes
= &innolux_zj070na_01p_mode
,
2149 static const struct drm_display_mode ivo_m133nwf4_r0_mode
= {
2152 .hsync_start
= 1920 + 24,
2153 .hsync_end
= 1920 + 24 + 48,
2154 .htotal
= 1920 + 24 + 48 + 88,
2156 .vsync_start
= 1080 + 3,
2157 .vsync_end
= 1080 + 3 + 12,
2158 .vtotal
= 1080 + 3 + 12 + 17,
2160 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
2163 static const struct panel_desc ivo_m133nwf4_r0
= {
2164 .modes
= &ivo_m133nwf4_r0_mode
,
2172 .hpd_absent_delay
= 200,
2175 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2176 .bus_flags
= DRM_BUS_FLAG_DATA_MSB_TO_LSB
,
2177 .connector_type
= DRM_MODE_CONNECTOR_eDP
,
2180 static const struct display_timing koe_tx14d24vm1bpa_timing
= {
2181 .pixelclock
= { 5580000, 5850000, 6200000 },
2182 .hactive
= { 320, 320, 320 },
2183 .hfront_porch
= { 30, 30, 30 },
2184 .hback_porch
= { 30, 30, 30 },
2185 .hsync_len
= { 1, 5, 17 },
2186 .vactive
= { 240, 240, 240 },
2187 .vfront_porch
= { 6, 6, 6 },
2188 .vback_porch
= { 5, 5, 5 },
2189 .vsync_len
= { 1, 2, 11 },
2190 .flags
= DISPLAY_FLAGS_DE_HIGH
,
2193 static const struct panel_desc koe_tx14d24vm1bpa
= {
2194 .timings
= &koe_tx14d24vm1bpa_timing
,
2203 static const struct display_timing koe_tx31d200vm0baa_timing
= {
2204 .pixelclock
= { 39600000, 43200000, 48000000 },
2205 .hactive
= { 1280, 1280, 1280 },
2206 .hfront_porch
= { 16, 36, 56 },
2207 .hback_porch
= { 16, 36, 56 },
2208 .hsync_len
= { 8, 8, 8 },
2209 .vactive
= { 480, 480, 480 },
2210 .vfront_porch
= { 6, 21, 33 },
2211 .vback_porch
= { 6, 21, 33 },
2212 .vsync_len
= { 8, 8, 8 },
2213 .flags
= DISPLAY_FLAGS_DE_HIGH
,
2216 static const struct panel_desc koe_tx31d200vm0baa
= {
2217 .timings
= &koe_tx31d200vm0baa_timing
,
2224 .bus_format
= MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
,
2225 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2228 static const struct display_timing kyo_tcg121xglp_timing
= {
2229 .pixelclock
= { 52000000, 65000000, 71000000 },
2230 .hactive
= { 1024, 1024, 1024 },
2231 .hfront_porch
= { 2, 2, 2 },
2232 .hback_porch
= { 2, 2, 2 },
2233 .hsync_len
= { 86, 124, 244 },
2234 .vactive
= { 768, 768, 768 },
2235 .vfront_porch
= { 2, 2, 2 },
2236 .vback_porch
= { 2, 2, 2 },
2237 .vsync_len
= { 6, 34, 73 },
2238 .flags
= DISPLAY_FLAGS_DE_HIGH
,
2241 static const struct panel_desc kyo_tcg121xglp
= {
2242 .timings
= &kyo_tcg121xglp_timing
,
2249 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2250 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2253 static const struct drm_display_mode lemaker_bl035_rgb_002_mode
= {
2256 .hsync_start
= 320 + 20,
2257 .hsync_end
= 320 + 20 + 30,
2258 .htotal
= 320 + 20 + 30 + 38,
2260 .vsync_start
= 240 + 4,
2261 .vsync_end
= 240 + 4 + 3,
2262 .vtotal
= 240 + 4 + 3 + 15,
2266 static const struct panel_desc lemaker_bl035_rgb_002
= {
2267 .modes
= &lemaker_bl035_rgb_002_mode
,
2273 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2274 .bus_flags
= DRM_BUS_FLAG_DE_LOW
,
2277 static const struct drm_display_mode lg_lb070wv8_mode
= {
2280 .hsync_start
= 800 + 88,
2281 .hsync_end
= 800 + 88 + 80,
2282 .htotal
= 800 + 88 + 80 + 88,
2284 .vsync_start
= 480 + 10,
2285 .vsync_end
= 480 + 10 + 25,
2286 .vtotal
= 480 + 10 + 25 + 10,
2290 static const struct panel_desc lg_lb070wv8
= {
2291 .modes
= &lg_lb070wv8_mode
,
2298 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2299 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2302 static const struct drm_display_mode lg_lp079qx1_sp0v_mode
= {
2305 .hsync_start
= 1536 + 12,
2306 .hsync_end
= 1536 + 12 + 16,
2307 .htotal
= 1536 + 12 + 16 + 48,
2309 .vsync_start
= 2048 + 8,
2310 .vsync_end
= 2048 + 8 + 4,
2311 .vtotal
= 2048 + 8 + 4 + 8,
2313 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2316 static const struct panel_desc lg_lp079qx1_sp0v
= {
2317 .modes
= &lg_lp079qx1_sp0v_mode
,
2325 static const struct drm_display_mode lg_lp097qx1_spa1_mode
= {
2328 .hsync_start
= 2048 + 150,
2329 .hsync_end
= 2048 + 150 + 5,
2330 .htotal
= 2048 + 150 + 5 + 5,
2332 .vsync_start
= 1536 + 3,
2333 .vsync_end
= 1536 + 3 + 1,
2334 .vtotal
= 1536 + 3 + 1 + 9,
2338 static const struct panel_desc lg_lp097qx1_spa1
= {
2339 .modes
= &lg_lp097qx1_spa1_mode
,
2347 static const struct drm_display_mode lg_lp120up1_mode
= {
2350 .hsync_start
= 1920 + 40,
2351 .hsync_end
= 1920 + 40 + 40,
2352 .htotal
= 1920 + 40 + 40+ 80,
2354 .vsync_start
= 1280 + 4,
2355 .vsync_end
= 1280 + 4 + 4,
2356 .vtotal
= 1280 + 4 + 4 + 12,
2360 static const struct panel_desc lg_lp120up1
= {
2361 .modes
= &lg_lp120up1_mode
,
2368 .connector_type
= DRM_MODE_CONNECTOR_eDP
,
2371 static const struct drm_display_mode lg_lp129qe_mode
= {
2374 .hsync_start
= 2560 + 48,
2375 .hsync_end
= 2560 + 48 + 32,
2376 .htotal
= 2560 + 48 + 32 + 80,
2378 .vsync_start
= 1700 + 3,
2379 .vsync_end
= 1700 + 3 + 10,
2380 .vtotal
= 1700 + 3 + 10 + 36,
2384 static const struct panel_desc lg_lp129qe
= {
2385 .modes
= &lg_lp129qe_mode
,
2394 static const struct display_timing logictechno_lt161010_2nh_timing
= {
2395 .pixelclock
= { 26400000, 33300000, 46800000 },
2396 .hactive
= { 800, 800, 800 },
2397 .hfront_porch
= { 16, 210, 354 },
2398 .hback_porch
= { 46, 46, 46 },
2399 .hsync_len
= { 1, 20, 40 },
2400 .vactive
= { 480, 480, 480 },
2401 .vfront_porch
= { 7, 22, 147 },
2402 .vback_porch
= { 23, 23, 23 },
2403 .vsync_len
= { 1, 10, 20 },
2404 .flags
= DISPLAY_FLAGS_HSYNC_LOW
| DISPLAY_FLAGS_VSYNC_LOW
|
2405 DISPLAY_FLAGS_DE_HIGH
| DISPLAY_FLAGS_PIXDATA_POSEDGE
|
2406 DISPLAY_FLAGS_SYNC_POSEDGE
,
2409 static const struct panel_desc logictechno_lt161010_2nh
= {
2410 .timings
= &logictechno_lt161010_2nh_timing
,
2416 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
2417 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
|
2418 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
|
2419 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
,
2420 .connector_type
= DRM_MODE_CONNECTOR_DPI
,
2423 static const struct display_timing logictechno_lt170410_2whc_timing
= {
2424 .pixelclock
= { 68900000, 71100000, 73400000 },
2425 .hactive
= { 1280, 1280, 1280 },
2426 .hfront_porch
= { 23, 60, 71 },
2427 .hback_porch
= { 23, 60, 71 },
2428 .hsync_len
= { 15, 40, 47 },
2429 .vactive
= { 800, 800, 800 },
2430 .vfront_porch
= { 5, 7, 10 },
2431 .vback_porch
= { 5, 7, 10 },
2432 .vsync_len
= { 6, 9, 12 },
2433 .flags
= DISPLAY_FLAGS_HSYNC_LOW
| DISPLAY_FLAGS_VSYNC_LOW
|
2434 DISPLAY_FLAGS_DE_HIGH
| DISPLAY_FLAGS_PIXDATA_POSEDGE
|
2435 DISPLAY_FLAGS_SYNC_POSEDGE
,
2438 static const struct panel_desc logictechno_lt170410_2whc
= {
2439 .timings
= &logictechno_lt170410_2whc_timing
,
2445 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2446 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
|
2447 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE
|
2448 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
,
2449 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2452 static const struct drm_display_mode mitsubishi_aa070mc01_mode
= {
2455 .hsync_start
= 800 + 0,
2456 .hsync_end
= 800 + 1,
2457 .htotal
= 800 + 0 + 1 + 160,
2459 .vsync_start
= 480 + 0,
2460 .vsync_end
= 480 + 48 + 1,
2461 .vtotal
= 480 + 48 + 1 + 0,
2463 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
2466 static const struct drm_display_mode logicpd_type_28_mode
= {
2469 .hsync_start
= 480 + 3,
2470 .hsync_end
= 480 + 3 + 42,
2471 .htotal
= 480 + 3 + 42 + 2,
2474 .vsync_start
= 272 + 2,
2475 .vsync_end
= 272 + 2 + 11,
2476 .vtotal
= 272 + 2 + 11 + 3,
2478 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
2481 static const struct panel_desc logicpd_type_28
= {
2482 .modes
= &logicpd_type_28_mode
,
2495 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2496 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
|
2497 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE
,
2498 .connector_type
= DRM_MODE_CONNECTOR_DPI
,
2501 static const struct panel_desc mitsubishi_aa070mc01
= {
2502 .modes
= &mitsubishi_aa070mc01_mode
,
2515 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2516 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2517 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
,
2520 static const struct display_timing nec_nl12880bc20_05_timing
= {
2521 .pixelclock
= { 67000000, 71000000, 75000000 },
2522 .hactive
= { 1280, 1280, 1280 },
2523 .hfront_porch
= { 2, 30, 30 },
2524 .hback_porch
= { 6, 100, 100 },
2525 .hsync_len
= { 2, 30, 30 },
2526 .vactive
= { 800, 800, 800 },
2527 .vfront_porch
= { 5, 5, 5 },
2528 .vback_porch
= { 11, 11, 11 },
2529 .vsync_len
= { 7, 7, 7 },
2532 static const struct panel_desc nec_nl12880bc20_05
= {
2533 .timings
= &nec_nl12880bc20_05_timing
,
2544 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2545 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2548 static const struct drm_display_mode nec_nl4827hc19_05b_mode
= {
2551 .hsync_start
= 480 + 2,
2552 .hsync_end
= 480 + 2 + 41,
2553 .htotal
= 480 + 2 + 41 + 2,
2555 .vsync_start
= 272 + 2,
2556 .vsync_end
= 272 + 2 + 4,
2557 .vtotal
= 272 + 2 + 4 + 2,
2559 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2562 static const struct panel_desc nec_nl4827hc19_05b
= {
2563 .modes
= &nec_nl4827hc19_05b_mode
,
2570 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2571 .bus_flags
= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
2574 static const struct drm_display_mode netron_dy_e231732_mode
= {
2577 .hsync_start
= 1024 + 160,
2578 .hsync_end
= 1024 + 160 + 70,
2579 .htotal
= 1024 + 160 + 70 + 90,
2581 .vsync_start
= 600 + 127,
2582 .vsync_end
= 600 + 127 + 20,
2583 .vtotal
= 600 + 127 + 20 + 3,
2587 static const struct panel_desc netron_dy_e231732
= {
2588 .modes
= &netron_dy_e231732_mode
,
2594 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
2597 static const struct drm_display_mode neweast_wjfh116008a_modes
[] = {
2601 .hsync_start
= 1920 + 48,
2602 .hsync_end
= 1920 + 48 + 32,
2603 .htotal
= 1920 + 48 + 32 + 80,
2605 .vsync_start
= 1080 + 3,
2606 .vsync_end
= 1080 + 3 + 5,
2607 .vtotal
= 1080 + 3 + 5 + 23,
2609 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2613 .hsync_start
= 1920 + 48,
2614 .hsync_end
= 1920 + 48 + 32,
2615 .htotal
= 1920 + 48 + 32 + 80,
2617 .vsync_start
= 1080 + 3,
2618 .vsync_end
= 1080 + 3 + 5,
2619 .vtotal
= 1080 + 3 + 5 + 23,
2621 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2625 static const struct panel_desc neweast_wjfh116008a
= {
2626 .modes
= neweast_wjfh116008a_modes
,
2638 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
2639 .connector_type
= DRM_MODE_CONNECTOR_eDP
,
2642 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode
= {
2645 .hsync_start
= 480 + 2,
2646 .hsync_end
= 480 + 2 + 41,
2647 .htotal
= 480 + 2 + 41 + 2,
2649 .vsync_start
= 272 + 2,
2650 .vsync_end
= 272 + 2 + 10,
2651 .vtotal
= 272 + 2 + 10 + 2,
2653 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2656 static const struct panel_desc newhaven_nhd_43_480272ef_atxl
= {
2657 .modes
= &newhaven_nhd_43_480272ef_atxl_mode
,
2664 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2665 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
|
2666 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
,
2669 static const struct display_timing nlt_nl192108ac18_02d_timing
= {
2670 .pixelclock
= { 130000000, 148350000, 163000000 },
2671 .hactive
= { 1920, 1920, 1920 },
2672 .hfront_porch
= { 80, 100, 100 },
2673 .hback_porch
= { 100, 120, 120 },
2674 .hsync_len
= { 50, 60, 60 },
2675 .vactive
= { 1080, 1080, 1080 },
2676 .vfront_porch
= { 12, 30, 30 },
2677 .vback_porch
= { 4, 10, 10 },
2678 .vsync_len
= { 4, 5, 5 },
2681 static const struct panel_desc nlt_nl192108ac18_02d
= {
2682 .timings
= &nlt_nl192108ac18_02d_timing
,
2692 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2693 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2696 static const struct drm_display_mode nvd_9128_mode
= {
2699 .hsync_start
= 800 + 130,
2700 .hsync_end
= 800 + 130 + 98,
2701 .htotal
= 800 + 0 + 130 + 98,
2703 .vsync_start
= 480 + 10,
2704 .vsync_end
= 480 + 10 + 50,
2705 .vtotal
= 480 + 0 + 10 + 50,
2708 static const struct panel_desc nvd_9128
= {
2709 .modes
= &nvd_9128_mode
,
2716 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2717 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2720 static const struct display_timing okaya_rs800480t_7x0gp_timing
= {
2721 .pixelclock
= { 30000000, 30000000, 40000000 },
2722 .hactive
= { 800, 800, 800 },
2723 .hfront_porch
= { 40, 40, 40 },
2724 .hback_porch
= { 40, 40, 40 },
2725 .hsync_len
= { 1, 48, 48 },
2726 .vactive
= { 480, 480, 480 },
2727 .vfront_porch
= { 13, 13, 13 },
2728 .vback_porch
= { 29, 29, 29 },
2729 .vsync_len
= { 3, 3, 3 },
2730 .flags
= DISPLAY_FLAGS_DE_HIGH
,
2733 static const struct panel_desc okaya_rs800480t_7x0gp
= {
2734 .timings
= &okaya_rs800480t_7x0gp_timing
,
2747 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
2750 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode
= {
2753 .hsync_start
= 480 + 5,
2754 .hsync_end
= 480 + 5 + 30,
2755 .htotal
= 480 + 5 + 30 + 10,
2757 .vsync_start
= 272 + 8,
2758 .vsync_end
= 272 + 8 + 5,
2759 .vtotal
= 272 + 8 + 5 + 3,
2763 static const struct panel_desc olimex_lcd_olinuxino_43ts
= {
2764 .modes
= &olimex_lcd_olinuxino_43ts_mode
,
2770 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2774 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2775 * pixel clocks, but this is the timing that was being used in the Adafruit
2776 * installation instructions.
2778 static const struct drm_display_mode ontat_yx700wv03_mode
= {
2789 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2794 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2796 static const struct panel_desc ontat_yx700wv03
= {
2797 .modes
= &ontat_yx700wv03_mode
,
2804 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
2807 static const struct drm_display_mode ortustech_com37h3m_mode
= {
2810 .hsync_start
= 480 + 40,
2811 .hsync_end
= 480 + 40 + 10,
2812 .htotal
= 480 + 40 + 10 + 40,
2814 .vsync_start
= 640 + 4,
2815 .vsync_end
= 640 + 4 + 2,
2816 .vtotal
= 640 + 4 + 2 + 4,
2818 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2821 static const struct panel_desc ortustech_com37h3m
= {
2822 .modes
= &ortustech_com37h3m_mode
,
2826 .width
= 56, /* 56.16mm */
2827 .height
= 75, /* 74.88mm */
2829 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2830 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_POSEDGE
|
2831 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
,
2834 static const struct drm_display_mode ortustech_com43h4m85ulc_mode
= {
2837 .hsync_start
= 480 + 10,
2838 .hsync_end
= 480 + 10 + 10,
2839 .htotal
= 480 + 10 + 10 + 15,
2841 .vsync_start
= 800 + 3,
2842 .vsync_end
= 800 + 3 + 3,
2843 .vtotal
= 800 + 3 + 3 + 3,
2847 static const struct panel_desc ortustech_com43h4m85ulc
= {
2848 .modes
= &ortustech_com43h4m85ulc_mode
,
2855 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2856 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
2857 .connector_type
= DRM_MODE_CONNECTOR_DPI
,
2860 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode
= {
2863 .hsync_start
= 800 + 210,
2864 .hsync_end
= 800 + 210 + 30,
2865 .htotal
= 800 + 210 + 30 + 16,
2867 .vsync_start
= 480 + 22,
2868 .vsync_end
= 480 + 22 + 13,
2869 .vtotal
= 480 + 22 + 13 + 10,
2871 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
2874 static const struct panel_desc osddisplays_osd070t1718_19ts
= {
2875 .modes
= &osddisplays_osd070t1718_19ts_mode
,
2882 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2883 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
|
2884 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
,
2885 .connector_type
= DRM_MODE_CONNECTOR_DPI
,
2888 static const struct drm_display_mode pda_91_00156_a0_mode
= {
2891 .hsync_start
= 800 + 1,
2892 .hsync_end
= 800 + 1 + 64,
2893 .htotal
= 800 + 1 + 64 + 64,
2895 .vsync_start
= 480 + 1,
2896 .vsync_end
= 480 + 1 + 23,
2897 .vtotal
= 480 + 1 + 23 + 22,
2901 static const struct panel_desc pda_91_00156_a0
= {
2902 .modes
= &pda_91_00156_a0_mode
,
2908 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2912 static const struct drm_display_mode qd43003c0_40_mode
= {
2915 .hsync_start
= 480 + 8,
2916 .hsync_end
= 480 + 8 + 4,
2917 .htotal
= 480 + 8 + 4 + 39,
2919 .vsync_start
= 272 + 4,
2920 .vsync_end
= 272 + 4 + 10,
2921 .vtotal
= 272 + 4 + 10 + 2,
2925 static const struct panel_desc qd43003c0_40
= {
2926 .modes
= &qd43003c0_40_mode
,
2933 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
2936 static const struct display_timing rocktech_rk070er9427_timing
= {
2937 .pixelclock
= { 26400000, 33300000, 46800000 },
2938 .hactive
= { 800, 800, 800 },
2939 .hfront_porch
= { 16, 210, 354 },
2940 .hback_porch
= { 46, 46, 46 },
2941 .hsync_len
= { 1, 1, 1 },
2942 .vactive
= { 480, 480, 480 },
2943 .vfront_porch
= { 7, 22, 147 },
2944 .vback_porch
= { 23, 23, 23 },
2945 .vsync_len
= { 1, 1, 1 },
2946 .flags
= DISPLAY_FLAGS_DE_HIGH
,
2949 static const struct panel_desc rocktech_rk070er9427
= {
2950 .timings
= &rocktech_rk070er9427_timing
,
2963 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
2966 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode
= {
2969 .hsync_start
= 1280 + 48,
2970 .hsync_end
= 1280 + 48 + 32,
2971 .htotal
= 1280 + 48 + 32 + 80,
2973 .vsync_start
= 800 + 2,
2974 .vsync_end
= 800 + 2 + 5,
2975 .vtotal
= 800 + 2 + 5 + 16,
2979 static const struct panel_desc rocktech_rk101ii01d_ct
= {
2980 .modes
= &rocktech_rk101ii01d_ct_mode
,
2990 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
,
2991 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
2992 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
2995 static const struct drm_display_mode samsung_lsn122dl01_c01_mode
= {
2998 .hsync_start
= 2560 + 48,
2999 .hsync_end
= 2560 + 48 + 32,
3000 .htotal
= 2560 + 48 + 32 + 80,
3002 .vsync_start
= 1600 + 2,
3003 .vsync_end
= 1600 + 2 + 5,
3004 .vtotal
= 1600 + 2 + 5 + 57,
3008 static const struct panel_desc samsung_lsn122dl01_c01
= {
3009 .modes
= &samsung_lsn122dl01_c01_mode
,
3017 static const struct drm_display_mode samsung_ltn101nt05_mode
= {
3020 .hsync_start
= 1024 + 24,
3021 .hsync_end
= 1024 + 24 + 136,
3022 .htotal
= 1024 + 24 + 136 + 160,
3024 .vsync_start
= 600 + 3,
3025 .vsync_end
= 600 + 3 + 6,
3026 .vtotal
= 600 + 3 + 6 + 61,
3030 static const struct panel_desc samsung_ltn101nt05
= {
3031 .modes
= &samsung_ltn101nt05_mode
,
3040 static const struct drm_display_mode samsung_ltn140at29_301_mode
= {
3043 .hsync_start
= 1366 + 64,
3044 .hsync_end
= 1366 + 64 + 48,
3045 .htotal
= 1366 + 64 + 48 + 128,
3047 .vsync_start
= 768 + 2,
3048 .vsync_end
= 768 + 2 + 5,
3049 .vtotal
= 768 + 2 + 5 + 17,
3053 static const struct panel_desc samsung_ltn140at29_301
= {
3054 .modes
= &samsung_ltn140at29_301_mode
,
3063 static const struct display_timing satoz_sat050at40h12r2_timing
= {
3064 .pixelclock
= {33300000, 33300000, 50000000},
3065 .hactive
= {800, 800, 800},
3066 .hfront_porch
= {16, 210, 354},
3067 .hback_porch
= {46, 46, 46},
3068 .hsync_len
= {1, 1, 40},
3069 .vactive
= {480, 480, 480},
3070 .vfront_porch
= {7, 22, 147},
3071 .vback_porch
= {23, 23, 23},
3072 .vsync_len
= {1, 1, 20},
3075 static const struct panel_desc satoz_sat050at40h12r2
= {
3076 .timings
= &satoz_sat050at40h12r2_timing
,
3083 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3084 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3087 static const struct drm_display_mode sharp_ld_d5116z01b_mode
= {
3090 .hsync_start
= 1920 + 48,
3091 .hsync_end
= 1920 + 48 + 32,
3092 .htotal
= 1920 + 48 + 32 + 80,
3094 .vsync_start
= 1280 + 3,
3095 .vsync_end
= 1280 + 3 + 10,
3096 .vtotal
= 1280 + 3 + 10 + 57,
3098 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
3101 static const struct panel_desc sharp_ld_d5116z01b
= {
3102 .modes
= &sharp_ld_d5116z01b_mode
,
3109 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3110 .bus_flags
= DRM_BUS_FLAG_DATA_MSB_TO_LSB
,
3113 static const struct drm_display_mode sharp_lq070y3dg3b_mode
= {
3116 .hsync_start
= 800 + 64,
3117 .hsync_end
= 800 + 64 + 128,
3118 .htotal
= 800 + 64 + 128 + 64,
3120 .vsync_start
= 480 + 8,
3121 .vsync_end
= 480 + 8 + 2,
3122 .vtotal
= 480 + 8 + 2 + 35,
3124 .flags
= DISPLAY_FLAGS_PIXDATA_POSEDGE
,
3127 static const struct panel_desc sharp_lq070y3dg3b
= {
3128 .modes
= &sharp_lq070y3dg3b_mode
,
3132 .width
= 152, /* 152.4mm */
3133 .height
= 91, /* 91.4mm */
3135 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3136 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_POSEDGE
|
3137 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE
,
3140 static const struct drm_display_mode sharp_lq035q7db03_mode
= {
3143 .hsync_start
= 240 + 16,
3144 .hsync_end
= 240 + 16 + 7,
3145 .htotal
= 240 + 16 + 7 + 5,
3147 .vsync_start
= 320 + 9,
3148 .vsync_end
= 320 + 9 + 1,
3149 .vtotal
= 320 + 9 + 1 + 7,
3153 static const struct panel_desc sharp_lq035q7db03
= {
3154 .modes
= &sharp_lq035q7db03_mode
,
3161 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
3164 static const struct display_timing sharp_lq101k1ly04_timing
= {
3165 .pixelclock
= { 60000000, 65000000, 80000000 },
3166 .hactive
= { 1280, 1280, 1280 },
3167 .hfront_porch
= { 20, 20, 20 },
3168 .hback_porch
= { 20, 20, 20 },
3169 .hsync_len
= { 10, 10, 10 },
3170 .vactive
= { 800, 800, 800 },
3171 .vfront_porch
= { 4, 4, 4 },
3172 .vback_porch
= { 4, 4, 4 },
3173 .vsync_len
= { 4, 4, 4 },
3174 .flags
= DISPLAY_FLAGS_PIXDATA_POSEDGE
,
3177 static const struct panel_desc sharp_lq101k1ly04
= {
3178 .timings
= &sharp_lq101k1ly04_timing
,
3185 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA
,
3186 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3189 static const struct display_timing sharp_lq123p1jx31_timing
= {
3190 .pixelclock
= { 252750000, 252750000, 266604720 },
3191 .hactive
= { 2400, 2400, 2400 },
3192 .hfront_porch
= { 48, 48, 48 },
3193 .hback_porch
= { 80, 80, 84 },
3194 .hsync_len
= { 32, 32, 32 },
3195 .vactive
= { 1600, 1600, 1600 },
3196 .vfront_porch
= { 3, 3, 3 },
3197 .vback_porch
= { 33, 33, 120 },
3198 .vsync_len
= { 10, 10, 10 },
3199 .flags
= DISPLAY_FLAGS_VSYNC_LOW
| DISPLAY_FLAGS_HSYNC_LOW
,
3202 static const struct panel_desc sharp_lq123p1jx31
= {
3203 .timings
= &sharp_lq123p1jx31_timing
,
3217 static const struct display_timing sharp_ls020b1dd01d_timing
= {
3218 .pixelclock
= { 2000000, 4200000, 5000000 },
3219 .hactive
= { 240, 240, 240 },
3220 .hfront_porch
= { 66, 66, 66 },
3221 .hback_porch
= { 1, 1, 1 },
3222 .hsync_len
= { 1, 1, 1 },
3223 .vactive
= { 160, 160, 160 },
3224 .vfront_porch
= { 52, 52, 52 },
3225 .vback_porch
= { 6, 6, 6 },
3226 .vsync_len
= { 10, 10, 10 },
3227 .flags
= DISPLAY_FLAGS_HSYNC_HIGH
| DISPLAY_FLAGS_VSYNC_LOW
,
3230 static const struct panel_desc sharp_ls020b1dd01d
= {
3231 .timings
= &sharp_ls020b1dd01d_timing
,
3238 .bus_format
= MEDIA_BUS_FMT_RGB565_1X16
,
3239 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
3240 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
3241 | DRM_BUS_FLAG_SHARP_SIGNALS
,
3244 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode
= {
3247 .hsync_start
= 800 + 1,
3248 .hsync_end
= 800 + 1 + 64,
3249 .htotal
= 800 + 1 + 64 + 64,
3251 .vsync_start
= 480 + 1,
3252 .vsync_end
= 480 + 1 + 23,
3253 .vtotal
= 480 + 1 + 23 + 22,
3257 static const struct panel_desc shelly_sca07010_bfn_lnn
= {
3258 .modes
= &shelly_sca07010_bfn_lnn_mode
,
3264 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
3267 static const struct drm_display_mode starry_kr070pe2t_mode
= {
3270 .hsync_start
= 800 + 209,
3271 .hsync_end
= 800 + 209 + 1,
3272 .htotal
= 800 + 209 + 1 + 45,
3274 .vsync_start
= 480 + 22,
3275 .vsync_end
= 480 + 22 + 1,
3276 .vtotal
= 480 + 22 + 1 + 22,
3280 static const struct panel_desc starry_kr070pe2t
= {
3281 .modes
= &starry_kr070pe2t_mode
,
3288 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3289 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE
,
3290 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3293 static const struct drm_display_mode starry_kr122ea0sra_mode
= {
3296 .hsync_start
= 1920 + 16,
3297 .hsync_end
= 1920 + 16 + 16,
3298 .htotal
= 1920 + 16 + 16 + 32,
3300 .vsync_start
= 1200 + 15,
3301 .vsync_end
= 1200 + 15 + 2,
3302 .vtotal
= 1200 + 15 + 2 + 18,
3304 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
3307 static const struct panel_desc starry_kr122ea0sra
= {
3308 .modes
= &starry_kr122ea0sra_mode
,
3315 .prepare
= 10 + 200,
3317 .unprepare
= 10 + 500,
3321 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode
= {
3324 .hsync_start
= 800 + 39,
3325 .hsync_end
= 800 + 39 + 47,
3326 .htotal
= 800 + 39 + 47 + 39,
3328 .vsync_start
= 480 + 13,
3329 .vsync_end
= 480 + 13 + 2,
3330 .vtotal
= 480 + 13 + 2 + 29,
3334 static const struct panel_desc tfc_s9700rtwv43tr_01b
= {
3335 .modes
= &tfc_s9700rtwv43tr_01b_mode
,
3342 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3343 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_POSEDGE
,
3346 static const struct display_timing tianma_tm070jdhg30_timing
= {
3347 .pixelclock
= { 62600000, 68200000, 78100000 },
3348 .hactive
= { 1280, 1280, 1280 },
3349 .hfront_porch
= { 15, 64, 159 },
3350 .hback_porch
= { 5, 5, 5 },
3351 .hsync_len
= { 1, 1, 256 },
3352 .vactive
= { 800, 800, 800 },
3353 .vfront_porch
= { 3, 40, 99 },
3354 .vback_porch
= { 2, 2, 2 },
3355 .vsync_len
= { 1, 1, 128 },
3356 .flags
= DISPLAY_FLAGS_DE_HIGH
,
3359 static const struct panel_desc tianma_tm070jdhg30
= {
3360 .timings
= &tianma_tm070jdhg30_timing
,
3367 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
3368 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3371 static const struct display_timing tianma_tm070rvhg71_timing
= {
3372 .pixelclock
= { 27700000, 29200000, 39600000 },
3373 .hactive
= { 800, 800, 800 },
3374 .hfront_porch
= { 12, 40, 212 },
3375 .hback_porch
= { 88, 88, 88 },
3376 .hsync_len
= { 1, 1, 40 },
3377 .vactive
= { 480, 480, 480 },
3378 .vfront_porch
= { 1, 13, 88 },
3379 .vback_porch
= { 32, 32, 32 },
3380 .vsync_len
= { 1, 1, 3 },
3381 .flags
= DISPLAY_FLAGS_DE_HIGH
,
3384 static const struct panel_desc tianma_tm070rvhg71
= {
3385 .timings
= &tianma_tm070rvhg71_timing
,
3392 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_SPWG
,
3393 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3396 static const struct drm_display_mode ti_nspire_cx_lcd_mode
[] = {
3400 .hsync_start
= 320 + 50,
3401 .hsync_end
= 320 + 50 + 6,
3402 .htotal
= 320 + 50 + 6 + 38,
3404 .vsync_start
= 240 + 3,
3405 .vsync_end
= 240 + 3 + 1,
3406 .vtotal
= 240 + 3 + 1 + 17,
3408 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
3412 static const struct panel_desc ti_nspire_cx_lcd_panel
= {
3413 .modes
= ti_nspire_cx_lcd_mode
,
3420 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3421 .bus_flags
= DRM_BUS_FLAG_PIXDATA_NEGEDGE
,
3424 static const struct drm_display_mode ti_nspire_classic_lcd_mode
[] = {
3428 .hsync_start
= 320 + 6,
3429 .hsync_end
= 320 + 6 + 6,
3430 .htotal
= 320 + 6 + 6 + 6,
3432 .vsync_start
= 240 + 0,
3433 .vsync_end
= 240 + 0 + 1,
3434 .vtotal
= 240 + 0 + 1 + 0,
3436 .flags
= DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
,
3440 static const struct panel_desc ti_nspire_classic_lcd_panel
= {
3441 .modes
= ti_nspire_classic_lcd_mode
,
3443 /* The grayscale panel has 8 bit for the color .. Y (black) */
3449 /* This is the grayscale bus format */
3450 .bus_format
= MEDIA_BUS_FMT_Y8_1X8
,
3451 .bus_flags
= DRM_BUS_FLAG_PIXDATA_POSEDGE
,
3454 static const struct drm_display_mode toshiba_lt089ac29000_mode
= {
3457 .hsync_start
= 1280 + 192,
3458 .hsync_end
= 1280 + 192 + 128,
3459 .htotal
= 1280 + 192 + 128 + 64,
3461 .vsync_start
= 768 + 20,
3462 .vsync_end
= 768 + 20 + 7,
3463 .vtotal
= 768 + 20 + 7 + 3,
3467 static const struct panel_desc toshiba_lt089ac29000
= {
3468 .modes
= &toshiba_lt089ac29000_mode
,
3474 .bus_format
= MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA
,
3475 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
3476 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3479 static const struct drm_display_mode tpk_f07a_0102_mode
= {
3482 .hsync_start
= 800 + 40,
3483 .hsync_end
= 800 + 40 + 128,
3484 .htotal
= 800 + 40 + 128 + 88,
3486 .vsync_start
= 480 + 10,
3487 .vsync_end
= 480 + 10 + 2,
3488 .vtotal
= 480 + 10 + 2 + 33,
3492 static const struct panel_desc tpk_f07a_0102
= {
3493 .modes
= &tpk_f07a_0102_mode
,
3499 .bus_flags
= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE
,
3502 static const struct drm_display_mode tpk_f10a_0102_mode
= {
3505 .hsync_start
= 1024 + 176,
3506 .hsync_end
= 1024 + 176 + 5,
3507 .htotal
= 1024 + 176 + 5 + 88,
3509 .vsync_start
= 600 + 20,
3510 .vsync_end
= 600 + 20 + 5,
3511 .vtotal
= 600 + 20 + 5 + 25,
3515 static const struct panel_desc tpk_f10a_0102
= {
3516 .modes
= &tpk_f10a_0102_mode
,
3524 static const struct display_timing urt_umsh_8596md_timing
= {
3525 .pixelclock
= { 33260000, 33260000, 33260000 },
3526 .hactive
= { 800, 800, 800 },
3527 .hfront_porch
= { 41, 41, 41 },
3528 .hback_porch
= { 216 - 128, 216 - 128, 216 - 128 },
3529 .hsync_len
= { 71, 128, 128 },
3530 .vactive
= { 480, 480, 480 },
3531 .vfront_porch
= { 10, 10, 10 },
3532 .vback_porch
= { 35 - 2, 35 - 2, 35 - 2 },
3533 .vsync_len
= { 2, 2, 2 },
3534 .flags
= DISPLAY_FLAGS_DE_HIGH
| DISPLAY_FLAGS_PIXDATA_NEGEDGE
|
3535 DISPLAY_FLAGS_HSYNC_LOW
| DISPLAY_FLAGS_VSYNC_LOW
,
3538 static const struct panel_desc urt_umsh_8596md_lvds
= {
3539 .timings
= &urt_umsh_8596md_timing
,
3546 .bus_format
= MEDIA_BUS_FMT_RGB666_1X7X3_SPWG
,
3547 .connector_type
= DRM_MODE_CONNECTOR_LVDS
,
3550 static const struct panel_desc urt_umsh_8596md_parallel
= {
3551 .timings
= &urt_umsh_8596md_timing
,
3558 .bus_format
= MEDIA_BUS_FMT_RGB666_1X18
,
3561 static const struct drm_display_mode vl050_8048nt_c01_mode
= {
3564 .hsync_start
= 800 + 210,
3565 .hsync_end
= 800 + 210 + 20,
3566 .htotal
= 800 + 210 + 20 + 46,
3568 .vsync_start
= 480 + 22,
3569 .vsync_end
= 480 + 22 + 10,
3570 .vtotal
= 480 + 22 + 10 + 23,
3572 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
3575 static const struct panel_desc vl050_8048nt_c01
= {
3576 .modes
= &vl050_8048nt_c01_mode
,
3583 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3584 .bus_flags
= DRM_BUS_FLAG_DE_HIGH
| DRM_BUS_FLAG_PIXDATA_POSEDGE
,
3587 static const struct drm_display_mode winstar_wf35ltiacd_mode
= {
3590 .hsync_start
= 320 + 20,
3591 .hsync_end
= 320 + 20 + 30,
3592 .htotal
= 320 + 20 + 30 + 38,
3594 .vsync_start
= 240 + 4,
3595 .vsync_end
= 240 + 4 + 3,
3596 .vtotal
= 240 + 4 + 3 + 15,
3598 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
3601 static const struct panel_desc winstar_wf35ltiacd
= {
3602 .modes
= &winstar_wf35ltiacd_mode
,
3609 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3612 static const struct drm_display_mode arm_rtsm_mode
[] = {
3616 .hsync_start
= 1024 + 24,
3617 .hsync_end
= 1024 + 24 + 136,
3618 .htotal
= 1024 + 24 + 136 + 160,
3620 .vsync_start
= 768 + 3,
3621 .vsync_end
= 768 + 3 + 6,
3622 .vtotal
= 768 + 3 + 6 + 29,
3624 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
3628 static const struct panel_desc arm_rtsm
= {
3629 .modes
= arm_rtsm_mode
,
3636 .bus_format
= MEDIA_BUS_FMT_RGB888_1X24
,
3639 static const struct of_device_id platform_of_match
[] = {
3641 .compatible
= "ampire,am-480272h3tmqw-t01h",
3642 .data
= &ire_am_480272h3tmqw_t01h
,
3644 .compatible
= "ampire,am800480r3tmqwa1h",
3645 .data
= &ire_am800480r3tmqwa1h
,
3647 .compatible
= "arm,rtsm-display",
3650 .compatible
= "armadeus,st0700-adapt",
3651 .data
= &armadeus_st0700_adapt
,
3653 .compatible
= "auo,b101aw03",
3654 .data
= &auo_b101aw03
,
3656 .compatible
= "auo,b101ean01",
3657 .data
= &auo_b101ean01
,
3659 .compatible
= "auo,b101xtn01",
3660 .data
= &auo_b101xtn01
,
3662 .compatible
= "auo,b116xa01",
3663 .data
= &auo_b116xak01
,
3665 .compatible
= "auo,b116xw03",
3666 .data
= &auo_b116xw03
,
3668 .compatible
= "auo,b133htn01",
3669 .data
= &auo_b133htn01
,
3671 .compatible
= "auo,b133xtn01",
3672 .data
= &auo_b133xtn01
,
3674 .compatible
= "auo,g070vvn01",
3675 .data
= &auo_g070vvn01
,
3677 .compatible
= "auo,g101evn010",
3678 .data
= &auo_g101evn010
,
3680 .compatible
= "auo,g104sn02",
3681 .data
= &auo_g104sn02
,
3683 .compatible
= "auo,g121ean01",
3684 .data
= &auo_g121ean01
,
3686 .compatible
= "auo,g133han01",
3687 .data
= &auo_g133han01
,
3689 .compatible
= "auo,g156xtn01",
3690 .data
= &auo_g156xtn01
,
3692 .compatible
= "auo,g185han01",
3693 .data
= &auo_g185han01
,
3695 .compatible
= "auo,g190ean01",
3696 .data
= &auo_g190ean01
,
3698 .compatible
= "auo,p320hvn03",
3699 .data
= &auo_p320hvn03
,
3701 .compatible
= "auo,t215hvn01",
3702 .data
= &auo_t215hvn01
,
3704 .compatible
= "avic,tm070ddh03",
3705 .data
= &avic_tm070ddh03
,
3707 .compatible
= "bananapi,s070wv20-ct16",
3708 .data
= &bananapi_s070wv20_ct16
,
3710 .compatible
= "boe,hv070wsa-100",
3711 .data
= &boe_hv070wsa
3713 .compatible
= "boe,nv101wxmn51",
3714 .data
= &boe_nv101wxmn51
,
3716 .compatible
= "boe,nv133fhm-n61",
3717 .data
= &boe_nv133fhm_n61
,
3719 .compatible
= "boe,nv133fhm-n62",
3720 .data
= &boe_nv133fhm_n61
,
3722 .compatible
= "boe,nv140fhmn49",
3723 .data
= &boe_nv140fhmn49
,
3725 .compatible
= "cdtech,s043wq26h-ct7",
3726 .data
= &cdtech_s043wq26h_ct7
,
3728 .compatible
= "cdtech,s070wv95-ct16",
3729 .data
= &cdtech_s070wv95_ct16
,
3731 .compatible
= "chunghwa,claa070wp03xg",
3732 .data
= &chunghwa_claa070wp03xg
,
3734 .compatible
= "chunghwa,claa101wa01a",
3735 .data
= &chunghwa_claa101wa01a
3737 .compatible
= "chunghwa,claa101wb01",
3738 .data
= &chunghwa_claa101wb01
3740 .compatible
= "dataimage,scf0700c48ggu18",
3741 .data
= &dataimage_scf0700c48ggu18
,
3743 .compatible
= "dlc,dlc0700yzg-1",
3744 .data
= &dlc_dlc0700yzg_1
,
3746 .compatible
= "dlc,dlc1010gig",
3747 .data
= &dlc_dlc1010gig
,
3749 .compatible
= "edt,et035012dm6",
3750 .data
= &edt_et035012dm6
,
3752 .compatible
= "edt,etm043080dh6gp",
3753 .data
= &edt_etm043080dh6gp
,
3755 .compatible
= "edt,etm0430g0dh6",
3756 .data
= &edt_etm0430g0dh6
,
3758 .compatible
= "edt,et057090dhu",
3759 .data
= &edt_et057090dhu
,
3761 .compatible
= "edt,et070080dh6",
3762 .data
= &edt_etm0700g0dh6
,
3764 .compatible
= "edt,etm0700g0dh6",
3765 .data
= &edt_etm0700g0dh6
,
3767 .compatible
= "edt,etm0700g0bdh6",
3768 .data
= &edt_etm0700g0bdh6
,
3770 .compatible
= "edt,etm0700g0edh6",
3771 .data
= &edt_etm0700g0bdh6
,
3773 .compatible
= "evervision,vgg804821",
3774 .data
= &evervision_vgg804821
,
3776 .compatible
= "foxlink,fl500wvr00-a0t",
3777 .data
= &foxlink_fl500wvr00_a0t
,
3779 .compatible
= "frida,frd350h54004",
3780 .data
= &frida_frd350h54004
,
3782 .compatible
= "friendlyarm,hd702e",
3783 .data
= &friendlyarm_hd702e
,
3785 .compatible
= "giantplus,gpg482739qs5",
3786 .data
= &giantplus_gpg482739qs5
3788 .compatible
= "giantplus,gpm940b0",
3789 .data
= &giantplus_gpm940b0
,
3791 .compatible
= "hannstar,hsd070pww1",
3792 .data
= &hannstar_hsd070pww1
,
3794 .compatible
= "hannstar,hsd100pxn1",
3795 .data
= &hannstar_hsd100pxn1
,
3797 .compatible
= "hit,tx23d38vm0caa",
3798 .data
= &hitachi_tx23d38vm0caa
3800 .compatible
= "innolux,at043tn24",
3801 .data
= &innolux_at043tn24
,
3803 .compatible
= "innolux,at070tn92",
3804 .data
= &innolux_at070tn92
,
3806 .compatible
= "innolux,g070y2-l01",
3807 .data
= &innolux_g070y2_l01
,
3809 .compatible
= "innolux,g101ice-l01",
3810 .data
= &innolux_g101ice_l01
3812 .compatible
= "innolux,g121i1-l01",
3813 .data
= &innolux_g121i1_l01
3815 .compatible
= "innolux,g121x1-l03",
3816 .data
= &innolux_g121x1_l03
,
3818 .compatible
= "innolux,n116bge",
3819 .data
= &innolux_n116bge
,
3821 .compatible
= "innolux,n156bge-l21",
3822 .data
= &innolux_n156bge_l21
,
3824 .compatible
= "innolux,p120zdg-bf1",
3825 .data
= &innolux_p120zdg_bf1
,
3827 .compatible
= "innolux,zj070na-01p",
3828 .data
= &innolux_zj070na_01p
,
3830 .compatible
= "ivo,m133nwf4-r0",
3831 .data
= &ivo_m133nwf4_r0
,
3833 .compatible
= "koe,tx14d24vm1bpa",
3834 .data
= &koe_tx14d24vm1bpa
,
3836 .compatible
= "koe,tx31d200vm0baa",
3837 .data
= &koe_tx31d200vm0baa
,
3839 .compatible
= "kyo,tcg121xglp",
3840 .data
= &kyo_tcg121xglp
,
3842 .compatible
= "lemaker,bl035-rgb-002",
3843 .data
= &lemaker_bl035_rgb_002
,
3845 .compatible
= "lg,lb070wv8",
3846 .data
= &lg_lb070wv8
,
3848 .compatible
= "lg,lp079qx1-sp0v",
3849 .data
= &lg_lp079qx1_sp0v
,
3851 .compatible
= "lg,lp097qx1-spa1",
3852 .data
= &lg_lp097qx1_spa1
,
3854 .compatible
= "lg,lp120up1",
3855 .data
= &lg_lp120up1
,
3857 .compatible
= "lg,lp129qe",
3858 .data
= &lg_lp129qe
,
3860 .compatible
= "logicpd,type28",
3861 .data
= &logicpd_type_28
,
3863 .compatible
= "logictechno,lt161010-2nhc",
3864 .data
= &logictechno_lt161010_2nh
,
3866 .compatible
= "logictechno,lt161010-2nhr",
3867 .data
= &logictechno_lt161010_2nh
,
3869 .compatible
= "logictechno,lt170410-2whc",
3870 .data
= &logictechno_lt170410_2whc
,
3872 .compatible
= "mitsubishi,aa070mc01-ca1",
3873 .data
= &mitsubishi_aa070mc01
,
3875 .compatible
= "nec,nl12880bc20-05",
3876 .data
= &nec_nl12880bc20_05
,
3878 .compatible
= "nec,nl4827hc19-05b",
3879 .data
= &nec_nl4827hc19_05b
,
3881 .compatible
= "netron-dy,e231732",
3882 .data
= &netron_dy_e231732
,
3884 .compatible
= "neweast,wjfh116008a",
3885 .data
= &neweast_wjfh116008a
,
3887 .compatible
= "newhaven,nhd-4.3-480272ef-atxl",
3888 .data
= &newhaven_nhd_43_480272ef_atxl
,
3890 .compatible
= "nlt,nl192108ac18-02d",
3891 .data
= &nlt_nl192108ac18_02d
,
3893 .compatible
= "nvd,9128",
3896 .compatible
= "okaya,rs800480t-7x0gp",
3897 .data
= &okaya_rs800480t_7x0gp
,
3899 .compatible
= "olimex,lcd-olinuxino-43-ts",
3900 .data
= &olimex_lcd_olinuxino_43ts
,
3902 .compatible
= "ontat,yx700wv03",
3903 .data
= &ontat_yx700wv03
,
3905 .compatible
= "ortustech,com37h3m05dtc",
3906 .data
= &ortustech_com37h3m
,
3908 .compatible
= "ortustech,com37h3m99dtc",
3909 .data
= &ortustech_com37h3m
,
3911 .compatible
= "ortustech,com43h4m85ulc",
3912 .data
= &ortustech_com43h4m85ulc
,
3914 .compatible
= "osddisplays,osd070t1718-19ts",
3915 .data
= &osddisplays_osd070t1718_19ts
,
3917 .compatible
= "pda,91-00156-a0",
3918 .data
= &pda_91_00156_a0
,
3920 .compatible
= "qiaodian,qd43003c0-40",
3921 .data
= &qd43003c0_40
,
3923 .compatible
= "rocktech,rk070er9427",
3924 .data
= &rocktech_rk070er9427
,
3926 .compatible
= "rocktech,rk101ii01d-ct",
3927 .data
= &rocktech_rk101ii01d_ct
,
3929 .compatible
= "samsung,lsn122dl01-c01",
3930 .data
= &samsung_lsn122dl01_c01
,
3932 .compatible
= "samsung,ltn101nt05",
3933 .data
= &samsung_ltn101nt05
,
3935 .compatible
= "samsung,ltn140at29-301",
3936 .data
= &samsung_ltn140at29_301
,
3938 .compatible
= "satoz,sat050at40h12r2",
3939 .data
= &satoz_sat050at40h12r2
,
3941 .compatible
= "sharp,ld-d5116z01b",
3942 .data
= &sharp_ld_d5116z01b
,
3944 .compatible
= "sharp,lq035q7db03",
3945 .data
= &sharp_lq035q7db03
,
3947 .compatible
= "sharp,lq070y3dg3b",
3948 .data
= &sharp_lq070y3dg3b
,
3950 .compatible
= "sharp,lq101k1ly04",
3951 .data
= &sharp_lq101k1ly04
,
3953 .compatible
= "sharp,lq123p1jx31",
3954 .data
= &sharp_lq123p1jx31
,
3956 .compatible
= "sharp,ls020b1dd01d",
3957 .data
= &sharp_ls020b1dd01d
,
3959 .compatible
= "shelly,sca07010-bfn-lnn",
3960 .data
= &shelly_sca07010_bfn_lnn
,
3962 .compatible
= "starry,kr070pe2t",
3963 .data
= &starry_kr070pe2t
,
3965 .compatible
= "starry,kr122ea0sra",
3966 .data
= &starry_kr122ea0sra
,
3968 .compatible
= "tfc,s9700rtwv43tr-01b",
3969 .data
= &tfc_s9700rtwv43tr_01b
,
3971 .compatible
= "tianma,tm070jdhg30",
3972 .data
= &tianma_tm070jdhg30
,
3974 .compatible
= "tianma,tm070rvhg71",
3975 .data
= &tianma_tm070rvhg71
,
3977 .compatible
= "ti,nspire-cx-lcd-panel",
3978 .data
= &ti_nspire_cx_lcd_panel
,
3980 .compatible
= "ti,nspire-classic-lcd-panel",
3981 .data
= &ti_nspire_classic_lcd_panel
,
3983 .compatible
= "toshiba,lt089ac29000",
3984 .data
= &toshiba_lt089ac29000
,
3986 .compatible
= "tpk,f07a-0102",
3987 .data
= &tpk_f07a_0102
,
3989 .compatible
= "tpk,f10a-0102",
3990 .data
= &tpk_f10a_0102
,
3992 .compatible
= "urt,umsh-8596md-t",
3993 .data
= &urt_umsh_8596md_parallel
,
3995 .compatible
= "urt,umsh-8596md-1t",
3996 .data
= &urt_umsh_8596md_parallel
,
3998 .compatible
= "urt,umsh-8596md-7t",
3999 .data
= &urt_umsh_8596md_parallel
,
4001 .compatible
= "urt,umsh-8596md-11t",
4002 .data
= &urt_umsh_8596md_lvds
,
4004 .compatible
= "urt,umsh-8596md-19t",
4005 .data
= &urt_umsh_8596md_lvds
,
4007 .compatible
= "urt,umsh-8596md-20t",
4008 .data
= &urt_umsh_8596md_parallel
,
4010 .compatible
= "vxt,vl050-8048nt-c01",
4011 .data
= &vl050_8048nt_c01
,
4013 .compatible
= "winstar,wf35ltiacd",
4014 .data
= &winstar_wf35ltiacd
,
4016 /* Must be the last entry */
4017 .compatible
= "panel-dpi",
4023 MODULE_DEVICE_TABLE(of
, platform_of_match
);
4025 static int panel_simple_platform_probe(struct platform_device
*pdev
)
4027 const struct of_device_id
*id
;
4029 id
= of_match_node(platform_of_match
, pdev
->dev
.of_node
);
4033 return panel_simple_probe(&pdev
->dev
, id
->data
);
4036 static int panel_simple_platform_remove(struct platform_device
*pdev
)
4038 return panel_simple_remove(&pdev
->dev
);
4041 static void panel_simple_platform_shutdown(struct platform_device
*pdev
)
4043 panel_simple_shutdown(&pdev
->dev
);
4046 static struct platform_driver panel_simple_platform_driver
= {
4048 .name
= "panel-simple",
4049 .of_match_table
= platform_of_match
,
4051 .probe
= panel_simple_platform_probe
,
4052 .remove
= panel_simple_platform_remove
,
4053 .shutdown
= panel_simple_platform_shutdown
,
4056 struct panel_desc_dsi
{
4057 struct panel_desc desc
;
4059 unsigned long flags
;
4060 enum mipi_dsi_pixel_format format
;
4064 static const struct drm_display_mode auo_b080uan01_mode
= {
4067 .hsync_start
= 1200 + 62,
4068 .hsync_end
= 1200 + 62 + 4,
4069 .htotal
= 1200 + 62 + 4 + 62,
4071 .vsync_start
= 1920 + 9,
4072 .vsync_end
= 1920 + 9 + 2,
4073 .vtotal
= 1920 + 9 + 2 + 8,
4077 static const struct panel_desc_dsi auo_b080uan01
= {
4079 .modes
= &auo_b080uan01_mode
,
4087 .flags
= MIPI_DSI_MODE_VIDEO
| MIPI_DSI_CLOCK_NON_CONTINUOUS
,
4088 .format
= MIPI_DSI_FMT_RGB888
,
4092 static const struct drm_display_mode boe_tv080wum_nl0_mode
= {
4095 .hsync_start
= 1200 + 120,
4096 .hsync_end
= 1200 + 120 + 20,
4097 .htotal
= 1200 + 120 + 20 + 21,
4099 .vsync_start
= 1920 + 21,
4100 .vsync_end
= 1920 + 21 + 3,
4101 .vtotal
= 1920 + 21 + 3 + 18,
4103 .flags
= DRM_MODE_FLAG_NVSYNC
| DRM_MODE_FLAG_NHSYNC
,
4106 static const struct panel_desc_dsi boe_tv080wum_nl0
= {
4108 .modes
= &boe_tv080wum_nl0_mode
,
4115 .flags
= MIPI_DSI_MODE_VIDEO
|
4116 MIPI_DSI_MODE_VIDEO_BURST
|
4117 MIPI_DSI_MODE_VIDEO_SYNC_PULSE
,
4118 .format
= MIPI_DSI_FMT_RGB888
,
4122 static const struct drm_display_mode lg_ld070wx3_sl01_mode
= {
4125 .hsync_start
= 800 + 32,
4126 .hsync_end
= 800 + 32 + 1,
4127 .htotal
= 800 + 32 + 1 + 57,
4129 .vsync_start
= 1280 + 28,
4130 .vsync_end
= 1280 + 28 + 1,
4131 .vtotal
= 1280 + 28 + 1 + 14,
4135 static const struct panel_desc_dsi lg_ld070wx3_sl01
= {
4137 .modes
= &lg_ld070wx3_sl01_mode
,
4145 .flags
= MIPI_DSI_MODE_VIDEO
| MIPI_DSI_CLOCK_NON_CONTINUOUS
,
4146 .format
= MIPI_DSI_FMT_RGB888
,
4150 static const struct drm_display_mode lg_lh500wx1_sd03_mode
= {
4153 .hsync_start
= 720 + 12,
4154 .hsync_end
= 720 + 12 + 4,
4155 .htotal
= 720 + 12 + 4 + 112,
4157 .vsync_start
= 1280 + 8,
4158 .vsync_end
= 1280 + 8 + 4,
4159 .vtotal
= 1280 + 8 + 4 + 12,
4163 static const struct panel_desc_dsi lg_lh500wx1_sd03
= {
4165 .modes
= &lg_lh500wx1_sd03_mode
,
4173 .flags
= MIPI_DSI_MODE_VIDEO
,
4174 .format
= MIPI_DSI_FMT_RGB888
,
4178 static const struct drm_display_mode panasonic_vvx10f004b00_mode
= {
4181 .hsync_start
= 1920 + 154,
4182 .hsync_end
= 1920 + 154 + 16,
4183 .htotal
= 1920 + 154 + 16 + 32,
4185 .vsync_start
= 1200 + 17,
4186 .vsync_end
= 1200 + 17 + 2,
4187 .vtotal
= 1200 + 17 + 2 + 16,
4191 static const struct panel_desc_dsi panasonic_vvx10f004b00
= {
4193 .modes
= &panasonic_vvx10f004b00_mode
,
4201 .flags
= MIPI_DSI_MODE_VIDEO
| MIPI_DSI_MODE_VIDEO_SYNC_PULSE
|
4202 MIPI_DSI_CLOCK_NON_CONTINUOUS
,
4203 .format
= MIPI_DSI_FMT_RGB888
,
4207 static const struct drm_display_mode lg_acx467akm_7_mode
= {
4210 .hsync_start
= 1080 + 2,
4211 .hsync_end
= 1080 + 2 + 2,
4212 .htotal
= 1080 + 2 + 2 + 2,
4214 .vsync_start
= 1920 + 2,
4215 .vsync_end
= 1920 + 2 + 2,
4216 .vtotal
= 1920 + 2 + 2 + 2,
4220 static const struct panel_desc_dsi lg_acx467akm_7
= {
4222 .modes
= &lg_acx467akm_7_mode
,
4231 .format
= MIPI_DSI_FMT_RGB888
,
4235 static const struct drm_display_mode osd101t2045_53ts_mode
= {
4238 .hsync_start
= 1920 + 112,
4239 .hsync_end
= 1920 + 112 + 16,
4240 .htotal
= 1920 + 112 + 16 + 32,
4242 .vsync_start
= 1200 + 16,
4243 .vsync_end
= 1200 + 16 + 2,
4244 .vtotal
= 1200 + 16 + 2 + 16,
4246 .flags
= DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
,
4249 static const struct panel_desc_dsi osd101t2045_53ts
= {
4251 .modes
= &osd101t2045_53ts_mode
,
4259 .flags
= MIPI_DSI_MODE_VIDEO
| MIPI_DSI_MODE_VIDEO_BURST
|
4260 MIPI_DSI_MODE_VIDEO_SYNC_PULSE
|
4261 MIPI_DSI_MODE_EOT_PACKET
,
4262 .format
= MIPI_DSI_FMT_RGB888
,
4266 static const struct of_device_id dsi_of_match
[] = {
4268 .compatible
= "auo,b080uan01",
4269 .data
= &auo_b080uan01
4271 .compatible
= "boe,tv080wum-nl0",
4272 .data
= &boe_tv080wum_nl0
4274 .compatible
= "lg,ld070wx3-sl01",
4275 .data
= &lg_ld070wx3_sl01
4277 .compatible
= "lg,lh500wx1-sd03",
4278 .data
= &lg_lh500wx1_sd03
4280 .compatible
= "panasonic,vvx10f004b00",
4281 .data
= &panasonic_vvx10f004b00
4283 .compatible
= "lg,acx467akm-7",
4284 .data
= &lg_acx467akm_7
4286 .compatible
= "osddisplays,osd101t2045-53ts",
4287 .data
= &osd101t2045_53ts
4292 MODULE_DEVICE_TABLE(of
, dsi_of_match
);
4294 static int panel_simple_dsi_probe(struct mipi_dsi_device
*dsi
)
4296 const struct panel_desc_dsi
*desc
;
4297 const struct of_device_id
*id
;
4300 id
= of_match_node(dsi_of_match
, dsi
->dev
.of_node
);
4306 err
= panel_simple_probe(&dsi
->dev
, &desc
->desc
);
4310 dsi
->mode_flags
= desc
->flags
;
4311 dsi
->format
= desc
->format
;
4312 dsi
->lanes
= desc
->lanes
;
4314 err
= mipi_dsi_attach(dsi
);
4316 struct panel_simple
*panel
= dev_get_drvdata(&dsi
->dev
);
4318 drm_panel_remove(&panel
->base
);
4324 static int panel_simple_dsi_remove(struct mipi_dsi_device
*dsi
)
4328 err
= mipi_dsi_detach(dsi
);
4330 dev_err(&dsi
->dev
, "failed to detach from DSI host: %d\n", err
);
4332 return panel_simple_remove(&dsi
->dev
);
4335 static void panel_simple_dsi_shutdown(struct mipi_dsi_device
*dsi
)
4337 panel_simple_shutdown(&dsi
->dev
);
4340 static struct mipi_dsi_driver panel_simple_dsi_driver
= {
4342 .name
= "panel-simple-dsi",
4343 .of_match_table
= dsi_of_match
,
4345 .probe
= panel_simple_dsi_probe
,
4346 .remove
= panel_simple_dsi_remove
,
4347 .shutdown
= panel_simple_dsi_shutdown
,
4350 static int __init
panel_simple_init(void)
4354 err
= platform_driver_register(&panel_simple_platform_driver
);
4358 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI
)) {
4359 err
= mipi_dsi_driver_register(&panel_simple_dsi_driver
);
4366 module_init(panel_simple_init
);
4368 static void __exit
panel_simple_exit(void)
4370 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI
))
4371 mipi_dsi_driver_unregister(&panel_simple_dsi_driver
);
4373 platform_driver_unregister(&panel_simple_platform_driver
);
4375 module_exit(panel_simple_exit
);
4377 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4378 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4379 MODULE_LICENSE("GPL and additional rights");