drivers/gpu/drm/panfrost/panfrost_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
   3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
   4 /* Copyright 2019 Collabora ltd. */
   5 #include <linux/bitfield.h>
   6 #include <linux/bitmap.h>
   7 #include <linux/delay.h>
   8 #include <linux/dma-mapping.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/platform_device.h>
  13
  14 #include "panfrost_device.h"
  15 #include "panfrost_features.h"
  16 #include "panfrost_issues.h"
  17 #include "panfrost_gpu.h"
  18 #include "panfrost_perfcnt.h"
  19 #include "panfrost_regs.h"
  20
  21 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data)
  22 {
  23         struct panfrost_device *pfdev = data;
  24         u32 state = gpu_read(pfdev, GPU_INT_STAT);
  25         u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS);
  26
  27         if (!state)
  28                 return IRQ_NONE;
  29
  30         if (state & GPU_IRQ_MASK_ERROR) {
  31                 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32;
  32                 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO);
  33
  34                 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n",
  35                          fault_status & 0xFF, panfrost_exception_name(pfdev, fault_status),
  36                          address);
  37
  38                 if (state & GPU_IRQ_MULTIPLE_FAULT)
  39                         dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n");
  40
  41                 gpu_write(pfdev, GPU_INT_MASK, 0);
  42         }
  43
  44         if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED)
  45                 panfrost_perfcnt_sample_done(pfdev);
  46
  47         if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED)
  48                 panfrost_perfcnt_clean_cache_done(pfdev);
  49
  50         gpu_write(pfdev, GPU_INT_CLEAR, state);
  51
  52         return IRQ_HANDLED;
  53 }
  54
  55 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev)
  56 {
  57         int ret;
  58         u32 val;
  59
  60         gpu_write(pfdev, GPU_INT_MASK, 0);
  61         gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED);
  62         gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET);
  63
  64         ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT,
  65                 val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
  66
  67         if (ret) {
  68                 dev_err(pfdev->dev, "gpu soft reset timed out\n");
  69                 return ret;
  70         }
  71
  72         gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL);
  73         gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL);
  74
  75         return 0;
  76 }
  77
  78 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
  79 {
  80         u32 quirks = 0;
  81
  82         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) ||
  83             panfrost_has_hw_issue(pfdev, HW_ISSUE_11035))
  84                 quirks |= SC_LS_PAUSEBUFFER_DISABLE;
  85
  86         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327))
  87                 quirks |= SC_SDC_DISABLE_OQ_DISCARD;
  88
  89         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797))
  90                 quirks |= SC_ENABLE_TEXGRD_FLAGS;
  91
  92         if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) {
  93                 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */
  94                         quirks |= SC_LS_ATTR_CHECK_DISABLE;
  95                 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */
  96                         quirks |= SC_LS_ALLOW_ATTR_TYPES;
  97         }
  98
  99         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
 100                 quirks |= SC_TLS_HASH_ENABLE;
 101
 102         if (quirks)
 103                 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks);
 104
 105
 106         quirks = gpu_read(pfdev, GPU_TILER_CONFIG);
 107
 108         /* Set tiler clock gate override if required */
 109         if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953))
 110                 quirks |= TC_CLOCK_GATE_OVERRIDE;
 111
 112         gpu_write(pfdev, GPU_TILER_CONFIG, quirks);
 113
 114
 115         quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG);
 116
 117         /* Limit read & write ID width for AXI */
 118         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG))
 119                 quirks &= ~(L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS |
 120                             L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES);
 121         else
 122                 quirks &= ~(L2_MMU_CONFIG_LIMIT_EXTERNAL_READS |
 123                             L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES);
 124
 125         gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks);
 126
 127         quirks = 0;
 128         if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) &&
 129             pfdev->features.revision >= 0x2000)
 130                 quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
 131         else if (panfrost_model_eq(pfdev, 0x6000) &&
 132                  pfdev->features.coherency_features == COHERENCY_ACE)
 133                 quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
 134                            JM_FORCE_COHERENCY_FEATURES_SHIFT;
 135
 136         if (quirks)
 137                 gpu_write(pfdev, GPU_JM_CONFIG, quirks);
 138 }
 139
 140 #define MAX_HW_REVS 6
 141
 142 struct panfrost_model {
 143         const char *name;
 144         u32 id;
 145         u32 id_mask;
 146         u64 features;
 147         u64 issues;
 148         struct {
 149                 u32 revision;
 150                 u64 issues;
 151         } revs[MAX_HW_REVS];
 152 };
 153
 154 #define GPU_MODEL(_name, _id, ...) \
 155 {\
 156         .name = __stringify(_name),                             \
 157         .id = _id,                                              \
 158         .features = hw_features_##_name,                        \
 159         .issues = hw_issues_##_name,                            \
 160         .revs = { __VA_ARGS__ },                                \
 161 }
 162
 163 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \
 164 {\
 165         .revision = (_rev) << 12 | (_p) << 4 | (_s),            \
 166         .issues = hw_issues_##name##_r##_rev##p##_p##stat,      \
 167 }
 168 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, )
 169
 170 static const struct panfrost_model gpu_models[] = {
 171         /* T60x has an oddball version */
 172         GPU_MODEL(t600, 0x600,
 173                 GPU_REV_EXT(t600, 0, 0, 1, _15dev0)),
 174         GPU_MODEL(t620, 0x620,
 175                 GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)),
 176         GPU_MODEL(t720, 0x720),
 177         GPU_MODEL(t760, 0x750,
 178                 GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1),
 179                 GPU_REV_EXT(t760, 0, 1, 0, _50rel0),
 180                 GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)),
 181         GPU_MODEL(t820, 0x820),
 182         GPU_MODEL(t830, 0x830),
 183         GPU_MODEL(t860, 0x860),
 184         GPU_MODEL(t880, 0x880),
 185
 186         GPU_MODEL(g71, 0x6000,
 187                 GPU_REV_EXT(g71, 0, 0, 1, _05dev0)),
 188         GPU_MODEL(g72, 0x6001),
 189         GPU_MODEL(g51, 0x7000),
 190         GPU_MODEL(g76, 0x7001),
 191         GPU_MODEL(g52, 0x7002),
 192         GPU_MODEL(g31, 0x7003,
 193                 GPU_REV(g31, 1, 0)),
 194 };
 195
 196 static void panfrost_gpu_init_features(struct panfrost_device *pfdev)
 197 {
 198         u32 gpu_id, num_js, major, minor, status, rev;
 199         const char *name = "unknown";
 200         u64 hw_feat = 0;
 201         u64 hw_issues = hw_issues_all;
 202         const struct panfrost_model *model;
 203         int i;
 204
 205         pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES);
 206         pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES);
 207         pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES);
 208         pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES);
 209         pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES);
 210         pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES);
 211         pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
 212         for (i = 0; i < 4; i++)
 213                 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
 214
 215         pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT);
 216
 217         pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT);
 218         num_js = hweight32(pfdev->features.js_present);
 219         for (i = 0; i < num_js; i++)
 220                 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i));
 221
 222         pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO);
 223         pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32;
 224
 225         pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO);
 226         pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32;
 227
 228         pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO);
 229         pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32;
 230         pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present);
 231
 232         pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
 233         pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
 234
 235         gpu_id = gpu_read(pfdev, GPU_ID);
 236         pfdev->features.revision = gpu_id & 0xffff;
 237         pfdev->features.id = gpu_id >> 16;
 238
 239         /* The T60x has an oddball ID value. Fix it up to the standard Midgard
 240          * format so we (and userspace) don't have to special case it.
 241          */
 242         if (pfdev->features.id == 0x6956)
 243                 pfdev->features.id = 0x0600;
 244
 245         major = (pfdev->features.revision >> 12) & 0xf;
 246         minor = (pfdev->features.revision >> 4) & 0xff;
 247         status = pfdev->features.revision & 0xf;
 248         rev = pfdev->features.revision;
 249
 250         gpu_id = pfdev->features.id;
 251
 252         for (model = gpu_models; model->name; model++) {
 253                 int best = -1;
 254
 255                 if (!panfrost_model_eq(pfdev, model->id))
 256                         continue;
 257
 258                 name = model->name;
 259                 hw_feat = model->features;
 260                 hw_issues |= model->issues;
 261                 for (i = 0; i < MAX_HW_REVS; i++) {
 262                         if (model->revs[i].revision == rev) {
 263                                 best = i;
 264                                 break;
 265                         } else if (model->revs[i].revision == (rev & ~0xf))
 266                                 best = i;
 267                 }
 268
 269                 if (best >= 0)
 270                         hw_issues |= model->revs[best].issues;
 271
 272                 break;
 273         }
 274
 275         bitmap_from_u64(pfdev->features.hw_features, hw_feat);
 276         bitmap_from_u64(pfdev->features.hw_issues, hw_issues);
 277
 278         dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x",
 279                  name, gpu_id, major, minor, status);
 280         dev_info(pfdev->dev, "features: %64pb, issues: %64pb",
 281                  pfdev->features.hw_features,
 282                  pfdev->features.hw_issues);
 283
 284         dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x",
 285                  pfdev->features.l2_features,
 286                  pfdev->features.core_features,
 287                  pfdev->features.tiler_features,
 288                  pfdev->features.mem_features,
 289                  pfdev->features.mmu_features,
 290                  pfdev->features.as_present,
 291                  pfdev->features.js_present);
 292
 293         dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx",
 294                  pfdev->features.shader_present, pfdev->features.l2_present);
 295 }
 296
 297 void panfrost_gpu_power_on(struct panfrost_device *pfdev)
 298 {
 299         int ret;
 300         u32 val;
 301
 302         /* Just turn on everything for now */
 303         gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
 304         ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
 305                 val, val == pfdev->features.l2_present, 100, 1000);
 306
 307         gpu_write(pfdev, STACK_PWRON_LO, pfdev->features.stack_present);
 308         ret |= readl_relaxed_poll_timeout(pfdev->iomem + STACK_READY_LO,
 309                 val, val == pfdev->features.stack_present, 100, 1000);
 310
 311         gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
 312         ret |= readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
 313                 val, val == pfdev->features.shader_present, 100, 1000);
 314
 315         gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
 316         ret |= readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
 317                 val, val == pfdev->features.tiler_present, 100, 1000);
 318
 319         if (ret)
 320                 dev_err(pfdev->dev, "error powering up gpu");
 321 }
 322
 323 void panfrost_gpu_power_off(struct panfrost_device *pfdev)
 324 {
 325         gpu_write(pfdev, TILER_PWROFF_LO, 0);
 326         gpu_write(pfdev, SHADER_PWROFF_LO, 0);
 327         gpu_write(pfdev, STACK_PWROFF_LO, 0);
 328         gpu_write(pfdev, L2_PWROFF_LO, 0);
 329 }
 330
 331 int panfrost_gpu_init(struct panfrost_device *pfdev)
 332 {
 333         int err, irq;
 334
 335         err = panfrost_gpu_soft_reset(pfdev);
 336         if (err)
 337                 return err;
 338
 339         panfrost_gpu_init_features(pfdev);
 340
 341         dma_set_mask_and_coherent(pfdev->dev,
 342                 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features)));
 343
 344         irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu");
 345         if (irq <= 0)
 346                 return -ENODEV;
 347
 348         err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler,
 349                                IRQF_SHARED, "gpu", pfdev);
 350         if (err) {
 351                 dev_err(pfdev->dev, "failed to request gpu irq");
 352                 return err;
 353         }
 354
 355         panfrost_gpu_init_quirks(pfdev);
 356         panfrost_gpu_power_on(pfdev);
 357
 358         return 0;
 359 }
 360
 361 void panfrost_gpu_fini(struct panfrost_device *pfdev)
 362 {
 363         panfrost_gpu_power_off(pfdev);
 364 }
 365
 366 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev)
 367 {
 368         if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION))
 369                 return gpu_read(pfdev, GPU_LATEST_FLUSH_ID);
 370         return 0;
 371 }