2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc
*crtc
,
35 struct drm_display_mode
*mode
,
36 struct drm_display_mode
*adjusted_mode
)
38 struct drm_device
*dev
= crtc
->dev
;
39 struct radeon_device
*rdev
= dev
->dev_private
;
40 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args
;
42 int index
= GetIndexIntoMasterTable(COMMAND
, SetCRTC_OverScan
);
45 memset(&args
, 0, sizeof(args
));
47 args
.ucCRTC
= radeon_crtc
->crtc_id
;
49 switch (radeon_crtc
->rmx_type
) {
51 args
.usOverscanTop
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- mode
->crtc_vdisplay
) / 2);
52 args
.usOverscanBottom
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- mode
->crtc_vdisplay
) / 2);
53 args
.usOverscanLeft
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- mode
->crtc_hdisplay
) / 2);
54 args
.usOverscanRight
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- mode
->crtc_hdisplay
) / 2);
57 a1
= mode
->crtc_vdisplay
* adjusted_mode
->crtc_hdisplay
;
58 a2
= adjusted_mode
->crtc_vdisplay
* mode
->crtc_hdisplay
;
61 args
.usOverscanLeft
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- (a2
/ mode
->crtc_vdisplay
)) / 2);
62 args
.usOverscanRight
= cpu_to_le16((adjusted_mode
->crtc_hdisplay
- (a2
/ mode
->crtc_vdisplay
)) / 2);
64 args
.usOverscanTop
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- (a1
/ mode
->crtc_hdisplay
)) / 2);
65 args
.usOverscanBottom
= cpu_to_le16((adjusted_mode
->crtc_vdisplay
- (a1
/ mode
->crtc_hdisplay
)) / 2);
70 args
.usOverscanRight
= cpu_to_le16(radeon_crtc
->h_border
);
71 args
.usOverscanLeft
= cpu_to_le16(radeon_crtc
->h_border
);
72 args
.usOverscanBottom
= cpu_to_le16(radeon_crtc
->v_border
);
73 args
.usOverscanTop
= cpu_to_le16(radeon_crtc
->v_border
);
76 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
79 static void atombios_scaler_setup(struct drm_crtc
*crtc
)
81 struct drm_device
*dev
= crtc
->dev
;
82 struct radeon_device
*rdev
= dev
->dev_private
;
83 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
84 ENABLE_SCALER_PS_ALLOCATION args
;
85 int index
= GetIndexIntoMasterTable(COMMAND
, EnableScaler
);
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
89 bool is_tv
= false, is_cv
= false;
90 struct drm_encoder
*encoder
;
92 if (!ASIC_IS_AVIVO(rdev
) && radeon_crtc
->crtc_id
)
95 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
97 if (encoder
->crtc
== crtc
) {
98 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
99 if (radeon_encoder
->active_device
& ATOM_DEVICE_TV_SUPPORT
) {
100 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
101 tv_std
= tv_dac
->tv_std
;
107 memset(&args
, 0, sizeof(args
));
109 args
.ucScaler
= radeon_crtc
->crtc_id
;
115 args
.ucTVStandard
= ATOM_TV_NTSC
;
118 args
.ucTVStandard
= ATOM_TV_PAL
;
121 args
.ucTVStandard
= ATOM_TV_PALM
;
124 args
.ucTVStandard
= ATOM_TV_PAL60
;
127 args
.ucTVStandard
= ATOM_TV_NTSCJ
;
129 case TV_STD_SCART_PAL
:
130 args
.ucTVStandard
= ATOM_TV_PAL
; /* ??? */
133 args
.ucTVStandard
= ATOM_TV_SECAM
;
136 args
.ucTVStandard
= ATOM_TV_PALCN
;
139 args
.ucEnable
= SCALER_ENABLE_MULTITAP_MODE
;
141 args
.ucTVStandard
= ATOM_TV_CV
;
142 args
.ucEnable
= SCALER_ENABLE_MULTITAP_MODE
;
144 switch (radeon_crtc
->rmx_type
) {
146 args
.ucEnable
= ATOM_SCALER_EXPANSION
;
149 args
.ucEnable
= ATOM_SCALER_CENTER
;
152 args
.ucEnable
= ATOM_SCALER_EXPANSION
;
155 if (ASIC_IS_AVIVO(rdev
))
156 args
.ucEnable
= ATOM_SCALER_DISABLE
;
158 args
.ucEnable
= ATOM_SCALER_CENTER
;
162 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
164 && rdev
->family
>= CHIP_RV515
&& rdev
->family
<= CHIP_R580
) {
165 atom_rv515_force_tv_scaler(rdev
, radeon_crtc
);
169 static void atombios_lock_crtc(struct drm_crtc
*crtc
, int lock
)
171 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
172 struct drm_device
*dev
= crtc
->dev
;
173 struct radeon_device
*rdev
= dev
->dev_private
;
175 GetIndexIntoMasterTable(COMMAND
, UpdateCRTC_DoubleBufferRegisters
);
176 ENABLE_CRTC_PS_ALLOCATION args
;
178 memset(&args
, 0, sizeof(args
));
180 args
.ucCRTC
= radeon_crtc
->crtc_id
;
181 args
.ucEnable
= lock
;
183 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
186 static void atombios_enable_crtc(struct drm_crtc
*crtc
, int state
)
188 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
189 struct drm_device
*dev
= crtc
->dev
;
190 struct radeon_device
*rdev
= dev
->dev_private
;
191 int index
= GetIndexIntoMasterTable(COMMAND
, EnableCRTC
);
192 ENABLE_CRTC_PS_ALLOCATION args
;
194 memset(&args
, 0, sizeof(args
));
196 args
.ucCRTC
= radeon_crtc
->crtc_id
;
197 args
.ucEnable
= state
;
199 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
202 static void atombios_enable_crtc_memreq(struct drm_crtc
*crtc
, int state
)
204 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
205 struct drm_device
*dev
= crtc
->dev
;
206 struct radeon_device
*rdev
= dev
->dev_private
;
207 int index
= GetIndexIntoMasterTable(COMMAND
, EnableCRTCMemReq
);
208 ENABLE_CRTC_PS_ALLOCATION args
;
210 memset(&args
, 0, sizeof(args
));
212 args
.ucCRTC
= radeon_crtc
->crtc_id
;
213 args
.ucEnable
= state
;
215 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
218 static void atombios_blank_crtc(struct drm_crtc
*crtc
, int state
)
220 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
221 struct drm_device
*dev
= crtc
->dev
;
222 struct radeon_device
*rdev
= dev
->dev_private
;
223 int index
= GetIndexIntoMasterTable(COMMAND
, BlankCRTC
);
224 BLANK_CRTC_PS_ALLOCATION args
;
226 memset(&args
, 0, sizeof(args
));
228 args
.ucCRTC
= radeon_crtc
->crtc_id
;
229 args
.ucBlanking
= state
;
231 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
234 void atombios_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
236 struct drm_device
*dev
= crtc
->dev
;
237 struct radeon_device
*rdev
= dev
->dev_private
;
238 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
241 case DRM_MODE_DPMS_ON
:
242 radeon_crtc
->enabled
= true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev
);
245 atombios_enable_crtc(crtc
, ATOM_ENABLE
);
246 if (ASIC_IS_DCE3(rdev
))
247 atombios_enable_crtc_memreq(crtc
, ATOM_ENABLE
);
248 atombios_blank_crtc(crtc
, ATOM_DISABLE
);
249 drm_vblank_post_modeset(dev
, radeon_crtc
->crtc_id
);
250 radeon_crtc_load_lut(crtc
);
252 case DRM_MODE_DPMS_STANDBY
:
253 case DRM_MODE_DPMS_SUSPEND
:
254 case DRM_MODE_DPMS_OFF
:
255 drm_vblank_pre_modeset(dev
, radeon_crtc
->crtc_id
);
256 if (radeon_crtc
->enabled
)
257 atombios_blank_crtc(crtc
, ATOM_ENABLE
);
258 if (ASIC_IS_DCE3(rdev
))
259 atombios_enable_crtc_memreq(crtc
, ATOM_DISABLE
);
260 atombios_enable_crtc(crtc
, ATOM_DISABLE
);
261 radeon_crtc
->enabled
= false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev
);
269 atombios_set_crtc_dtd_timing(struct drm_crtc
*crtc
,
270 struct drm_display_mode
*mode
)
272 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
273 struct drm_device
*dev
= crtc
->dev
;
274 struct radeon_device
*rdev
= dev
->dev_private
;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args
;
276 int index
= GetIndexIntoMasterTable(COMMAND
, SetCRTC_UsingDTDTiming
);
279 memset(&args
, 0, sizeof(args
));
280 args
.usH_Size
= cpu_to_le16(mode
->crtc_hdisplay
- (radeon_crtc
->h_border
* 2));
281 args
.usH_Blanking_Time
=
282 cpu_to_le16(mode
->crtc_hblank_end
- mode
->crtc_hdisplay
+ (radeon_crtc
->h_border
* 2));
283 args
.usV_Size
= cpu_to_le16(mode
->crtc_vdisplay
- (radeon_crtc
->v_border
* 2));
284 args
.usV_Blanking_Time
=
285 cpu_to_le16(mode
->crtc_vblank_end
- mode
->crtc_vdisplay
+ (radeon_crtc
->v_border
* 2));
286 args
.usH_SyncOffset
=
287 cpu_to_le16(mode
->crtc_hsync_start
- mode
->crtc_hdisplay
+ radeon_crtc
->h_border
);
289 cpu_to_le16(mode
->crtc_hsync_end
- mode
->crtc_hsync_start
);
290 args
.usV_SyncOffset
=
291 cpu_to_le16(mode
->crtc_vsync_start
- mode
->crtc_vdisplay
+ radeon_crtc
->v_border
);
293 cpu_to_le16(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
);
294 args
.ucH_Border
= radeon_crtc
->h_border
;
295 args
.ucV_Border
= radeon_crtc
->v_border
;
297 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
298 misc
|= ATOM_VSYNC_POLARITY
;
299 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
300 misc
|= ATOM_HSYNC_POLARITY
;
301 if (mode
->flags
& DRM_MODE_FLAG_CSYNC
)
302 misc
|= ATOM_COMPOSITESYNC
;
303 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
304 misc
|= ATOM_INTERLACE
;
305 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
306 misc
|= ATOM_DOUBLE_CLOCK_MODE
;
308 args
.susModeMiscInfo
.usAccess
= cpu_to_le16(misc
);
309 args
.ucCRTC
= radeon_crtc
->crtc_id
;
311 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
314 static void atombios_crtc_set_timing(struct drm_crtc
*crtc
,
315 struct drm_display_mode
*mode
)
317 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
318 struct drm_device
*dev
= crtc
->dev
;
319 struct radeon_device
*rdev
= dev
->dev_private
;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args
;
321 int index
= GetIndexIntoMasterTable(COMMAND
, SetCRTC_Timing
);
324 memset(&args
, 0, sizeof(args
));
325 args
.usH_Total
= cpu_to_le16(mode
->crtc_htotal
);
326 args
.usH_Disp
= cpu_to_le16(mode
->crtc_hdisplay
);
327 args
.usH_SyncStart
= cpu_to_le16(mode
->crtc_hsync_start
);
329 cpu_to_le16(mode
->crtc_hsync_end
- mode
->crtc_hsync_start
);
330 args
.usV_Total
= cpu_to_le16(mode
->crtc_vtotal
);
331 args
.usV_Disp
= cpu_to_le16(mode
->crtc_vdisplay
);
332 args
.usV_SyncStart
= cpu_to_le16(mode
->crtc_vsync_start
);
334 cpu_to_le16(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
);
336 args
.ucOverscanRight
= radeon_crtc
->h_border
;
337 args
.ucOverscanLeft
= radeon_crtc
->h_border
;
338 args
.ucOverscanBottom
= radeon_crtc
->v_border
;
339 args
.ucOverscanTop
= radeon_crtc
->v_border
;
341 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
342 misc
|= ATOM_VSYNC_POLARITY
;
343 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
344 misc
|= ATOM_HSYNC_POLARITY
;
345 if (mode
->flags
& DRM_MODE_FLAG_CSYNC
)
346 misc
|= ATOM_COMPOSITESYNC
;
347 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
348 misc
|= ATOM_INTERLACE
;
349 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
350 misc
|= ATOM_DOUBLE_CLOCK_MODE
;
352 args
.susModeMiscInfo
.usAccess
= cpu_to_le16(misc
);
353 args
.ucCRTC
= radeon_crtc
->crtc_id
;
355 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
358 static void atombios_disable_ss(struct drm_crtc
*crtc
)
360 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
361 struct drm_device
*dev
= crtc
->dev
;
362 struct radeon_device
*rdev
= dev
->dev_private
;
365 if (ASIC_IS_DCE4(rdev
)) {
366 switch (radeon_crtc
->pll_id
) {
368 ss_cntl
= RREG32(EVERGREEN_P1PLL_SS_CNTL
);
369 ss_cntl
&= ~EVERGREEN_PxPLL_SS_EN
;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL
, ss_cntl
);
373 ss_cntl
= RREG32(EVERGREEN_P2PLL_SS_CNTL
);
374 ss_cntl
&= ~EVERGREEN_PxPLL_SS_EN
;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL
, ss_cntl
);
378 case ATOM_PPLL_INVALID
:
381 } else if (ASIC_IS_AVIVO(rdev
)) {
382 switch (radeon_crtc
->pll_id
) {
384 ss_cntl
= RREG32(AVIVO_P1PLL_INT_SS_CNTL
);
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL
, ss_cntl
);
389 ss_cntl
= RREG32(AVIVO_P2PLL_INT_SS_CNTL
);
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL
, ss_cntl
);
394 case ATOM_PPLL_INVALID
:
401 union atom_enable_ss
{
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss
;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2
;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1
;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2
;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3
;
409 static void atombios_crtc_program_ss(struct drm_crtc
*crtc
,
412 struct radeon_atom_ss
*ss
)
414 struct drm_device
*dev
= crtc
->dev
;
415 struct radeon_device
*rdev
= dev
->dev_private
;
416 int index
= GetIndexIntoMasterTable(COMMAND
, EnableSpreadSpectrumOnPPLL
);
417 union atom_enable_ss args
;
419 memset(&args
, 0, sizeof(args
));
421 if (ASIC_IS_DCE5(rdev
)) {
422 args
.v3
.usSpreadSpectrumAmountFrac
= cpu_to_le16(0);
423 args
.v3
.ucSpreadSpectrumType
= ss
->type
& ATOM_SS_CENTRE_SPREAD_MODE_MASK
;
426 args
.v3
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V3_P1PLL
;
427 args
.v3
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
428 args
.v3
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
431 args
.v3
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V3_P2PLL
;
432 args
.v3
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
433 args
.v3
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
436 args
.v3
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V3_DCPLL
;
437 args
.v3
.usSpreadSpectrumAmount
= cpu_to_le16(0);
438 args
.v3
.usSpreadSpectrumStep
= cpu_to_le16(0);
440 case ATOM_PPLL_INVALID
:
443 args
.v3
.ucEnable
= enable
;
444 if ((ss
->percentage
== 0) || (ss
->type
& ATOM_EXTERNAL_SS_MASK
))
445 args
.v3
.ucEnable
= ATOM_DISABLE
;
446 } else if (ASIC_IS_DCE4(rdev
)) {
447 args
.v2
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
448 args
.v2
.ucSpreadSpectrumType
= ss
->type
& ATOM_SS_CENTRE_SPREAD_MODE_MASK
;
451 args
.v2
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V2_P1PLL
;
452 args
.v2
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
453 args
.v2
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
456 args
.v2
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V2_P2PLL
;
457 args
.v2
.usSpreadSpectrumAmount
= cpu_to_le16(ss
->amount
);
458 args
.v2
.usSpreadSpectrumStep
= cpu_to_le16(ss
->step
);
461 args
.v2
.ucSpreadSpectrumType
|= ATOM_PPLL_SS_TYPE_V2_DCPLL
;
462 args
.v2
.usSpreadSpectrumAmount
= cpu_to_le16(0);
463 args
.v2
.usSpreadSpectrumStep
= cpu_to_le16(0);
465 case ATOM_PPLL_INVALID
:
468 args
.v2
.ucEnable
= enable
;
469 if ((ss
->percentage
== 0) || (ss
->type
& ATOM_EXTERNAL_SS_MASK
))
470 args
.v2
.ucEnable
= ATOM_DISABLE
;
471 } else if (ASIC_IS_DCE3(rdev
)) {
472 args
.v1
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
473 args
.v1
.ucSpreadSpectrumType
= ss
->type
& ATOM_SS_CENTRE_SPREAD_MODE_MASK
;
474 args
.v1
.ucSpreadSpectrumStep
= ss
->step
;
475 args
.v1
.ucSpreadSpectrumDelay
= ss
->delay
;
476 args
.v1
.ucSpreadSpectrumRange
= ss
->range
;
477 args
.v1
.ucPpll
= pll_id
;
478 args
.v1
.ucEnable
= enable
;
479 } else if (ASIC_IS_AVIVO(rdev
)) {
480 if ((enable
== ATOM_DISABLE
) || (ss
->percentage
== 0) ||
481 (ss
->type
& ATOM_EXTERNAL_SS_MASK
)) {
482 atombios_disable_ss(crtc
);
485 args
.lvds_ss_2
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
486 args
.lvds_ss_2
.ucSpreadSpectrumType
= ss
->type
& ATOM_SS_CENTRE_SPREAD_MODE_MASK
;
487 args
.lvds_ss_2
.ucSpreadSpectrumStep
= ss
->step
;
488 args
.lvds_ss_2
.ucSpreadSpectrumDelay
= ss
->delay
;
489 args
.lvds_ss_2
.ucSpreadSpectrumRange
= ss
->range
;
490 args
.lvds_ss_2
.ucEnable
= enable
;
492 if ((enable
== ATOM_DISABLE
) || (ss
->percentage
== 0) ||
493 (ss
->type
& ATOM_EXTERNAL_SS_MASK
)) {
494 atombios_disable_ss(crtc
);
497 args
.lvds_ss
.usSpreadSpectrumPercentage
= cpu_to_le16(ss
->percentage
);
498 args
.lvds_ss
.ucSpreadSpectrumType
= ss
->type
& ATOM_SS_CENTRE_SPREAD_MODE_MASK
;
499 args
.lvds_ss
.ucSpreadSpectrumStepSize_Delay
= (ss
->step
& 3) << 2;
500 args
.lvds_ss
.ucSpreadSpectrumStepSize_Delay
|= (ss
->delay
& 7) << 4;
501 args
.lvds_ss
.ucEnable
= enable
;
503 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
506 union adjust_pixel_clock
{
507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1
;
508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3
;
511 static u32
atombios_adjust_pll(struct drm_crtc
*crtc
,
512 struct drm_display_mode
*mode
,
513 struct radeon_pll
*pll
,
515 struct radeon_atom_ss
*ss
)
517 struct drm_device
*dev
= crtc
->dev
;
518 struct radeon_device
*rdev
= dev
->dev_private
;
519 struct drm_encoder
*encoder
= NULL
;
520 struct radeon_encoder
*radeon_encoder
= NULL
;
521 struct drm_connector
*connector
= NULL
;
522 u32 adjusted_clock
= mode
->clock
;
523 int encoder_mode
= 0;
524 u32 dp_clock
= mode
->clock
;
527 /* reset the pll flags */
530 if (ASIC_IS_AVIVO(rdev
)) {
531 if ((rdev
->family
== CHIP_RS600
) ||
532 (rdev
->family
== CHIP_RS690
) ||
533 (rdev
->family
== CHIP_RS740
))
534 pll
->flags
|= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
535 RADEON_PLL_PREFER_CLOSEST_LOWER
);
537 if (ASIC_IS_DCE32(rdev
) && mode
->clock
> 200000) /* range limits??? */
538 pll
->flags
|= RADEON_PLL_PREFER_HIGH_FB_DIV
;
540 pll
->flags
|= RADEON_PLL_PREFER_LOW_REF_DIV
;
542 if (rdev
->family
< CHIP_RV770
)
543 pll
->flags
|= RADEON_PLL_PREFER_MINM_OVER_MAXP
;
545 pll
->flags
|= RADEON_PLL_LEGACY
;
547 if (mode
->clock
> 200000) /* range limits??? */
548 pll
->flags
|= RADEON_PLL_PREFER_HIGH_FB_DIV
;
550 pll
->flags
|= RADEON_PLL_PREFER_LOW_REF_DIV
;
553 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
554 if (encoder
->crtc
== crtc
) {
555 radeon_encoder
= to_radeon_encoder(encoder
);
556 connector
= radeon_get_connector_for_encoder(encoder
);
558 bpc
= connector
->display_info
.bpc
;
559 encoder_mode
= atombios_get_encoder_mode(encoder
);
560 if ((radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
| ATOM_DEVICE_DFP_SUPPORT
)) ||
561 radeon_encoder_is_dp_bridge(encoder
)) {
563 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
564 struct radeon_connector_atom_dig
*dig_connector
=
565 radeon_connector
->con_priv
;
567 dp_clock
= dig_connector
->dp_clock
;
571 /* use recommended ref_div for ss */
572 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
575 pll
->flags
|= RADEON_PLL_USE_REF_DIV
;
576 pll
->reference_div
= ss
->refdiv
;
577 if (ASIC_IS_AVIVO(rdev
))
578 pll
->flags
|= RADEON_PLL_USE_FRAC_FB_DIV
;
583 if (ASIC_IS_AVIVO(rdev
)) {
584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
585 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
)
586 adjusted_clock
= mode
->clock
* 2;
587 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
588 pll
->flags
|= RADEON_PLL_PREFER_CLOSEST_LOWER
;
589 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
590 pll
->flags
|= RADEON_PLL_IS_LCD
;
592 if (encoder
->encoder_type
!= DRM_MODE_ENCODER_DAC
)
593 pll
->flags
|= RADEON_PLL_NO_ODD_POST_DIV
;
594 if (encoder
->encoder_type
== DRM_MODE_ENCODER_LVDS
)
595 pll
->flags
|= RADEON_PLL_USE_REF_DIV
;
601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
602 * accordingly based on the encoder/transmitter to work around
603 * special hw requirements.
605 if (ASIC_IS_DCE3(rdev
)) {
606 union adjust_pixel_clock args
;
610 index
= GetIndexIntoMasterTable(COMMAND
, AdjustDisplayPll
);
611 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
,
613 return adjusted_clock
;
615 memset(&args
, 0, sizeof(args
));
622 args
.v1
.usPixelClock
= cpu_to_le16(mode
->clock
/ 10);
623 args
.v1
.ucTransmitterID
= radeon_encoder
->encoder_id
;
624 args
.v1
.ucEncodeMode
= encoder_mode
;
625 if (ss_enabled
&& ss
->percentage
)
627 ADJUST_DISPLAY_CONFIG_SS_ENABLE
;
629 atom_execute_table(rdev
->mode_info
.atom_context
,
630 index
, (uint32_t *)&args
);
631 adjusted_clock
= le16_to_cpu(args
.v1
.usPixelClock
) * 10;
634 args
.v3
.sInput
.usPixelClock
= cpu_to_le16(mode
->clock
/ 10);
635 args
.v3
.sInput
.ucTransmitterID
= radeon_encoder
->encoder_id
;
636 args
.v3
.sInput
.ucEncodeMode
= encoder_mode
;
637 args
.v3
.sInput
.ucDispPllConfig
= 0;
638 if (ss_enabled
&& ss
->percentage
)
639 args
.v3
.sInput
.ucDispPllConfig
|=
640 DISPPLL_CONFIG_SS_ENABLE
;
641 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
) ||
642 radeon_encoder_is_dp_bridge(encoder
)) {
643 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
644 if (encoder_mode
== ATOM_ENCODER_MODE_DP
) {
645 args
.v3
.sInput
.ucDispPllConfig
|=
646 DISPPLL_CONFIG_COHERENT_MODE
;
648 args
.v3
.sInput
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
650 if (encoder_mode
== ATOM_ENCODER_MODE_HDMI
) {
651 /* deep color support */
652 args
.v3
.sInput
.usPixelClock
=
653 cpu_to_le16((mode
->clock
* bpc
/ 8) / 10);
655 if (dig
->coherent_mode
)
656 args
.v3
.sInput
.ucDispPllConfig
|=
657 DISPPLL_CONFIG_COHERENT_MODE
;
658 if (mode
->clock
> 165000)
659 args
.v3
.sInput
.ucDispPllConfig
|=
660 DISPPLL_CONFIG_DUAL_LINK
;
662 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
663 if (encoder_mode
== ATOM_ENCODER_MODE_DP
) {
664 args
.v3
.sInput
.ucDispPllConfig
|=
665 DISPPLL_CONFIG_COHERENT_MODE
;
667 args
.v3
.sInput
.usPixelClock
= cpu_to_le16(dp_clock
/ 10);
668 } else if (encoder_mode
!= ATOM_ENCODER_MODE_LVDS
) {
669 if (mode
->clock
> 165000)
670 args
.v3
.sInput
.ucDispPllConfig
|=
671 DISPPLL_CONFIG_DUAL_LINK
;
674 atom_execute_table(rdev
->mode_info
.atom_context
,
675 index
, (uint32_t *)&args
);
676 adjusted_clock
= le32_to_cpu(args
.v3
.sOutput
.ulDispPllFreq
) * 10;
677 if (args
.v3
.sOutput
.ucRefDiv
) {
678 pll
->flags
|= RADEON_PLL_USE_FRAC_FB_DIV
;
679 pll
->flags
|= RADEON_PLL_USE_REF_DIV
;
680 pll
->reference_div
= args
.v3
.sOutput
.ucRefDiv
;
682 if (args
.v3
.sOutput
.ucPostDiv
) {
683 pll
->flags
|= RADEON_PLL_USE_FRAC_FB_DIV
;
684 pll
->flags
|= RADEON_PLL_USE_POST_DIV
;
685 pll
->post_div
= args
.v3
.sOutput
.ucPostDiv
;
689 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
690 return adjusted_clock
;
694 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
695 return adjusted_clock
;
698 return adjusted_clock
;
701 union set_pixel_clock
{
702 SET_PIXEL_CLOCK_PS_ALLOCATION base
;
703 PIXEL_CLOCK_PARAMETERS v1
;
704 PIXEL_CLOCK_PARAMETERS_V2 v2
;
705 PIXEL_CLOCK_PARAMETERS_V3 v3
;
706 PIXEL_CLOCK_PARAMETERS_V5 v5
;
707 PIXEL_CLOCK_PARAMETERS_V6 v6
;
710 /* on DCE5, make sure the voltage is high enough to support the
713 static void atombios_crtc_set_dcpll(struct drm_crtc
*crtc
,
716 struct drm_device
*dev
= crtc
->dev
;
717 struct radeon_device
*rdev
= dev
->dev_private
;
720 union set_pixel_clock args
;
722 memset(&args
, 0, sizeof(args
));
724 index
= GetIndexIntoMasterTable(COMMAND
, SetPixelClock
);
725 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
,
733 /* if the default dcpll clock is specified,
734 * SetPixelClock provides the dividers
736 args
.v5
.ucCRTC
= ATOM_CRTC_INVALID
;
737 args
.v5
.usPixelClock
= cpu_to_le16(dispclk
);
738 args
.v5
.ucPpll
= ATOM_DCPLL
;
741 /* if the default dcpll clock is specified,
742 * SetPixelClock provides the dividers
744 args
.v6
.ulDispEngClkFreq
= cpu_to_le32(dispclk
);
745 args
.v6
.ucPpll
= ATOM_DCPLL
;
748 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
753 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
756 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
759 static void atombios_crtc_program_pll(struct drm_crtc
*crtc
,
771 struct radeon_atom_ss
*ss
)
773 struct drm_device
*dev
= crtc
->dev
;
774 struct radeon_device
*rdev
= dev
->dev_private
;
776 int index
= GetIndexIntoMasterTable(COMMAND
, SetPixelClock
);
777 union set_pixel_clock args
;
779 memset(&args
, 0, sizeof(args
));
781 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
,
789 if (clock
== ATOM_DISABLE
)
791 args
.v1
.usPixelClock
= cpu_to_le16(clock
/ 10);
792 args
.v1
.usRefDiv
= cpu_to_le16(ref_div
);
793 args
.v1
.usFbDiv
= cpu_to_le16(fb_div
);
794 args
.v1
.ucFracFbDiv
= frac_fb_div
;
795 args
.v1
.ucPostDiv
= post_div
;
796 args
.v1
.ucPpll
= pll_id
;
797 args
.v1
.ucCRTC
= crtc_id
;
798 args
.v1
.ucRefDivSrc
= 1;
801 args
.v2
.usPixelClock
= cpu_to_le16(clock
/ 10);
802 args
.v2
.usRefDiv
= cpu_to_le16(ref_div
);
803 args
.v2
.usFbDiv
= cpu_to_le16(fb_div
);
804 args
.v2
.ucFracFbDiv
= frac_fb_div
;
805 args
.v2
.ucPostDiv
= post_div
;
806 args
.v2
.ucPpll
= pll_id
;
807 args
.v2
.ucCRTC
= crtc_id
;
808 args
.v2
.ucRefDivSrc
= 1;
811 args
.v3
.usPixelClock
= cpu_to_le16(clock
/ 10);
812 args
.v3
.usRefDiv
= cpu_to_le16(ref_div
);
813 args
.v3
.usFbDiv
= cpu_to_le16(fb_div
);
814 args
.v3
.ucFracFbDiv
= frac_fb_div
;
815 args
.v3
.ucPostDiv
= post_div
;
816 args
.v3
.ucPpll
= pll_id
;
817 args
.v3
.ucMiscInfo
= (pll_id
<< 2);
818 if (ss_enabled
&& (ss
->type
& ATOM_EXTERNAL_SS_MASK
))
819 args
.v3
.ucMiscInfo
|= PIXEL_CLOCK_MISC_REF_DIV_SRC
;
820 args
.v3
.ucTransmitterId
= encoder_id
;
821 args
.v3
.ucEncoderMode
= encoder_mode
;
824 args
.v5
.ucCRTC
= crtc_id
;
825 args
.v5
.usPixelClock
= cpu_to_le16(clock
/ 10);
826 args
.v5
.ucRefDiv
= ref_div
;
827 args
.v5
.usFbDiv
= cpu_to_le16(fb_div
);
828 args
.v5
.ulFbDivDecFrac
= cpu_to_le32(frac_fb_div
* 100000);
829 args
.v5
.ucPostDiv
= post_div
;
830 args
.v5
.ucMiscInfo
= 0; /* HDMI depth, etc. */
831 if (ss_enabled
&& (ss
->type
& ATOM_EXTERNAL_SS_MASK
))
832 args
.v5
.ucMiscInfo
|= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC
;
836 args
.v5
.ucMiscInfo
|= PIXEL_CLOCK_V5_MISC_HDMI_24BPP
;
839 args
.v5
.ucMiscInfo
|= PIXEL_CLOCK_V5_MISC_HDMI_30BPP
;
842 args
.v5
.ucTransmitterID
= encoder_id
;
843 args
.v5
.ucEncoderMode
= encoder_mode
;
844 args
.v5
.ucPpll
= pll_id
;
847 args
.v6
.ulCrtcPclkFreq
.ucCRTC
= crtc_id
;
848 args
.v6
.ulCrtcPclkFreq
.ulPixelClock
= cpu_to_le32(clock
/ 10);
849 args
.v6
.ucRefDiv
= ref_div
;
850 args
.v6
.usFbDiv
= cpu_to_le16(fb_div
);
851 args
.v6
.ulFbDivDecFrac
= cpu_to_le32(frac_fb_div
* 100000);
852 args
.v6
.ucPostDiv
= post_div
;
853 args
.v6
.ucMiscInfo
= 0; /* HDMI depth, etc. */
854 if (ss_enabled
&& (ss
->type
& ATOM_EXTERNAL_SS_MASK
))
855 args
.v6
.ucMiscInfo
|= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC
;
859 args
.v6
.ucMiscInfo
|= PIXEL_CLOCK_V6_MISC_HDMI_24BPP
;
862 args
.v6
.ucMiscInfo
|= PIXEL_CLOCK_V6_MISC_HDMI_30BPP
;
865 args
.v6
.ucMiscInfo
|= PIXEL_CLOCK_V6_MISC_HDMI_36BPP
;
868 args
.v6
.ucMiscInfo
|= PIXEL_CLOCK_V6_MISC_HDMI_48BPP
;
871 args
.v6
.ucTransmitterID
= encoder_id
;
872 args
.v6
.ucEncoderMode
= encoder_mode
;
873 args
.v6
.ucPpll
= pll_id
;
876 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
881 DRM_ERROR("Unknown table version %d %d\n", frev
, crev
);
885 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
888 static void atombios_crtc_set_pll(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
)
890 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
891 struct drm_device
*dev
= crtc
->dev
;
892 struct radeon_device
*rdev
= dev
->dev_private
;
893 struct drm_encoder
*encoder
= NULL
;
894 struct radeon_encoder
*radeon_encoder
= NULL
;
895 u32 pll_clock
= mode
->clock
;
896 u32 ref_div
= 0, fb_div
= 0, frac_fb_div
= 0, post_div
= 0;
897 struct radeon_pll
*pll
;
899 int encoder_mode
= 0;
900 struct radeon_atom_ss ss
;
901 bool ss_enabled
= false;
904 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
905 if (encoder
->crtc
== crtc
) {
906 radeon_encoder
= to_radeon_encoder(encoder
);
907 encoder_mode
= atombios_get_encoder_mode(encoder
);
915 switch (radeon_crtc
->pll_id
) {
917 pll
= &rdev
->clock
.p1pll
;
920 pll
= &rdev
->clock
.p2pll
;
923 case ATOM_PPLL_INVALID
:
925 pll
= &rdev
->clock
.dcpll
;
929 if (radeon_encoder
->active_device
&
930 (ATOM_DEVICE_LCD_SUPPORT
| ATOM_DEVICE_DFP_SUPPORT
)) {
931 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
932 struct drm_connector
*connector
=
933 radeon_get_connector_for_encoder(encoder
);
934 struct radeon_connector
*radeon_connector
=
935 to_radeon_connector(connector
);
936 struct radeon_connector_atom_dig
*dig_connector
=
937 radeon_connector
->con_priv
;
939 bpc
= connector
->display_info
.bpc
;
941 switch (encoder_mode
) {
942 case ATOM_ENCODER_MODE_DP
:
944 dp_clock
= dig_connector
->dp_clock
/ 10;
945 if (ASIC_IS_DCE4(rdev
))
947 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
948 ASIC_INTERNAL_SS_ON_DP
,
951 if (dp_clock
== 16200) {
953 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
957 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
961 radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
965 case ATOM_ENCODER_MODE_LVDS
:
966 if (ASIC_IS_DCE4(rdev
))
967 ss_enabled
= radeon_atombios_get_asic_ss_info(rdev
, &ss
,
971 ss_enabled
= radeon_atombios_get_ppll_ss_info(rdev
, &ss
,
974 case ATOM_ENCODER_MODE_DVI
:
975 if (ASIC_IS_DCE4(rdev
))
977 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
978 ASIC_INTERNAL_SS_ON_TMDS
,
981 case ATOM_ENCODER_MODE_HDMI
:
982 if (ASIC_IS_DCE4(rdev
))
984 radeon_atombios_get_asic_ss_info(rdev
, &ss
,
985 ASIC_INTERNAL_SS_ON_HDMI
,
993 /* adjust pixel clock as needed */
994 adjusted_clock
= atombios_adjust_pll(crtc
, mode
, pll
, ss_enabled
, &ss
);
996 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
997 /* TV seems to prefer the legacy algo on some boards */
998 radeon_compute_pll_legacy(pll
, adjusted_clock
, &pll_clock
, &fb_div
, &frac_fb_div
,
999 &ref_div
, &post_div
);
1000 else if (ASIC_IS_AVIVO(rdev
))
1001 radeon_compute_pll_avivo(pll
, adjusted_clock
, &pll_clock
, &fb_div
, &frac_fb_div
,
1002 &ref_div
, &post_div
);
1004 radeon_compute_pll_legacy(pll
, adjusted_clock
, &pll_clock
, &fb_div
, &frac_fb_div
,
1005 &ref_div
, &post_div
);
1007 atombios_crtc_program_ss(crtc
, ATOM_DISABLE
, radeon_crtc
->pll_id
, &ss
);
1009 atombios_crtc_program_pll(crtc
, radeon_crtc
->crtc_id
, radeon_crtc
->pll_id
,
1010 encoder_mode
, radeon_encoder
->encoder_id
, mode
->clock
,
1011 ref_div
, fb_div
, frac_fb_div
, post_div
, bpc
, ss_enabled
, &ss
);
1014 /* calculate ss amount and step size */
1015 if (ASIC_IS_DCE4(rdev
)) {
1017 u32 amount
= (((fb_div
* 10) + frac_fb_div
) * ss
.percentage
) / 10000;
1018 ss
.amount
= (amount
/ 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK
;
1019 ss
.amount
|= ((amount
- (amount
/ 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT
) &
1020 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK
;
1021 if (ss
.type
& ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD
)
1022 step_size
= (4 * amount
* ref_div
* (ss
.rate
* 2048)) /
1023 (125 * 25 * pll
->reference_freq
/ 100);
1025 step_size
= (2 * amount
* ref_div
* (ss
.rate
* 2048)) /
1026 (125 * 25 * pll
->reference_freq
/ 100);
1027 ss
.step
= step_size
;
1030 atombios_crtc_program_ss(crtc
, ATOM_ENABLE
, radeon_crtc
->pll_id
, &ss
);
1034 static int dce4_crtc_do_set_base(struct drm_crtc
*crtc
,
1035 struct drm_framebuffer
*fb
,
1036 int x
, int y
, int atomic
)
1038 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1039 struct drm_device
*dev
= crtc
->dev
;
1040 struct radeon_device
*rdev
= dev
->dev_private
;
1041 struct radeon_framebuffer
*radeon_fb
;
1042 struct drm_framebuffer
*target_fb
;
1043 struct drm_gem_object
*obj
;
1044 struct radeon_bo
*rbo
;
1045 uint64_t fb_location
;
1046 uint32_t fb_format
, fb_pitch_pixels
, tiling_flags
;
1047 u32 fb_swap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE
);
1048 u32 tmp
, viewport_w
, viewport_h
;
1052 if (!atomic
&& !crtc
->fb
) {
1053 DRM_DEBUG_KMS("No FB bound\n");
1058 radeon_fb
= to_radeon_framebuffer(fb
);
1062 radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
1063 target_fb
= crtc
->fb
;
1066 /* If atomic, assume fb object is pinned & idle & fenced and
1067 * just update base pointers
1069 obj
= radeon_fb
->obj
;
1070 rbo
= gem_to_radeon_bo(obj
);
1071 r
= radeon_bo_reserve(rbo
, false);
1072 if (unlikely(r
!= 0))
1076 fb_location
= radeon_bo_gpu_offset(rbo
);
1078 r
= radeon_bo_pin(rbo
, RADEON_GEM_DOMAIN_VRAM
, &fb_location
);
1079 if (unlikely(r
!= 0)) {
1080 radeon_bo_unreserve(rbo
);
1085 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
1086 radeon_bo_unreserve(rbo
);
1088 switch (target_fb
->bits_per_pixel
) {
1090 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP
) |
1091 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED
));
1094 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP
) |
1095 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555
));
1098 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP
) |
1099 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565
));
1101 fb_swap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16
);
1106 fb_format
= (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP
) |
1107 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888
));
1109 fb_swap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32
);
1113 DRM_ERROR("Unsupported screen depth %d\n",
1114 target_fb
->bits_per_pixel
);
1118 if (tiling_flags
& RADEON_TILING_MACRO
)
1119 fb_format
|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1
);
1120 else if (tiling_flags
& RADEON_TILING_MICRO
)
1121 fb_format
|= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1
);
1123 switch (radeon_crtc
->crtc_id
) {
1125 WREG32(AVIVO_D1VGA_CONTROL
, 0);
1128 WREG32(AVIVO_D2VGA_CONTROL
, 0);
1131 WREG32(EVERGREEN_D3VGA_CONTROL
, 0);
1134 WREG32(EVERGREEN_D4VGA_CONTROL
, 0);
1137 WREG32(EVERGREEN_D5VGA_CONTROL
, 0);
1140 WREG32(EVERGREEN_D6VGA_CONTROL
, 0);
1146 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
1147 upper_32_bits(fb_location
));
1148 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ radeon_crtc
->crtc_offset
,
1149 upper_32_bits(fb_location
));
1150 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
1151 (u32
)fb_location
& EVERGREEN_GRPH_SURFACE_ADDRESS_MASK
);
1152 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
1153 (u32
) fb_location
& EVERGREEN_GRPH_SURFACE_ADDRESS_MASK
);
1154 WREG32(EVERGREEN_GRPH_CONTROL
+ radeon_crtc
->crtc_offset
, fb_format
);
1155 WREG32(EVERGREEN_GRPH_SWAP_CONTROL
+ radeon_crtc
->crtc_offset
, fb_swap
);
1157 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X
+ radeon_crtc
->crtc_offset
, 0);
1158 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y
+ radeon_crtc
->crtc_offset
, 0);
1159 WREG32(EVERGREEN_GRPH_X_START
+ radeon_crtc
->crtc_offset
, 0);
1160 WREG32(EVERGREEN_GRPH_Y_START
+ radeon_crtc
->crtc_offset
, 0);
1161 WREG32(EVERGREEN_GRPH_X_END
+ radeon_crtc
->crtc_offset
, target_fb
->width
);
1162 WREG32(EVERGREEN_GRPH_Y_END
+ radeon_crtc
->crtc_offset
, target_fb
->height
);
1164 fb_pitch_pixels
= target_fb
->pitch
/ (target_fb
->bits_per_pixel
/ 8);
1165 WREG32(EVERGREEN_GRPH_PITCH
+ radeon_crtc
->crtc_offset
, fb_pitch_pixels
);
1166 WREG32(EVERGREEN_GRPH_ENABLE
+ radeon_crtc
->crtc_offset
, 1);
1168 WREG32(EVERGREEN_DESKTOP_HEIGHT
+ radeon_crtc
->crtc_offset
,
1169 crtc
->mode
.vdisplay
);
1172 WREG32(EVERGREEN_VIEWPORT_START
+ radeon_crtc
->crtc_offset
,
1174 viewport_w
= crtc
->mode
.hdisplay
;
1175 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
1176 WREG32(EVERGREEN_VIEWPORT_SIZE
+ radeon_crtc
->crtc_offset
,
1177 (viewport_w
<< 16) | viewport_h
);
1179 /* pageflip setup */
1180 /* make sure flip is at vb rather than hb */
1181 tmp
= RREG32(EVERGREEN_GRPH_FLIP_CONTROL
+ radeon_crtc
->crtc_offset
);
1182 tmp
&= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN
;
1183 WREG32(EVERGREEN_GRPH_FLIP_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
1185 /* set pageflip to happen anywhere in vblank interval */
1186 WREG32(EVERGREEN_MASTER_UPDATE_MODE
+ radeon_crtc
->crtc_offset
, 0);
1188 if (!atomic
&& fb
&& fb
!= crtc
->fb
) {
1189 radeon_fb
= to_radeon_framebuffer(fb
);
1190 rbo
= gem_to_radeon_bo(radeon_fb
->obj
);
1191 r
= radeon_bo_reserve(rbo
, false);
1192 if (unlikely(r
!= 0))
1194 radeon_bo_unpin(rbo
);
1195 radeon_bo_unreserve(rbo
);
1198 /* Bytes per pixel may have changed */
1199 radeon_bandwidth_update(rdev
);
1204 static int avivo_crtc_do_set_base(struct drm_crtc
*crtc
,
1205 struct drm_framebuffer
*fb
,
1206 int x
, int y
, int atomic
)
1208 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1209 struct drm_device
*dev
= crtc
->dev
;
1210 struct radeon_device
*rdev
= dev
->dev_private
;
1211 struct radeon_framebuffer
*radeon_fb
;
1212 struct drm_gem_object
*obj
;
1213 struct radeon_bo
*rbo
;
1214 struct drm_framebuffer
*target_fb
;
1215 uint64_t fb_location
;
1216 uint32_t fb_format
, fb_pitch_pixels
, tiling_flags
;
1217 u32 fb_swap
= R600_D1GRPH_SWAP_ENDIAN_NONE
;
1218 u32 tmp
, viewport_w
, viewport_h
;
1222 if (!atomic
&& !crtc
->fb
) {
1223 DRM_DEBUG_KMS("No FB bound\n");
1228 radeon_fb
= to_radeon_framebuffer(fb
);
1232 radeon_fb
= to_radeon_framebuffer(crtc
->fb
);
1233 target_fb
= crtc
->fb
;
1236 obj
= radeon_fb
->obj
;
1237 rbo
= gem_to_radeon_bo(obj
);
1238 r
= radeon_bo_reserve(rbo
, false);
1239 if (unlikely(r
!= 0))
1242 /* If atomic, assume fb object is pinned & idle & fenced and
1243 * just update base pointers
1246 fb_location
= radeon_bo_gpu_offset(rbo
);
1248 r
= radeon_bo_pin(rbo
, RADEON_GEM_DOMAIN_VRAM
, &fb_location
);
1249 if (unlikely(r
!= 0)) {
1250 radeon_bo_unreserve(rbo
);
1254 radeon_bo_get_tiling_flags(rbo
, &tiling_flags
, NULL
);
1255 radeon_bo_unreserve(rbo
);
1257 switch (target_fb
->bits_per_pixel
) {
1260 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
|
1261 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED
;
1265 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
|
1266 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555
;
1270 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
|
1271 AVIVO_D1GRPH_CONTROL_16BPP_RGB565
;
1273 fb_swap
= R600_D1GRPH_SWAP_ENDIAN_16BIT
;
1279 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
|
1280 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888
;
1282 fb_swap
= R600_D1GRPH_SWAP_ENDIAN_32BIT
;
1286 DRM_ERROR("Unsupported screen depth %d\n",
1287 target_fb
->bits_per_pixel
);
1291 if (rdev
->family
>= CHIP_R600
) {
1292 if (tiling_flags
& RADEON_TILING_MACRO
)
1293 fb_format
|= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
;
1294 else if (tiling_flags
& RADEON_TILING_MICRO
)
1295 fb_format
|= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
;
1297 if (tiling_flags
& RADEON_TILING_MACRO
)
1298 fb_format
|= AVIVO_D1GRPH_MACRO_ADDRESS_MODE
;
1300 if (tiling_flags
& RADEON_TILING_MICRO
)
1301 fb_format
|= AVIVO_D1GRPH_TILED
;
1304 if (radeon_crtc
->crtc_id
== 0)
1305 WREG32(AVIVO_D1VGA_CONTROL
, 0);
1307 WREG32(AVIVO_D2VGA_CONTROL
, 0);
1309 if (rdev
->family
>= CHIP_RV770
) {
1310 if (radeon_crtc
->crtc_id
) {
1311 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1312 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1314 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1315 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
, upper_32_bits(fb_location
));
1318 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS
+ radeon_crtc
->crtc_offset
,
1320 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS
+
1321 radeon_crtc
->crtc_offset
, (u32
) fb_location
);
1322 WREG32(AVIVO_D1GRPH_CONTROL
+ radeon_crtc
->crtc_offset
, fb_format
);
1323 if (rdev
->family
>= CHIP_R600
)
1324 WREG32(R600_D1GRPH_SWAP_CONTROL
+ radeon_crtc
->crtc_offset
, fb_swap
);
1326 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X
+ radeon_crtc
->crtc_offset
, 0);
1327 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y
+ radeon_crtc
->crtc_offset
, 0);
1328 WREG32(AVIVO_D1GRPH_X_START
+ radeon_crtc
->crtc_offset
, 0);
1329 WREG32(AVIVO_D1GRPH_Y_START
+ radeon_crtc
->crtc_offset
, 0);
1330 WREG32(AVIVO_D1GRPH_X_END
+ radeon_crtc
->crtc_offset
, target_fb
->width
);
1331 WREG32(AVIVO_D1GRPH_Y_END
+ radeon_crtc
->crtc_offset
, target_fb
->height
);
1333 fb_pitch_pixels
= target_fb
->pitch
/ (target_fb
->bits_per_pixel
/ 8);
1334 WREG32(AVIVO_D1GRPH_PITCH
+ radeon_crtc
->crtc_offset
, fb_pitch_pixels
);
1335 WREG32(AVIVO_D1GRPH_ENABLE
+ radeon_crtc
->crtc_offset
, 1);
1337 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT
+ radeon_crtc
->crtc_offset
,
1338 crtc
->mode
.vdisplay
);
1341 WREG32(AVIVO_D1MODE_VIEWPORT_START
+ radeon_crtc
->crtc_offset
,
1343 viewport_w
= crtc
->mode
.hdisplay
;
1344 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
1345 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE
+ radeon_crtc
->crtc_offset
,
1346 (viewport_w
<< 16) | viewport_h
);
1348 /* pageflip setup */
1349 /* make sure flip is at vb rather than hb */
1350 tmp
= RREG32(AVIVO_D1GRPH_FLIP_CONTROL
+ radeon_crtc
->crtc_offset
);
1351 tmp
&= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN
;
1352 WREG32(AVIVO_D1GRPH_FLIP_CONTROL
+ radeon_crtc
->crtc_offset
, tmp
);
1354 /* set pageflip to happen anywhere in vblank interval */
1355 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE
+ radeon_crtc
->crtc_offset
, 0);
1357 if (!atomic
&& fb
&& fb
!= crtc
->fb
) {
1358 radeon_fb
= to_radeon_framebuffer(fb
);
1359 rbo
= gem_to_radeon_bo(radeon_fb
->obj
);
1360 r
= radeon_bo_reserve(rbo
, false);
1361 if (unlikely(r
!= 0))
1363 radeon_bo_unpin(rbo
);
1364 radeon_bo_unreserve(rbo
);
1367 /* Bytes per pixel may have changed */
1368 radeon_bandwidth_update(rdev
);
1373 int atombios_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1374 struct drm_framebuffer
*old_fb
)
1376 struct drm_device
*dev
= crtc
->dev
;
1377 struct radeon_device
*rdev
= dev
->dev_private
;
1379 if (ASIC_IS_DCE4(rdev
))
1380 return dce4_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1381 else if (ASIC_IS_AVIVO(rdev
))
1382 return avivo_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1384 return radeon_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1387 int atombios_crtc_set_base_atomic(struct drm_crtc
*crtc
,
1388 struct drm_framebuffer
*fb
,
1389 int x
, int y
, enum mode_set_atomic state
)
1391 struct drm_device
*dev
= crtc
->dev
;
1392 struct radeon_device
*rdev
= dev
->dev_private
;
1394 if (ASIC_IS_DCE4(rdev
))
1395 return dce4_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
1396 else if (ASIC_IS_AVIVO(rdev
))
1397 return avivo_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
1399 return radeon_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
1402 /* properly set additional regs when using atombios */
1403 static void radeon_legacy_atom_fixup(struct drm_crtc
*crtc
)
1405 struct drm_device
*dev
= crtc
->dev
;
1406 struct radeon_device
*rdev
= dev
->dev_private
;
1407 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1408 u32 disp_merge_cntl
;
1410 switch (radeon_crtc
->crtc_id
) {
1412 disp_merge_cntl
= RREG32(RADEON_DISP_MERGE_CNTL
);
1413 disp_merge_cntl
&= ~RADEON_DISP_RGB_OFFSET_EN
;
1414 WREG32(RADEON_DISP_MERGE_CNTL
, disp_merge_cntl
);
1417 disp_merge_cntl
= RREG32(RADEON_DISP2_MERGE_CNTL
);
1418 disp_merge_cntl
&= ~RADEON_DISP2_RGB_OFFSET_EN
;
1419 WREG32(RADEON_DISP2_MERGE_CNTL
, disp_merge_cntl
);
1420 WREG32(RADEON_FP_H2_SYNC_STRT_WID
, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID
));
1421 WREG32(RADEON_FP_V2_SYNC_STRT_WID
, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID
));
1426 static int radeon_atom_pick_pll(struct drm_crtc
*crtc
)
1428 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1429 struct drm_device
*dev
= crtc
->dev
;
1430 struct radeon_device
*rdev
= dev
->dev_private
;
1431 struct drm_encoder
*test_encoder
;
1432 struct drm_crtc
*test_crtc
;
1433 uint32_t pll_in_use
= 0;
1435 if (ASIC_IS_DCE4(rdev
)) {
1436 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
1437 if (test_encoder
->crtc
&& (test_encoder
->crtc
== crtc
)) {
1438 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1439 * depending on the asic:
1440 * DCE4: PPLL or ext clock
1441 * DCE5: DCPLL or ext clock
1443 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1444 * PPLL/DCPLL programming and only program the DP DTO for the
1445 * crtc virtual pixel clock.
1447 if (atombios_get_encoder_mode(test_encoder
) == ATOM_ENCODER_MODE_DP
) {
1448 if (ASIC_IS_DCE5(rdev
) || rdev
->clock
.dp_extclk
)
1449 return ATOM_PPLL_INVALID
;
1454 /* otherwise, pick one of the plls */
1455 list_for_each_entry(test_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1456 struct radeon_crtc
*radeon_test_crtc
;
1458 if (crtc
== test_crtc
)
1461 radeon_test_crtc
= to_radeon_crtc(test_crtc
);
1462 if ((radeon_test_crtc
->pll_id
>= ATOM_PPLL1
) &&
1463 (radeon_test_crtc
->pll_id
<= ATOM_PPLL2
))
1464 pll_in_use
|= (1 << radeon_test_crtc
->pll_id
);
1466 if (!(pll_in_use
& 1))
1470 return radeon_crtc
->crtc_id
;
1474 int atombios_crtc_mode_set(struct drm_crtc
*crtc
,
1475 struct drm_display_mode
*mode
,
1476 struct drm_display_mode
*adjusted_mode
,
1477 int x
, int y
, struct drm_framebuffer
*old_fb
)
1479 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1480 struct drm_device
*dev
= crtc
->dev
;
1481 struct radeon_device
*rdev
= dev
->dev_private
;
1482 struct drm_encoder
*encoder
;
1483 bool is_tvcv
= false;
1485 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1487 if (encoder
->crtc
== crtc
) {
1488 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1489 if (radeon_encoder
->active_device
&
1490 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
1495 /* always set DCPLL */
1496 if (ASIC_IS_DCE4(rdev
)) {
1497 struct radeon_atom_ss ss
;
1498 bool ss_enabled
= radeon_atombios_get_asic_ss_info(rdev
, &ss
,
1499 ASIC_INTERNAL_SS_ON_DCPLL
,
1500 rdev
->clock
.default_dispclk
);
1502 atombios_crtc_program_ss(crtc
, ATOM_DISABLE
, ATOM_DCPLL
, &ss
);
1503 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1504 atombios_crtc_set_dcpll(crtc
, rdev
->clock
.default_dispclk
);
1506 atombios_crtc_program_ss(crtc
, ATOM_ENABLE
, ATOM_DCPLL
, &ss
);
1508 atombios_crtc_set_pll(crtc
, adjusted_mode
);
1510 if (ASIC_IS_DCE4(rdev
))
1511 atombios_set_crtc_dtd_timing(crtc
, adjusted_mode
);
1512 else if (ASIC_IS_AVIVO(rdev
)) {
1514 atombios_crtc_set_timing(crtc
, adjusted_mode
);
1516 atombios_set_crtc_dtd_timing(crtc
, adjusted_mode
);
1518 atombios_crtc_set_timing(crtc
, adjusted_mode
);
1519 if (radeon_crtc
->crtc_id
== 0)
1520 atombios_set_crtc_dtd_timing(crtc
, adjusted_mode
);
1521 radeon_legacy_atom_fixup(crtc
);
1523 atombios_crtc_set_base(crtc
, x
, y
, old_fb
);
1524 atombios_overscan_setup(crtc
, mode
, adjusted_mode
);
1525 atombios_scaler_setup(crtc
);
1529 static bool atombios_crtc_mode_fixup(struct drm_crtc
*crtc
,
1530 struct drm_display_mode
*mode
,
1531 struct drm_display_mode
*adjusted_mode
)
1533 struct drm_device
*dev
= crtc
->dev
;
1534 struct radeon_device
*rdev
= dev
->dev_private
;
1536 /* adjust pm to upcoming mode change */
1537 radeon_pm_compute_clocks(rdev
);
1539 if (!radeon_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
1544 static void atombios_crtc_prepare(struct drm_crtc
*crtc
)
1546 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1549 radeon_crtc
->pll_id
= radeon_atom_pick_pll(crtc
);
1551 atombios_lock_crtc(crtc
, ATOM_ENABLE
);
1552 atombios_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
1555 static void atombios_crtc_commit(struct drm_crtc
*crtc
)
1557 atombios_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
1558 atombios_lock_crtc(crtc
, ATOM_DISABLE
);
1561 static void atombios_crtc_disable(struct drm_crtc
*crtc
)
1563 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1564 struct radeon_atom_ss ss
;
1566 atombios_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
1568 switch (radeon_crtc
->pll_id
) {
1571 /* disable the ppll */
1572 atombios_crtc_program_pll(crtc
, radeon_crtc
->crtc_id
, radeon_crtc
->pll_id
,
1573 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
1578 radeon_crtc
->pll_id
= -1;
1581 static const struct drm_crtc_helper_funcs atombios_helper_funcs
= {
1582 .dpms
= atombios_crtc_dpms
,
1583 .mode_fixup
= atombios_crtc_mode_fixup
,
1584 .mode_set
= atombios_crtc_mode_set
,
1585 .mode_set_base
= atombios_crtc_set_base
,
1586 .mode_set_base_atomic
= atombios_crtc_set_base_atomic
,
1587 .prepare
= atombios_crtc_prepare
,
1588 .commit
= atombios_crtc_commit
,
1589 .load_lut
= radeon_crtc_load_lut
,
1590 .disable
= atombios_crtc_disable
,
1593 void radeon_atombios_init_crtc(struct drm_device
*dev
,
1594 struct radeon_crtc
*radeon_crtc
)
1596 struct radeon_device
*rdev
= dev
->dev_private
;
1598 if (ASIC_IS_DCE4(rdev
)) {
1599 switch (radeon_crtc
->crtc_id
) {
1602 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC0_REGISTER_OFFSET
;
1605 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC1_REGISTER_OFFSET
;
1608 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC2_REGISTER_OFFSET
;
1611 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC3_REGISTER_OFFSET
;
1614 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC4_REGISTER_OFFSET
;
1617 radeon_crtc
->crtc_offset
= EVERGREEN_CRTC5_REGISTER_OFFSET
;
1621 if (radeon_crtc
->crtc_id
== 1)
1622 radeon_crtc
->crtc_offset
=
1623 AVIVO_D2CRTC_H_TOTAL
- AVIVO_D1CRTC_H_TOTAL
;
1625 radeon_crtc
->crtc_offset
= 0;
1627 radeon_crtc
->pll_id
= -1;
1628 drm_crtc_helper_add(&radeon_crtc
->base
, &atombios_helper_funcs
);