2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names
[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names
[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8
*dst
, u8
*src
, u8 num_bytes
, bool to_le
)
56 u8 src_tmp
[20], dst_tmp
[20]; /* used for byteswapping */
60 memcpy(src_tmp
, src
, num_bytes
);
61 src32
= (u32
*)src_tmp
;
62 dst32
= (u32
*)dst_tmp
;
64 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
65 dst32
[i
] = cpu_to_le32(src32
[i
]);
66 memcpy(dst
, dst_tmp
, num_bytes
);
68 u8 dws
= num_bytes
& ~3;
69 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
70 dst32
[i
] = le32_to_cpu(src32
[i
]);
71 memcpy(dst
, dst_tmp
, dws
);
73 for (i
= 0; i
< (num_bytes
% 4); i
++)
74 dst
[dws
+i
] = dst_tmp
[dws
+i
];
78 memcpy(dst
, src
, num_bytes
);
82 union aux_channel_transaction
{
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1
;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2
;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan
*chan
,
88 u8
*send
, int send_bytes
,
89 u8
*recv
, int recv_size
,
92 struct drm_device
*dev
= chan
->dev
;
93 struct radeon_device
*rdev
= dev
->dev_private
;
94 union aux_channel_transaction args
;
95 int index
= GetIndexIntoMasterTable(COMMAND
, ProcessAuxChannelTransaction
);
100 memset(&args
, 0, sizeof(args
));
102 mutex_lock(&chan
->mutex
);
103 mutex_lock(&rdev
->mode_info
.atom_context
->scratch_mutex
);
105 base
= (unsigned char *)(rdev
->mode_info
.atom_context
->scratch
+ 1);
107 radeon_atom_copy_swap(base
, send
, send_bytes
, true);
109 args
.v1
.lpAuxRequest
= cpu_to_le16((u16
)(0 + 4));
110 args
.v1
.lpDataOut
= cpu_to_le16((u16
)(16 + 4));
111 args
.v1
.ucDataOutLen
= 0;
112 args
.v1
.ucChannelID
= chan
->rec
.i2c_id
;
113 args
.v1
.ucDelay
= delay
/ 10;
114 if (ASIC_IS_DCE4(rdev
))
115 args
.v2
.ucHPD_ID
= chan
->rec
.hpd
;
117 atom_execute_table_scratch_unlocked(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
119 *ack
= args
.v1
.ucReplyStatus
;
122 if (args
.v1
.ucReplyStatus
== 1) {
123 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
129 if (args
.v1
.ucReplyStatus
== 2) {
130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
136 if (args
.v1
.ucReplyStatus
== 3) {
137 DRM_DEBUG_KMS("dp_aux_ch error\n");
142 recv_bytes
= args
.v1
.ucDataOutLen
;
143 if (recv_bytes
> recv_size
)
144 recv_bytes
= recv_size
;
146 if (recv
&& recv_size
)
147 radeon_atom_copy_swap(recv
, base
+ 16, recv_bytes
, false);
151 mutex_unlock(&rdev
->mode_info
.atom_context
->scratch_mutex
);
152 mutex_unlock(&chan
->mutex
);
157 #define BARE_ADDRESS_SIZE 3
158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
161 radeon_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
163 struct radeon_i2c_chan
*chan
=
164 container_of(aux
, struct radeon_i2c_chan
, aux
);
170 if (WARN_ON(msg
->size
> 16))
173 tx_buf
[0] = msg
->address
& 0xff;
174 tx_buf
[1] = msg
->address
>> 8;
175 tx_buf
[2] = msg
->request
<< 4;
176 tx_buf
[3] = msg
->size
? (msg
->size
- 1) : 0;
178 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
179 case DP_AUX_NATIVE_WRITE
:
180 case DP_AUX_I2C_WRITE
:
181 /* tx_size needs to be 4 even for bare address packets since the atom
182 * table needs the info in tx_buf[3].
184 tx_size
= HEADER_SIZE
+ msg
->size
;
186 tx_buf
[3] |= BARE_ADDRESS_SIZE
<< 4;
188 tx_buf
[3] |= tx_size
<< 4;
189 memcpy(tx_buf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
190 ret
= radeon_process_aux_ch(chan
,
191 tx_buf
, tx_size
, NULL
, 0, delay
, &ack
);
193 /* Return payload size. */
196 case DP_AUX_NATIVE_READ
:
197 case DP_AUX_I2C_READ
:
198 /* tx_size needs to be 4 even for bare address packets since the atom
199 * table needs the info in tx_buf[3].
201 tx_size
= HEADER_SIZE
;
203 tx_buf
[3] |= BARE_ADDRESS_SIZE
<< 4;
205 tx_buf
[3] |= tx_size
<< 4;
206 ret
= radeon_process_aux_ch(chan
,
207 tx_buf
, tx_size
, msg
->buffer
, msg
->size
, delay
, &ack
);
215 msg
->reply
= ack
>> 4;
220 void radeon_dp_aux_init(struct radeon_connector
*radeon_connector
)
224 radeon_connector
->ddc_bus
->rec
.hpd
= radeon_connector
->hpd
.hpd
;
225 radeon_connector
->ddc_bus
->aux
.dev
= radeon_connector
->base
.kdev
;
226 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer
;
228 ret
= drm_dp_aux_register(&radeon_connector
->ddc_bus
->aux
);
230 radeon_connector
->ddc_bus
->has_aux
= true;
232 WARN(ret
, "drm_dp_aux_register() failed with error %d\n", ret
);
235 /***** general DP utility functions *****/
237 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
238 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
240 static void dp_get_adjust_train(u8 link_status
[DP_LINK_STATUS_SIZE
],
248 for (lane
= 0; lane
< lane_count
; lane
++) {
249 u8 this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
250 u8 this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
252 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
254 voltage_names
[this_v
>> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
255 pre_emph_names
[this_p
>> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
263 if (v
>= DP_VOLTAGE_MAX
)
264 v
|= DP_TRAIN_MAX_SWING_REACHED
;
266 if (p
>= DP_PRE_EMPHASIS_MAX
)
267 p
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
269 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
270 voltage_names
[(v
& DP_TRAIN_VOLTAGE_SWING_MASK
) >> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
271 pre_emph_names
[(p
& DP_TRAIN_PRE_EMPHASIS_MASK
) >> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
273 for (lane
= 0; lane
< 4; lane
++)
274 train_set
[lane
] = v
| p
;
277 /* convert bits per color to bits per pixel */
278 /* get bpc from the EDID */
279 static int convert_bpc_to_bpp(int bpc
)
287 /* get the max pix clock supported by the link rate and lane num */
288 static int dp_get_max_dp_pix_clock(int link_rate
,
292 return (link_rate
* lane_num
* 8) / bpp
;
295 /***** radeon specific DP functions *****/
297 static int radeon_dp_get_max_link_rate(struct drm_connector
*connector
,
298 u8 dpcd
[DP_DPCD_SIZE
])
302 if (radeon_connector_is_dp12_capable(connector
))
303 max_link_rate
= min(drm_dp_max_link_rate(dpcd
), 540000);
305 max_link_rate
= min(drm_dp_max_link_rate(dpcd
), 270000);
307 return max_link_rate
;
310 /* First get the min lane# when low rate is used according to pixel clock
311 * (prefer low rate), second check max lane# supported by DP panel,
312 * if the max lane# < low rate lane# then use max lane# instead.
314 static int radeon_dp_get_dp_lane_number(struct drm_connector
*connector
,
315 u8 dpcd
[DP_DPCD_SIZE
],
318 int bpp
= convert_bpc_to_bpp(radeon_get_monitor_bpc(connector
));
319 int max_link_rate
= radeon_dp_get_max_link_rate(connector
, dpcd
);
320 int max_lane_num
= drm_dp_max_lane_count(dpcd
);
322 int max_dp_pix_clock
;
324 for (lane_num
= 1; lane_num
< max_lane_num
; lane_num
<<= 1) {
325 max_dp_pix_clock
= dp_get_max_dp_pix_clock(max_link_rate
, lane_num
, bpp
);
326 if (pix_clock
<= max_dp_pix_clock
)
333 static int radeon_dp_get_dp_link_clock(struct drm_connector
*connector
,
334 u8 dpcd
[DP_DPCD_SIZE
],
337 int bpp
= convert_bpc_to_bpp(radeon_get_monitor_bpc(connector
));
338 int lane_num
, max_pix_clock
;
340 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector
) ==
341 ENCODER_OBJECT_ID_NUTMEG
)
344 lane_num
= radeon_dp_get_dp_lane_number(connector
, dpcd
, pix_clock
);
345 max_pix_clock
= dp_get_max_dp_pix_clock(162000, lane_num
, bpp
);
346 if (pix_clock
<= max_pix_clock
)
348 max_pix_clock
= dp_get_max_dp_pix_clock(270000, lane_num
, bpp
);
349 if (pix_clock
<= max_pix_clock
)
351 if (radeon_connector_is_dp12_capable(connector
)) {
352 max_pix_clock
= dp_get_max_dp_pix_clock(540000, lane_num
, bpp
);
353 if (pix_clock
<= max_pix_clock
)
357 return radeon_dp_get_max_link_rate(connector
, dpcd
);
360 static u8
radeon_dp_encoder_service(struct radeon_device
*rdev
,
361 int action
, int dp_clock
,
362 u8 ucconfig
, u8 lane_num
)
364 DP_ENCODER_SERVICE_PARAMETERS args
;
365 int index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
367 memset(&args
, 0, sizeof(args
));
368 args
.ucLinkClock
= dp_clock
/ 10;
369 args
.ucConfig
= ucconfig
;
370 args
.ucAction
= action
;
371 args
.ucLaneNum
= lane_num
;
374 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
375 return args
.ucStatus
;
378 u8
radeon_dp_getsinktype(struct radeon_connector
*radeon_connector
)
380 struct drm_device
*dev
= radeon_connector
->base
.dev
;
381 struct radeon_device
*rdev
= dev
->dev_private
;
383 return radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_GET_SINK_TYPE
, 0,
384 radeon_connector
->ddc_bus
->rec
.i2c_id
, 0);
387 static void radeon_dp_probe_oui(struct radeon_connector
*radeon_connector
)
389 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
392 if (!(dig_connector
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
395 if (drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
396 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
397 buf
[0], buf
[1], buf
[2]);
399 if (drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
400 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
401 buf
[0], buf
[1], buf
[2]);
404 bool radeon_dp_getdpcd(struct radeon_connector
*radeon_connector
)
406 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
407 u8 msg
[DP_DPCD_SIZE
];
410 ret
= drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_DPCD_REV
, msg
,
413 memcpy(dig_connector
->dpcd
, msg
, DP_DPCD_SIZE
);
415 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector
->dpcd
),
416 dig_connector
->dpcd
);
418 radeon_dp_probe_oui(radeon_connector
);
422 dig_connector
->dpcd
[0] = 0;
426 int radeon_dp_get_panel_mode(struct drm_encoder
*encoder
,
427 struct drm_connector
*connector
)
429 struct drm_device
*dev
= encoder
->dev
;
430 struct radeon_device
*rdev
= dev
->dev_private
;
431 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
432 struct radeon_connector_atom_dig
*dig_connector
;
433 int panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
434 u16 dp_bridge
= radeon_connector_encoder_get_dp_bridge_encoder_id(connector
);
437 if (!ASIC_IS_DCE4(rdev
))
440 if (!radeon_connector
->con_priv
)
443 dig_connector
= radeon_connector
->con_priv
;
445 if (dp_bridge
!= ENCODER_OBJECT_ID_NONE
) {
446 /* DP bridge chips */
447 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
,
448 DP_EDP_CONFIGURATION_CAP
, &tmp
) == 1) {
450 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
451 else if ((dp_bridge
== ENCODER_OBJECT_ID_NUTMEG
) ||
452 (dp_bridge
== ENCODER_OBJECT_ID_TRAVIS
))
453 panel_mode
= DP_PANEL_MODE_INTERNAL_DP1_MODE
;
455 panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
457 } else if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
459 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
,
460 DP_EDP_CONFIGURATION_CAP
, &tmp
) == 1) {
462 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
469 void radeon_dp_set_link_config(struct drm_connector
*connector
,
470 const struct drm_display_mode
*mode
)
472 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
473 struct radeon_connector_atom_dig
*dig_connector
;
475 if (!radeon_connector
->con_priv
)
477 dig_connector
= radeon_connector
->con_priv
;
479 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
480 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
481 dig_connector
->dp_clock
=
482 radeon_dp_get_dp_link_clock(connector
, dig_connector
->dpcd
, mode
->clock
);
483 dig_connector
->dp_lane_count
=
484 radeon_dp_get_dp_lane_number(connector
, dig_connector
->dpcd
, mode
->clock
);
488 int radeon_dp_mode_valid_helper(struct drm_connector
*connector
,
489 struct drm_display_mode
*mode
)
491 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
492 struct radeon_connector_atom_dig
*dig_connector
;
495 if (!radeon_connector
->con_priv
)
496 return MODE_CLOCK_HIGH
;
497 dig_connector
= radeon_connector
->con_priv
;
500 radeon_dp_get_dp_link_clock(connector
, dig_connector
->dpcd
, mode
->clock
);
502 if ((dp_clock
== 540000) &&
503 (!radeon_connector_is_dp12_capable(connector
)))
504 return MODE_CLOCK_HIGH
;
509 bool radeon_dp_needs_link_train(struct radeon_connector
*radeon_connector
)
511 u8 link_status
[DP_LINK_STATUS_SIZE
];
512 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
514 if (drm_dp_dpcd_read_link_status(&radeon_connector
->ddc_bus
->aux
, link_status
)
517 if (drm_dp_channel_eq_ok(link_status
, dig
->dp_lane_count
))
522 void radeon_dp_set_rx_power_state(struct drm_connector
*connector
,
525 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
526 struct radeon_connector_atom_dig
*dig_connector
;
528 if (!radeon_connector
->con_priv
)
531 dig_connector
= radeon_connector
->con_priv
;
533 /* power up/down the sink */
534 if (dig_connector
->dpcd
[0] >= 0x11) {
535 drm_dp_dpcd_writeb(&radeon_connector
->ddc_bus
->aux
,
536 DP_SET_POWER
, power_state
);
537 usleep_range(1000, 2000);
542 struct radeon_dp_link_train_info
{
543 struct radeon_device
*rdev
;
544 struct drm_encoder
*encoder
;
545 struct drm_connector
*connector
;
550 u8 dpcd
[DP_RECEIVER_CAP_SIZE
];
552 u8 link_status
[DP_LINK_STATUS_SIZE
];
555 struct drm_dp_aux
*aux
;
558 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info
*dp_info
)
560 /* set the initial vs/emph on the source */
561 atombios_dig_transmitter_setup(dp_info
->encoder
,
562 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
,
563 0, dp_info
->train_set
[0]); /* sets all lanes at once */
565 /* set the vs/emph on the sink */
566 drm_dp_dpcd_write(dp_info
->aux
, DP_TRAINING_LANE0_SET
,
567 dp_info
->train_set
, dp_info
->dp_lane_count
);
570 static void radeon_dp_set_tp(struct radeon_dp_link_train_info
*dp_info
, int tp
)
574 /* set training pattern on the source */
575 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
) {
577 case DP_TRAINING_PATTERN_1
:
578 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
;
580 case DP_TRAINING_PATTERN_2
:
581 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
;
583 case DP_TRAINING_PATTERN_3
:
584 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
;
587 atombios_dig_encoder_setup(dp_info
->encoder
, rtp
, 0);
590 case DP_TRAINING_PATTERN_1
:
593 case DP_TRAINING_PATTERN_2
:
597 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
598 dp_info
->dp_clock
, dp_info
->enc_id
, rtp
);
601 /* enable training pattern on the sink */
602 drm_dp_dpcd_writeb(dp_info
->aux
, DP_TRAINING_PATTERN_SET
, tp
);
605 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info
*dp_info
)
607 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(dp_info
->encoder
);
608 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
611 /* power up the sink */
612 radeon_dp_set_rx_power_state(dp_info
->connector
, DP_SET_POWER_D0
);
614 /* possibly enable downspread on the sink */
615 if (dp_info
->dpcd
[3] & 0x1)
616 drm_dp_dpcd_writeb(dp_info
->aux
,
617 DP_DOWNSPREAD_CTRL
, DP_SPREAD_AMP_0_5
);
619 drm_dp_dpcd_writeb(dp_info
->aux
,
620 DP_DOWNSPREAD_CTRL
, 0);
622 if ((dp_info
->connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) &&
623 (dig
->panel_mode
== DP_PANEL_MODE_INTERNAL_DP2_MODE
)) {
624 drm_dp_dpcd_writeb(dp_info
->aux
, DP_EDP_CONFIGURATION_SET
, 1);
627 /* set the lane count on the sink */
628 tmp
= dp_info
->dp_lane_count
;
629 if (drm_dp_enhanced_frame_cap(dp_info
->dpcd
))
630 tmp
|= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
631 drm_dp_dpcd_writeb(dp_info
->aux
, DP_LANE_COUNT_SET
, tmp
);
633 /* set the link rate on the sink */
634 tmp
= drm_dp_link_rate_to_bw_code(dp_info
->dp_clock
);
635 drm_dp_dpcd_writeb(dp_info
->aux
, DP_LINK_BW_SET
, tmp
);
637 /* start training on the source */
638 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
639 atombios_dig_encoder_setup(dp_info
->encoder
,
640 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
, 0);
642 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_START
,
643 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
645 /* disable the training pattern on the sink */
646 drm_dp_dpcd_writeb(dp_info
->aux
,
647 DP_TRAINING_PATTERN_SET
,
648 DP_TRAINING_PATTERN_DISABLE
);
653 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info
*dp_info
)
657 /* disable the training pattern on the sink */
658 drm_dp_dpcd_writeb(dp_info
->aux
,
659 DP_TRAINING_PATTERN_SET
,
660 DP_TRAINING_PATTERN_DISABLE
);
662 /* disable the training pattern on the source */
663 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
664 atombios_dig_encoder_setup(dp_info
->encoder
,
665 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
, 0);
667 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_COMPLETE
,
668 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
673 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info
*dp_info
)
679 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_1
);
680 memset(dp_info
->train_set
, 0, 4);
681 radeon_dp_update_vs_emph(dp_info
);
685 /* clock recovery loop */
686 clock_recovery
= false;
690 drm_dp_link_train_clock_recovery_delay(dp_info
->dpcd
);
692 if (drm_dp_dpcd_read_link_status(dp_info
->aux
,
693 dp_info
->link_status
) <= 0) {
694 DRM_ERROR("displayport link status failed\n");
698 if (drm_dp_clock_recovery_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
699 clock_recovery
= true;
703 for (i
= 0; i
< dp_info
->dp_lane_count
; i
++) {
704 if ((dp_info
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
707 if (i
== dp_info
->dp_lane_count
) {
708 DRM_ERROR("clock recovery reached max voltage\n");
712 if ((dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
714 if (dp_info
->tries
== 5) {
715 DRM_ERROR("clock recovery tried 5 times\n");
721 voltage
= dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
723 /* Compute new train_set as requested by sink */
724 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
726 radeon_dp_update_vs_emph(dp_info
);
728 if (!clock_recovery
) {
729 DRM_ERROR("clock recovery failed\n");
732 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
733 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
734 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
) >>
735 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
740 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info
*dp_info
)
744 if (dp_info
->tp3_supported
)
745 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_3
);
747 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_2
);
749 /* channel equalization loop */
753 drm_dp_link_train_channel_eq_delay(dp_info
->dpcd
);
755 if (drm_dp_dpcd_read_link_status(dp_info
->aux
,
756 dp_info
->link_status
) <= 0) {
757 DRM_ERROR("displayport link status failed\n");
761 if (drm_dp_channel_eq_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
767 if (dp_info
->tries
> 5) {
768 DRM_ERROR("channel eq failed: 5 tries\n");
772 /* Compute new train_set as requested by sink */
773 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
775 radeon_dp_update_vs_emph(dp_info
);
780 DRM_ERROR("channel eq failed\n");
783 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
784 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
785 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
)
786 >> DP_TRAIN_PRE_EMPHASIS_SHIFT
);
791 void radeon_dp_link_train(struct drm_encoder
*encoder
,
792 struct drm_connector
*connector
)
794 struct drm_device
*dev
= encoder
->dev
;
795 struct radeon_device
*rdev
= dev
->dev_private
;
796 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
797 struct radeon_encoder_atom_dig
*dig
;
798 struct radeon_connector
*radeon_connector
;
799 struct radeon_connector_atom_dig
*dig_connector
;
800 struct radeon_dp_link_train_info dp_info
;
804 if (!radeon_encoder
->enc_priv
)
806 dig
= radeon_encoder
->enc_priv
;
808 radeon_connector
= to_radeon_connector(connector
);
809 if (!radeon_connector
->con_priv
)
811 dig_connector
= radeon_connector
->con_priv
;
813 if ((dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_DISPLAYPORT
) &&
814 (dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_eDP
))
817 /* DPEncoderService newer than 1.1 can't program properly the
818 * training pattern. When facing such version use the
819 * DIGXEncoderControl (X== 1 | 2)
821 dp_info
.use_dpencoder
= true;
822 index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
823 if (atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
)) {
825 dp_info
.use_dpencoder
= false;
830 if (dig
->dig_encoder
)
831 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
;
833 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
;
835 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_B
;
837 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_A
;
839 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
, DP_MAX_LANE_COUNT
, &tmp
)
841 if (ASIC_IS_DCE5(rdev
) && (tmp
& DP_TPS3_SUPPORTED
))
842 dp_info
.tp3_supported
= true;
844 dp_info
.tp3_supported
= false;
846 dp_info
.tp3_supported
= false;
849 memcpy(dp_info
.dpcd
, dig_connector
->dpcd
, DP_RECEIVER_CAP_SIZE
);
851 dp_info
.encoder
= encoder
;
852 dp_info
.connector
= connector
;
853 dp_info
.dp_lane_count
= dig_connector
->dp_lane_count
;
854 dp_info
.dp_clock
= dig_connector
->dp_clock
;
855 dp_info
.aux
= &radeon_connector
->ddc_bus
->aux
;
857 if (radeon_dp_link_train_init(&dp_info
))
859 if (radeon_dp_link_train_cr(&dp_info
))
861 if (radeon_dp_link_train_ce(&dp_info
))
864 if (radeon_dp_link_train_finish(&dp_info
))