2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names
[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names
[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format so swap as appropriate when copying
49 * data to or from atom. Note that atom operates on dw units.
51 * Use to_le=true when sending data to atom and provide at least
52 * ALIGN(num_bytes,4) bytes in the dst buffer.
54 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
55 * byes in the src buffer.
57 void radeon_atom_copy_swap(u8
*dst
, u8
*src
, u8 num_bytes
, bool to_le
)
60 u32 src_tmp
[5], dst_tmp
[5];
62 u8 align_num_bytes
= ALIGN(num_bytes
, 4);
65 memcpy(src_tmp
, src
, num_bytes
);
66 for (i
= 0; i
< align_num_bytes
/ 4; i
++)
67 dst_tmp
[i
] = cpu_to_le32(src_tmp
[i
]);
68 memcpy(dst
, dst_tmp
, align_num_bytes
);
70 memcpy(src_tmp
, src
, align_num_bytes
);
71 for (i
= 0; i
< align_num_bytes
/ 4; i
++)
72 dst_tmp
[i
] = le32_to_cpu(src_tmp
[i
]);
73 memcpy(dst
, dst_tmp
, num_bytes
);
76 memcpy(dst
, src
, num_bytes
);
80 union aux_channel_transaction
{
81 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1
;
82 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2
;
85 static int radeon_process_aux_ch(struct radeon_i2c_chan
*chan
,
86 u8
*send
, int send_bytes
,
87 u8
*recv
, int recv_size
,
90 struct drm_device
*dev
= chan
->dev
;
91 struct radeon_device
*rdev
= dev
->dev_private
;
92 union aux_channel_transaction args
;
93 int index
= GetIndexIntoMasterTable(COMMAND
, ProcessAuxChannelTransaction
);
98 memset(&args
, 0, sizeof(args
));
100 mutex_lock(&chan
->mutex
);
101 mutex_lock(&rdev
->mode_info
.atom_context
->scratch_mutex
);
103 base
= (unsigned char *)(rdev
->mode_info
.atom_context
->scratch
+ 1);
105 radeon_atom_copy_swap(base
, send
, send_bytes
, true);
107 args
.v1
.lpAuxRequest
= cpu_to_le16((u16
)(0 + 4));
108 args
.v1
.lpDataOut
= cpu_to_le16((u16
)(16 + 4));
109 args
.v1
.ucDataOutLen
= 0;
110 args
.v1
.ucChannelID
= chan
->rec
.i2c_id
;
111 args
.v1
.ucDelay
= delay
/ 10;
112 if (ASIC_IS_DCE4(rdev
))
113 args
.v2
.ucHPD_ID
= chan
->rec
.hpd
;
115 atom_execute_table_scratch_unlocked(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
117 *ack
= args
.v1
.ucReplyStatus
;
120 if (args
.v1
.ucReplyStatus
== 1) {
121 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
127 if (args
.v1
.ucReplyStatus
== 2) {
128 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
134 if (args
.v1
.ucReplyStatus
== 3) {
135 DRM_DEBUG_KMS("dp_aux_ch error\n");
140 recv_bytes
= args
.v1
.ucDataOutLen
;
141 if (recv_bytes
> recv_size
)
142 recv_bytes
= recv_size
;
144 if (recv
&& recv_size
)
145 radeon_atom_copy_swap(recv
, base
+ 16, recv_bytes
, false);
149 mutex_unlock(&rdev
->mode_info
.atom_context
->scratch_mutex
);
150 mutex_unlock(&chan
->mutex
);
155 #define BARE_ADDRESS_SIZE 3
156 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
159 radeon_dp_aux_transfer_atom(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
161 struct radeon_i2c_chan
*chan
=
162 container_of(aux
, struct radeon_i2c_chan
, aux
);
168 if (WARN_ON(msg
->size
> 16))
171 tx_buf
[0] = msg
->address
& 0xff;
172 tx_buf
[1] = (msg
->address
>> 8) & 0xff;
173 tx_buf
[2] = (msg
->request
<< 4) |
174 ((msg
->address
>> 16) & 0xf);
175 tx_buf
[3] = msg
->size
? (msg
->size
- 1) : 0;
177 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
178 case DP_AUX_NATIVE_WRITE
:
179 case DP_AUX_I2C_WRITE
:
180 case DP_AUX_I2C_WRITE_STATUS_UPDATE
:
181 /* The atom implementation only supports writes with a max payload of
182 * 12 bytes since it uses 4 bits for the total count (header + payload)
183 * in the parameter space. The atom interface supports 16 byte
184 * payloads for reads. The hw itself supports up to 16 bytes of payload.
186 if (WARN_ON_ONCE(msg
->size
> 12))
188 /* tx_size needs to be 4 even for bare address packets since the atom
189 * table needs the info in tx_buf[3].
191 tx_size
= HEADER_SIZE
+ msg
->size
;
193 tx_buf
[3] |= BARE_ADDRESS_SIZE
<< 4;
195 tx_buf
[3] |= tx_size
<< 4;
196 memcpy(tx_buf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
197 ret
= radeon_process_aux_ch(chan
,
198 tx_buf
, tx_size
, NULL
, 0, delay
, &ack
);
200 /* Return payload size. */
203 case DP_AUX_NATIVE_READ
:
204 case DP_AUX_I2C_READ
:
205 /* tx_size needs to be 4 even for bare address packets since the atom
206 * table needs the info in tx_buf[3].
208 tx_size
= HEADER_SIZE
;
210 tx_buf
[3] |= BARE_ADDRESS_SIZE
<< 4;
212 tx_buf
[3] |= tx_size
<< 4;
213 ret
= radeon_process_aux_ch(chan
,
214 tx_buf
, tx_size
, msg
->buffer
, msg
->size
, delay
, &ack
);
222 msg
->reply
= ack
>> 4;
227 void radeon_dp_aux_init(struct radeon_connector
*radeon_connector
)
229 struct drm_device
*dev
= radeon_connector
->base
.dev
;
230 struct radeon_device
*rdev
= dev
->dev_private
;
233 radeon_connector
->ddc_bus
->rec
.hpd
= radeon_connector
->hpd
.hpd
;
234 radeon_connector
->ddc_bus
->aux
.dev
= radeon_connector
->base
.kdev
;
235 if (ASIC_IS_DCE5(rdev
)) {
237 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer_native
;
239 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer_atom
;
241 radeon_connector
->ddc_bus
->aux
.transfer
= radeon_dp_aux_transfer_atom
;
244 ret
= drm_dp_aux_register(&radeon_connector
->ddc_bus
->aux
);
246 radeon_connector
->ddc_bus
->has_aux
= true;
248 WARN(ret
, "drm_dp_aux_register() failed with error %d\n", ret
);
251 /***** general DP utility functions *****/
253 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
254 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
256 static void dp_get_adjust_train(const u8 link_status
[DP_LINK_STATUS_SIZE
],
264 for (lane
= 0; lane
< lane_count
; lane
++) {
265 u8 this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
266 u8 this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
268 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
270 voltage_names
[this_v
>> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
271 pre_emph_names
[this_p
>> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
279 if (v
>= DP_VOLTAGE_MAX
)
280 v
|= DP_TRAIN_MAX_SWING_REACHED
;
282 if (p
>= DP_PRE_EMPHASIS_MAX
)
283 p
|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
285 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
286 voltage_names
[(v
& DP_TRAIN_VOLTAGE_SWING_MASK
) >> DP_TRAIN_VOLTAGE_SWING_SHIFT
],
287 pre_emph_names
[(p
& DP_TRAIN_PRE_EMPHASIS_MASK
) >> DP_TRAIN_PRE_EMPHASIS_SHIFT
]);
289 for (lane
= 0; lane
< 4; lane
++)
290 train_set
[lane
] = v
| p
;
293 /* convert bits per color to bits per pixel */
294 /* get bpc from the EDID */
295 static int convert_bpc_to_bpp(int bpc
)
303 /***** radeon specific DP functions *****/
305 static int radeon_dp_get_dp_link_config(struct drm_connector
*connector
,
306 const u8 dpcd
[DP_DPCD_SIZE
],
308 unsigned *dp_lanes
, unsigned *dp_rate
)
310 int bpp
= convert_bpc_to_bpp(radeon_get_monitor_bpc(connector
));
311 static const unsigned link_rates
[3] = { 162000, 270000, 540000 };
312 unsigned max_link_rate
= drm_dp_max_link_rate(dpcd
);
313 unsigned max_lane_num
= drm_dp_max_lane_count(dpcd
);
314 unsigned lane_num
, i
, max_pix_clock
;
316 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector
) ==
317 ENCODER_OBJECT_ID_NUTMEG
) {
318 for (lane_num
= 1; lane_num
<= max_lane_num
; lane_num
<<= 1) {
319 max_pix_clock
= (lane_num
* 270000 * 8) / bpp
;
320 if (max_pix_clock
>= pix_clock
) {
321 *dp_lanes
= lane_num
;
327 for (i
= 0; i
< ARRAY_SIZE(link_rates
) && link_rates
[i
] <= max_link_rate
; i
++) {
328 for (lane_num
= 1; lane_num
<= max_lane_num
; lane_num
<<= 1) {
329 max_pix_clock
= (lane_num
* link_rates
[i
] * 8) / bpp
;
330 if (max_pix_clock
>= pix_clock
) {
331 *dp_lanes
= lane_num
;
332 *dp_rate
= link_rates
[i
];
342 static u8
radeon_dp_encoder_service(struct radeon_device
*rdev
,
343 int action
, int dp_clock
,
344 u8 ucconfig
, u8 lane_num
)
346 DP_ENCODER_SERVICE_PARAMETERS args
;
347 int index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
349 memset(&args
, 0, sizeof(args
));
350 args
.ucLinkClock
= dp_clock
/ 10;
351 args
.ucConfig
= ucconfig
;
352 args
.ucAction
= action
;
353 args
.ucLaneNum
= lane_num
;
356 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
357 return args
.ucStatus
;
360 u8
radeon_dp_getsinktype(struct radeon_connector
*radeon_connector
)
362 struct drm_device
*dev
= radeon_connector
->base
.dev
;
363 struct radeon_device
*rdev
= dev
->dev_private
;
365 return radeon_dp_encoder_service(rdev
, ATOM_DP_ACTION_GET_SINK_TYPE
, 0,
366 radeon_connector
->ddc_bus
->rec
.i2c_id
, 0);
369 static void radeon_dp_probe_oui(struct radeon_connector
*radeon_connector
)
371 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
374 if (!(dig_connector
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
377 if (drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
378 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
379 buf
[0], buf
[1], buf
[2]);
381 if (drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
382 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
383 buf
[0], buf
[1], buf
[2]);
386 bool radeon_dp_getdpcd(struct radeon_connector
*radeon_connector
)
388 struct radeon_connector_atom_dig
*dig_connector
= radeon_connector
->con_priv
;
389 u8 msg
[DP_DPCD_SIZE
];
392 ret
= drm_dp_dpcd_read(&radeon_connector
->ddc_bus
->aux
, DP_DPCD_REV
, msg
,
394 if (ret
== DP_DPCD_SIZE
) {
395 memcpy(dig_connector
->dpcd
, msg
, DP_DPCD_SIZE
);
397 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector
->dpcd
),
398 dig_connector
->dpcd
);
400 radeon_dp_probe_oui(radeon_connector
);
405 dig_connector
->dpcd
[0] = 0;
409 int radeon_dp_get_panel_mode(struct drm_encoder
*encoder
,
410 struct drm_connector
*connector
)
412 struct drm_device
*dev
= encoder
->dev
;
413 struct radeon_device
*rdev
= dev
->dev_private
;
414 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
415 int panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
416 u16 dp_bridge
= radeon_connector_encoder_get_dp_bridge_encoder_id(connector
);
419 if (!ASIC_IS_DCE4(rdev
))
422 if (!radeon_connector
->con_priv
)
425 if (dp_bridge
!= ENCODER_OBJECT_ID_NONE
) {
426 /* DP bridge chips */
427 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
,
428 DP_EDP_CONFIGURATION_CAP
, &tmp
) == 1) {
430 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
431 else if ((dp_bridge
== ENCODER_OBJECT_ID_NUTMEG
) ||
432 (dp_bridge
== ENCODER_OBJECT_ID_TRAVIS
))
433 panel_mode
= DP_PANEL_MODE_INTERNAL_DP1_MODE
;
435 panel_mode
= DP_PANEL_MODE_EXTERNAL_DP_MODE
;
437 } else if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
439 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
,
440 DP_EDP_CONFIGURATION_CAP
, &tmp
) == 1) {
442 panel_mode
= DP_PANEL_MODE_INTERNAL_DP2_MODE
;
449 void radeon_dp_set_link_config(struct drm_connector
*connector
,
450 const struct drm_display_mode
*mode
)
452 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
453 struct radeon_connector_atom_dig
*dig_connector
;
456 if (!radeon_connector
->con_priv
)
458 dig_connector
= radeon_connector
->con_priv
;
460 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
461 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
)) {
462 ret
= radeon_dp_get_dp_link_config(connector
, dig_connector
->dpcd
,
464 &dig_connector
->dp_lane_count
,
465 &dig_connector
->dp_clock
);
467 dig_connector
->dp_clock
= 0;
468 dig_connector
->dp_lane_count
= 0;
473 int radeon_dp_mode_valid_helper(struct drm_connector
*connector
,
474 struct drm_display_mode
*mode
)
476 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
477 struct radeon_connector_atom_dig
*dig_connector
;
478 unsigned dp_clock
, dp_lanes
;
481 if ((mode
->clock
> 340000) &&
482 (!radeon_connector_is_dp12_capable(connector
)))
483 return MODE_CLOCK_HIGH
;
485 if (!radeon_connector
->con_priv
)
486 return MODE_CLOCK_HIGH
;
487 dig_connector
= radeon_connector
->con_priv
;
489 ret
= radeon_dp_get_dp_link_config(connector
, dig_connector
->dpcd
,
494 return MODE_CLOCK_HIGH
;
496 if ((dp_clock
== 540000) &&
497 (!radeon_connector_is_dp12_capable(connector
)))
498 return MODE_CLOCK_HIGH
;
503 bool radeon_dp_needs_link_train(struct radeon_connector
*radeon_connector
)
505 u8 link_status
[DP_LINK_STATUS_SIZE
];
506 struct radeon_connector_atom_dig
*dig
= radeon_connector
->con_priv
;
508 if (drm_dp_dpcd_read_link_status(&radeon_connector
->ddc_bus
->aux
, link_status
)
511 if (drm_dp_channel_eq_ok(link_status
, dig
->dp_lane_count
))
516 void radeon_dp_set_rx_power_state(struct drm_connector
*connector
,
519 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
520 struct radeon_connector_atom_dig
*dig_connector
;
522 if (!radeon_connector
->con_priv
)
525 dig_connector
= radeon_connector
->con_priv
;
527 /* power up/down the sink */
528 if (dig_connector
->dpcd
[0] >= 0x11) {
529 drm_dp_dpcd_writeb(&radeon_connector
->ddc_bus
->aux
,
530 DP_SET_POWER
, power_state
);
531 usleep_range(1000, 2000);
536 struct radeon_dp_link_train_info
{
537 struct radeon_device
*rdev
;
538 struct drm_encoder
*encoder
;
539 struct drm_connector
*connector
;
544 u8 dpcd
[DP_RECEIVER_CAP_SIZE
];
546 u8 link_status
[DP_LINK_STATUS_SIZE
];
549 struct drm_dp_aux
*aux
;
552 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info
*dp_info
)
554 /* set the initial vs/emph on the source */
555 atombios_dig_transmitter_setup(dp_info
->encoder
,
556 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
,
557 0, dp_info
->train_set
[0]); /* sets all lanes at once */
559 /* set the vs/emph on the sink */
560 drm_dp_dpcd_write(dp_info
->aux
, DP_TRAINING_LANE0_SET
,
561 dp_info
->train_set
, dp_info
->dp_lane_count
);
564 static void radeon_dp_set_tp(struct radeon_dp_link_train_info
*dp_info
, int tp
)
568 /* set training pattern on the source */
569 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
) {
571 case DP_TRAINING_PATTERN_1
:
572 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1
;
574 case DP_TRAINING_PATTERN_2
:
575 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2
;
577 case DP_TRAINING_PATTERN_3
:
578 rtp
= ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3
;
581 atombios_dig_encoder_setup(dp_info
->encoder
, rtp
, 0);
584 case DP_TRAINING_PATTERN_1
:
587 case DP_TRAINING_PATTERN_2
:
591 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_PATTERN_SEL
,
592 dp_info
->dp_clock
, dp_info
->enc_id
, rtp
);
595 /* enable training pattern on the sink */
596 drm_dp_dpcd_writeb(dp_info
->aux
, DP_TRAINING_PATTERN_SET
, tp
);
599 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info
*dp_info
)
601 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(dp_info
->encoder
);
602 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
605 /* power up the sink */
606 radeon_dp_set_rx_power_state(dp_info
->connector
, DP_SET_POWER_D0
);
608 /* possibly enable downspread on the sink */
609 if (dp_info
->dpcd
[3] & 0x1)
610 drm_dp_dpcd_writeb(dp_info
->aux
,
611 DP_DOWNSPREAD_CTRL
, DP_SPREAD_AMP_0_5
);
613 drm_dp_dpcd_writeb(dp_info
->aux
,
614 DP_DOWNSPREAD_CTRL
, 0);
616 if (dig
->panel_mode
== DP_PANEL_MODE_INTERNAL_DP2_MODE
)
617 drm_dp_dpcd_writeb(dp_info
->aux
, DP_EDP_CONFIGURATION_SET
, 1);
619 /* set the lane count on the sink */
620 tmp
= dp_info
->dp_lane_count
;
621 if (drm_dp_enhanced_frame_cap(dp_info
->dpcd
))
622 tmp
|= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
623 drm_dp_dpcd_writeb(dp_info
->aux
, DP_LANE_COUNT_SET
, tmp
);
625 /* set the link rate on the sink */
626 tmp
= drm_dp_link_rate_to_bw_code(dp_info
->dp_clock
);
627 drm_dp_dpcd_writeb(dp_info
->aux
, DP_LINK_BW_SET
, tmp
);
629 /* start training on the source */
630 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
631 atombios_dig_encoder_setup(dp_info
->encoder
,
632 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START
, 0);
634 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_START
,
635 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
637 /* disable the training pattern on the sink */
638 drm_dp_dpcd_writeb(dp_info
->aux
,
639 DP_TRAINING_PATTERN_SET
,
640 DP_TRAINING_PATTERN_DISABLE
);
645 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info
*dp_info
)
649 /* disable the training pattern on the sink */
650 drm_dp_dpcd_writeb(dp_info
->aux
,
651 DP_TRAINING_PATTERN_SET
,
652 DP_TRAINING_PATTERN_DISABLE
);
654 /* disable the training pattern on the source */
655 if (ASIC_IS_DCE4(dp_info
->rdev
) || !dp_info
->use_dpencoder
)
656 atombios_dig_encoder_setup(dp_info
->encoder
,
657 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE
, 0);
659 radeon_dp_encoder_service(dp_info
->rdev
, ATOM_DP_ACTION_TRAINING_COMPLETE
,
660 dp_info
->dp_clock
, dp_info
->enc_id
, 0);
665 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info
*dp_info
)
671 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_1
);
672 memset(dp_info
->train_set
, 0, 4);
673 radeon_dp_update_vs_emph(dp_info
);
677 /* clock recovery loop */
678 clock_recovery
= false;
682 drm_dp_link_train_clock_recovery_delay(dp_info
->dpcd
);
684 if (drm_dp_dpcd_read_link_status(dp_info
->aux
,
685 dp_info
->link_status
) <= 0) {
686 DRM_ERROR("displayport link status failed\n");
690 if (drm_dp_clock_recovery_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
691 clock_recovery
= true;
695 for (i
= 0; i
< dp_info
->dp_lane_count
; i
++) {
696 if ((dp_info
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
699 if (i
== dp_info
->dp_lane_count
) {
700 DRM_ERROR("clock recovery reached max voltage\n");
704 if ((dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
706 if (dp_info
->tries
== 5) {
707 DRM_ERROR("clock recovery tried 5 times\n");
713 voltage
= dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
715 /* Compute new train_set as requested by sink */
716 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
718 radeon_dp_update_vs_emph(dp_info
);
720 if (!clock_recovery
) {
721 DRM_ERROR("clock recovery failed\n");
724 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
725 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
726 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
) >>
727 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
732 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info
*dp_info
)
736 if (dp_info
->tp3_supported
)
737 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_3
);
739 radeon_dp_set_tp(dp_info
, DP_TRAINING_PATTERN_2
);
741 /* channel equalization loop */
745 drm_dp_link_train_channel_eq_delay(dp_info
->dpcd
);
747 if (drm_dp_dpcd_read_link_status(dp_info
->aux
,
748 dp_info
->link_status
) <= 0) {
749 DRM_ERROR("displayport link status failed\n");
753 if (drm_dp_channel_eq_ok(dp_info
->link_status
, dp_info
->dp_lane_count
)) {
759 if (dp_info
->tries
> 5) {
760 DRM_ERROR("channel eq failed: 5 tries\n");
764 /* Compute new train_set as requested by sink */
765 dp_get_adjust_train(dp_info
->link_status
, dp_info
->dp_lane_count
, dp_info
->train_set
);
767 radeon_dp_update_vs_emph(dp_info
);
772 DRM_ERROR("channel eq failed\n");
775 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
776 dp_info
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
,
777 (dp_info
->train_set
[0] & DP_TRAIN_PRE_EMPHASIS_MASK
)
778 >> DP_TRAIN_PRE_EMPHASIS_SHIFT
);
783 void radeon_dp_link_train(struct drm_encoder
*encoder
,
784 struct drm_connector
*connector
)
786 struct drm_device
*dev
= encoder
->dev
;
787 struct radeon_device
*rdev
= dev
->dev_private
;
788 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
789 struct radeon_encoder_atom_dig
*dig
;
790 struct radeon_connector
*radeon_connector
;
791 struct radeon_connector_atom_dig
*dig_connector
;
792 struct radeon_dp_link_train_info dp_info
;
796 if (!radeon_encoder
->enc_priv
)
798 dig
= radeon_encoder
->enc_priv
;
800 radeon_connector
= to_radeon_connector(connector
);
801 if (!radeon_connector
->con_priv
)
803 dig_connector
= radeon_connector
->con_priv
;
805 if ((dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_DISPLAYPORT
) &&
806 (dig_connector
->dp_sink_type
!= CONNECTOR_OBJECT_ID_eDP
))
809 /* DPEncoderService newer than 1.1 can't program properly the
810 * training pattern. When facing such version use the
811 * DIGXEncoderControl (X== 1 | 2)
813 dp_info
.use_dpencoder
= true;
814 index
= GetIndexIntoMasterTable(COMMAND
, DPEncoderService
);
815 if (atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
)) {
817 dp_info
.use_dpencoder
= false;
821 if (dig
->dig_encoder
)
822 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG2_ENCODER
;
824 dp_info
.enc_id
|= ATOM_DP_CONFIG_DIG1_ENCODER
;
826 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_B
;
828 dp_info
.enc_id
|= ATOM_DP_CONFIG_LINK_A
;
830 if (drm_dp_dpcd_readb(&radeon_connector
->ddc_bus
->aux
, DP_MAX_LANE_COUNT
, &tmp
)
832 if (ASIC_IS_DCE5(rdev
) && (tmp
& DP_TPS3_SUPPORTED
))
833 dp_info
.tp3_supported
= true;
835 dp_info
.tp3_supported
= false;
837 dp_info
.tp3_supported
= false;
840 memcpy(dp_info
.dpcd
, dig_connector
->dpcd
, DP_RECEIVER_CAP_SIZE
);
842 dp_info
.encoder
= encoder
;
843 dp_info
.connector
= connector
;
844 dp_info
.dp_lane_count
= dig_connector
->dp_lane_count
;
845 dp_info
.dp_clock
= dig_connector
->dp_clock
;
846 dp_info
.aux
= &radeon_connector
->ddc_bus
->aux
;
848 if (radeon_dp_link_train_init(&dp_info
))
850 if (radeon_dp_link_train_cr(&dp_info
))
852 if (radeon_dp_link_train_ce(&dp_info
))
855 if (radeon_dp_link_train_finish(&dp_info
))